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authorSascha Hauer <s.hauer@pengutronix.de>2017-11-28 11:02:14 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-11-28 11:06:44 +0100
commit2e9cce8fb1f577088e2b20ae2f461130e13ad190 (patch)
treef82ae53e88d36e07608be1b3159da296ed025ef1 /dts/Bindings/reset
parentc68d466d263827692aa809e6b34abb90a1cab515 (diff)
downloadbarebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.gz
barebox-2e9cce8fb1f577088e2b20ae2f461130e13ad190.tar.xz
dts: update to v4.15-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/reset')
-rw-r--r--dts/Bindings/reset/allwinner,sunxi-clock-reset.txt2
-rw-r--r--dts/Bindings/reset/fsl,imx-src.txt6
-rw-r--r--dts/Bindings/reset/renesas,rst.txt1
-rw-r--r--dts/Bindings/reset/snps,axs10x-reset.txt33
-rw-r--r--dts/Bindings/reset/ti-syscon-reset.txt2
-rw-r--r--dts/Bindings/reset/uniphier-reset.txt3
6 files changed, 42 insertions, 5 deletions
diff --git a/dts/Bindings/reset/allwinner,sunxi-clock-reset.txt b/dts/Bindings/reset/allwinner,sunxi-clock-reset.txt
index c8f775714..4ca66c96f 100644
--- a/dts/Bindings/reset/allwinner,sunxi-clock-reset.txt
+++ b/dts/Bindings/reset/allwinner,sunxi-clock-reset.txt
@@ -14,7 +14,7 @@ Required properties:
example:
-ahb1_rst: reset@01c202c0 {
+ahb1_rst: reset@1c202c0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-ahb1-reset";
reg = <0x01c202c0 0xc>;
diff --git a/dts/Bindings/reset/fsl,imx-src.txt b/dts/Bindings/reset/fsl,imx-src.txt
index 13301777e..6ed79e602 100644
--- a/dts/Bindings/reset/fsl,imx-src.txt
+++ b/dts/Bindings/reset/fsl,imx-src.txt
@@ -14,7 +14,7 @@ Required properties:
example:
-src: src@020d8000 {
+src: src@20d8000 {
compatible = "fsl,imx6q-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 0x04 0 96 0x04>;
@@ -33,10 +33,10 @@ reset.txt
example:
- ipu1: ipu@02400000 {
+ ipu1: ipu@2400000 {
resets = <&src 2>;
};
- ipu2: ipu@02800000 {
+ ipu2: ipu@2800000 {
resets = <&src 4>;
};
diff --git a/dts/Bindings/reset/renesas,rst.txt b/dts/Bindings/reset/renesas,rst.txt
index e5a03ffe0..a8014f3ab 100644
--- a/dts/Bindings/reset/renesas,rst.txt
+++ b/dts/Bindings/reset/renesas,rst.txt
@@ -26,6 +26,7 @@ Required properties:
- "renesas,r8a7794-rst" (R-Car E2)
- "renesas,r8a7795-rst" (R-Car H3)
- "renesas,r8a7796-rst" (R-Car M3-W)
+ - "renesas,r8a77970-rst" (R-Car V3M)
- "renesas,r8a77995-rst" (R-Car D3)
- reg: Address start and address range for the device.
diff --git a/dts/Bindings/reset/snps,axs10x-reset.txt b/dts/Bindings/reset/snps,axs10x-reset.txt
new file mode 100644
index 000000000..32d8435a4
--- /dev/null
+++ b/dts/Bindings/reset/snps,axs10x-reset.txt
@@ -0,0 +1,33 @@
+Binding for the AXS10x reset controller
+
+This binding describes the ARC AXS10x boards custom IP-block which allows
+to control reset signals of selected peripherals. For example DW GMAC, etc...
+This block is controlled via memory-mapped register (AKA CREG) which
+represents up-to 32 reset lines.
+
+As of today only the following lines are used:
+ - DW GMAC - line 5
+
+This binding uses the common reset binding[1].
+
+[1] Documentation/devicetree/bindings/reset/reset.txt
+
+Required properties:
+- compatible: should be "snps,axs10x-reset".
+- reg: should always contain pair address - length: for creg reset
+ bits register.
+- #reset-cells: from common reset binding; Should always be set to 1.
+
+Example:
+ reset: reset-controller@11220 {
+ compatible = "snps,axs10x-reset";
+ #reset-cells = <1>;
+ reg = <0x11220 0x4>;
+ };
+
+Specifying reset lines connected to IP modules:
+ ethernet@.... {
+ ....
+ resets = <&reset 5>;
+ ....
+ };
diff --git a/dts/Bindings/reset/ti-syscon-reset.txt b/dts/Bindings/reset/ti-syscon-reset.txt
index c516d2495..86945502c 100644
--- a/dts/Bindings/reset/ti-syscon-reset.txt
+++ b/dts/Bindings/reset/ti-syscon-reset.txt
@@ -67,7 +67,7 @@ using the syscon node, and a consumer (a DSP device) on the TI Keystone 2
/ {
soc {
- psc: power-sleep-controller@02350000 {
+ psc: power-sleep-controller@2350000 {
compatible = "syscon", "simple-mfd";
reg = <0x02350000 0x1000>;
diff --git a/dts/Bindings/reset/uniphier-reset.txt b/dts/Bindings/reset/uniphier-reset.txt
index 68a6f487c..93efed629 100644
--- a/dts/Bindings/reset/uniphier-reset.txt
+++ b/dts/Bindings/reset/uniphier-reset.txt
@@ -13,6 +13,7 @@ Required properties:
"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
"socionext,uniphier-ld11-reset" - for LD11 SoC
"socionext,uniphier-ld20-reset" - for LD20 SoC
+ "socionext,uniphier-pxs3-reset" - for PXs3 SoC
- #reset-cells: should be 1.
Example:
@@ -44,6 +45,7 @@ Required properties:
"socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
"socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD)
"socionext,uniphier-ld20-sd-reset" - for LD20 SoC
+ "socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC
- #reset-cells: should be 1.
Example:
@@ -74,6 +76,7 @@ Required properties:
"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
"socionext,uniphier-ld11-peri-reset" - for LD11 SoC
"socionext,uniphier-ld20-peri-reset" - for LD20 SoC
+ "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
- #reset-cells: should be 1.
Example: