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author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-11-09 12:38:26 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-11-09 13:42:10 +0100 |
commit | 119c632f12509eab4bc58daf629c4b16fffcedca (patch) | |
tree | 34366b3095d957178b46be47f628a3926ad35ac3 /dts/Bindings/riscv/sifive-l2-cache.txt | |
parent | 89b766c63f94b5fe94db75a6f197c9e6c0f9da7e (diff) | |
download | barebox-119c632f12509eab4bc58daf629c4b16fffcedca.tar.gz barebox-119c632f12509eab4bc58daf629c4b16fffcedca.tar.xz |
dts: update to v5.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/riscv/sifive-l2-cache.txt')
-rw-r--r-- | dts/Bindings/riscv/sifive-l2-cache.txt | 51 |
1 files changed, 0 insertions, 51 deletions
diff --git a/dts/Bindings/riscv/sifive-l2-cache.txt b/dts/Bindings/riscv/sifive-l2-cache.txt deleted file mode 100644 index 73d8f19c3b..0000000000 --- a/dts/Bindings/riscv/sifive-l2-cache.txt +++ /dev/null @@ -1,51 +0,0 @@ -SiFive L2 Cache Controller --------------------------- -The SiFive Level 2 Cache Controller is used to provide access to fast copies -of memory for masters in a Core Complex. The Level 2 Cache Controller also -acts as directory-based coherency manager. -All the properties in ePAPR/DeviceTree specification applies for this platform - -Required Properties: --------------------- -- compatible: Should be "sifive,fu540-c000-ccache" and "cache" - -- cache-block-size: Specifies the block size in bytes of the cache. - Should be 64 - -- cache-level: Should be set to 2 for a level 2 cache - -- cache-sets: Specifies the number of associativity sets of the cache. - Should be 1024 - -- cache-size: Specifies the size in bytes of the cache. Should be 2097152 - -- cache-unified: Specifies the cache is a unified cache - -- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) - -- reg: Physical base address and size of L2 cache controller registers map - -Optional Properties: --------------------- -- next-level-cache: phandle to the next level cache if present. - -- memory-region: reference to the reserved-memory for the L2 Loosely Integrated - Memory region. The reserved memory node should be defined as per the bindings - in reserved-memory.txt - - -Example: - - cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; - next-level-cache = <&L25 &L40 &L36>; - memory-region = <&l2_lim>; - }; |