path: root/dts/Bindings/serial
diff options
authorSascha Hauer <>2015-12-08 07:35:17 +0100
committerSascha Hauer <>2015-12-10 08:48:40 +0100
commit6e6d9a2ff045f09d5a03e876becea5e6a1dabe90 (patch)
treebcf5e71df4472e374d03cc15ca22b4f841d9c73d /dts/Bindings/serial
parent8e2fd5380a4fd7cee428513dc8eab068912b49f1 (diff)
dts: update to v4.4-rc1
Signed-off-by: Sascha Hauer <>
Diffstat (limited to 'dts/Bindings/serial')
6 files changed, 14 insertions, 3 deletions
diff --git a/dts/Bindings/serial/ingenic,uart.txt b/dts/Bindings/serial/ingenic,uart.txt
index c2d3b3abe7..02cb7fe59c 100644
--- a/dts/Bindings/serial/ingenic,uart.txt
+++ b/dts/Bindings/serial/ingenic,uart.txt
@@ -1,7 +1,8 @@
* Ingenic SoC UART
Required properties:
-- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart"
+- compatible : "ingenic,jz4740-uart", "ingenic,jz4760-uart",
+ "ingenic,jz4775-uart" or "ingenic,jz4780-uart"
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
- clocks : phandles to the module & baud clocks.
diff --git a/dts/Bindings/serial/mrvl,pxa-ssp.txt b/dts/Bindings/serial/mrvl,pxa-ssp.txt
index 669b8140dd..d10cc06c0c 100644
--- a/dts/Bindings/serial/mrvl,pxa-ssp.txt
+++ b/dts/Bindings/serial/mrvl,pxa-ssp.txt
@@ -10,7 +10,6 @@ Required properties:
- mrvl,lpss-ssp
- reg: The memory base
- dmas: Two dma phandles, one for rx, one for tx
diff --git a/dts/Bindings/serial/pl011.txt b/dts/Bindings/serial/pl011.txt
index cbae3d9a02..77863aefe9 100644
--- a/dts/Bindings/serial/pl011.txt
+++ b/dts/Bindings/serial/pl011.txt
@@ -19,7 +19,7 @@ Optional properties:
must correspond to the PCLK clocking the internal logic
of the block. Just listing one clock (the first one) is
-- clocks-names:
+- clock-names:
When present, the first clock listed must be named
"uartclk" and the second clock listed must be named
diff --git a/dts/Bindings/serial/qcom,msm-uartdm.txt b/dts/Bindings/serial/qcom,msm-uartdm.txt
index a2114c2173..182777fac9 100644
--- a/dts/Bindings/serial/qcom,msm-uartdm.txt
+++ b/dts/Bindings/serial/qcom,msm-uartdm.txt
@@ -26,6 +26,12 @@ Required properties:
Optional properties:
- dmas: Should contain dma specifiers for transmit and receive channels
- dma-names: Should contain "tx" for transmit and "rx" for receive channels
+- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be
+ used with TX DMA channel. Required when using DMA for transmission
+ with UARTDM v1.3 and bellow.
+- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be
+ used with RX DMA channel. Required when using DMA for reception
+ with UARTDM v1.3 and bellow.
Note: Aliases may be defined to ensure the correct ordering of the UARTs.
The alias serialN will result in the UART being assigned port N. If any
diff --git a/dts/Bindings/serial/renesas,sci-serial.txt b/dts/Bindings/serial/renesas,sci-serial.txt
index e84b13a8ed..73f825e5e6 100644
--- a/dts/Bindings/serial/renesas,sci-serial.txt
+++ b/dts/Bindings/serial/renesas,sci-serial.txt
@@ -23,6 +23,8 @@ Required properties:
- "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
- "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
- "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART.
+ - "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART.
+ - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
- "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
- "renesas,scif" for generic SCIF compatible UART.
diff --git a/dts/Bindings/serial/snps-dw-apb-uart.txt b/dts/Bindings/serial/snps-dw-apb-uart.txt
index 289c40ed74..12bbe9f225 100644
--- a/dts/Bindings/serial/snps-dw-apb-uart.txt
+++ b/dts/Bindings/serial/snps-dw-apb-uart.txt
@@ -15,6 +15,9 @@ The supplying peripheral clock can also be handled, needing a second property
Required elements: "baudclk", "apb_pclk"
Optional properties:
+- snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
+ configuration parameter. Define this if your UART does not implement the busy
+ functionality.
- resets : phandle to the parent reset controller.
- reg-shift : quantity to shift the register offsets by. If this property is
not present then the register offsets are not shifted.