summaryrefslogtreecommitdiffstats
path: root/dts/Bindings/spi/jcore,spi.txt
diff options
context:
space:
mode:
authorSascha Hauer <s.hauer@pengutronix.de>2016-10-18 10:10:24 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-10-18 10:10:24 +0200
commitbfbf18d991756858337f7700e8ff0a6f0dc31afc (patch)
treecf3568de4fdff1891e277507f08f49a871682706 /dts/Bindings/spi/jcore,spi.txt
parent834f6bf5e5f1169065376ad1aeb6a6266e66ce5c (diff)
downloadbarebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.gz
barebox-bfbf18d991756858337f7700e8ff0a6f0dc31afc.tar.xz
dts: update to v4.9-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/spi/jcore,spi.txt')
-rw-r--r--dts/Bindings/spi/jcore,spi.txt34
1 files changed, 34 insertions, 0 deletions
diff --git a/dts/Bindings/spi/jcore,spi.txt b/dts/Bindings/spi/jcore,spi.txt
new file mode 100644
index 0000000000..93936d16e1
--- /dev/null
+++ b/dts/Bindings/spi/jcore,spi.txt
@@ -0,0 +1,34 @@
+J-Core SPI master
+
+Required properties:
+
+- compatible: Must be "jcore,spi2".
+
+- reg: Memory region for registers.
+
+- #address-cells: Must be 1.
+
+- #size-cells: Must be 0.
+
+Optional properties:
+
+- clocks: If a phandle named "ref_clk" is present, SPI clock speed
+ programming is relative to the frequency of the indicated clock.
+ Necessary only if the input clock rate is something other than a
+ fixed 50 MHz.
+
+- clock-names: Clock names, one for each phandle in clocks.
+
+See spi-bus.txt for additional properties not specific to this device.
+
+Example:
+
+spi@40 {
+ compatible = "jcore,spi2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40 0x8>;
+ spi-max-frequency = <25000000>;
+ clocks = <&bus_clk>;
+ clock-names = "ref_clk";
+}