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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-03-03 08:11:01 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-03-03 08:11:01 +0100 |
| commit | eaa819409db6ac80fbd7c3d36450b2d1bec93576 (patch) | |
| tree | 6cd5e0c7f8abe121af237b701ee9e0e1b6f7e40d /dts/Bindings/timer | |
| parent | 0c9aadb6185e1d84746b632284bc89e4e4c80cd3 (diff) | |
| download | barebox-eaa819409db6ac80fbd7c3d36450b2d1bec93576.tar.gz barebox-eaa819409db6ac80fbd7c3d36450b2d1bec93576.tar.xz | |
dts: update to v4.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/timer')
| -rw-r--r-- | dts/Bindings/timer/digicolor-timer.txt | 18 | ||||
| -rw-r--r-- | dts/Bindings/timer/nvidia,tegra30-timer.txt | 4 | ||||
| -rw-r--r-- | dts/Bindings/timer/rockchip,rk3288-timer.txt | 18 |
3 files changed, 39 insertions, 1 deletions
diff --git a/dts/Bindings/timer/digicolor-timer.txt b/dts/Bindings/timer/digicolor-timer.txt new file mode 100644 index 0000000000..d1b659bbc2 --- /dev/null +++ b/dts/Bindings/timer/digicolor-timer.txt @@ -0,0 +1,18 @@ +Conexant Digicolor SoCs Timer Controller + +Required properties: + +- compatible : should be "cnxt,cx92755-timer" +- reg : Specifies base physical address and size of the "Agent Communication" + timer registers +- interrupts : Contains 8 interrupts, one for each timer +- clocks: phandle to the main clock + +Example: + + timer@f0000fc0 { + compatible = "cnxt,cx92755-timer"; + reg = <0xf0000fc0 0x40>; + interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>; + clocks = <&main_clk>; + }; diff --git a/dts/Bindings/timer/nvidia,tegra30-timer.txt b/dts/Bindings/timer/nvidia,tegra30-timer.txt index b5082a1cf4..1761f53ee3 100644 --- a/dts/Bindings/timer/nvidia,tegra30-timer.txt +++ b/dts/Bindings/timer/nvidia,tegra30-timer.txt @@ -6,7 +6,9 @@ trigger a legacy watchdog reset. Required properties: -- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer". +- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise, + must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where + <chip> is tegra124 or tegra132. - reg : Specifies base physical address and size of the registers. - interrupts : A list of 6 interrupts; one per each of timer channels 1 through 5, and one for the shared interrupt for the remaining channels. diff --git a/dts/Bindings/timer/rockchip,rk3288-timer.txt b/dts/Bindings/timer/rockchip,rk3288-timer.txt new file mode 100644 index 0000000000..87f0b0042b --- /dev/null +++ b/dts/Bindings/timer/rockchip,rk3288-timer.txt @@ -0,0 +1,18 @@ +Rockchip rk3288 timer + +Required properties: +- compatible: shall be "rockchip,rk3288-timer" +- reg: base address of the timer register starting with TIMERS CONTROL register +- interrupts: should contain the interrupts for Timer0 +- clocks : must contain an entry for each entry in clock-names +- clock-names : must include the following entries: + "timer", "pclk" + +Example: + timer: timer@ff810000 { + compatible = "rockchip,rk3288-timer"; + reg = <0xff810000 0x20>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>, <&cru PCLK_TIMER>; + clock-names = "timer", "pclk"; + }; |