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author | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-14 09:09:57 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-14 09:09:57 +0100 |
commit | 33fdc89d4cbd74aa54c28dc61d62972ab164e64d (patch) | |
tree | da5ceff551dc1fdf2f2cc40e97a08035f9ef84fb /dts/Bindings/ufs | |
parent | 13a52906ce67ed2ce67bfc10714934ffa6c5d646 (diff) | |
download | barebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.gz barebox-33fdc89d4cbd74aa54c28dc61d62972ab164e64d.tar.xz |
dts: update to v5.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings/ufs')
-rw-r--r-- | dts/Bindings/ufs/cdns,ufshc.txt | 31 | ||||
-rw-r--r-- | dts/Bindings/ufs/ufshcd-pltfrm.txt | 6 |
2 files changed, 37 insertions, 0 deletions
diff --git a/dts/Bindings/ufs/cdns,ufshc.txt b/dts/Bindings/ufs/cdns,ufshc.txt new file mode 100644 index 0000000000..a04a4989ec --- /dev/null +++ b/dts/Bindings/ufs/cdns,ufshc.txt @@ -0,0 +1,31 @@ +* Cadence Universal Flash Storage (UFS) Controller + +UFS nodes are defined to describe on-chip UFS host controllers. +Each UFS controller instance should have its own node. +Please see the ufshcd-pltfrm.txt for a list of all available properties. + +Required properties: +- compatible : Compatible list, contains the following controller: + "cdns,ufshc" + complemented with the JEDEC version: + "jedec,ufs-2.0" + +- reg : Address and length of the UFS register set. +- interrupts : One interrupt mapping. +- freq-table-hz : Clock frequency table. + See the ufshcd-pltfrm.txt for details. +- clocks : List of phandle and clock specifier pairs. +- clock-names : List of clock input name strings sorted in the same + order as the clocks property. "core_clk" is mandatory. + Depending on a type of a PHY, + the "phy_clk" clock can also be added, if needed. + +Example: + ufs@fd030000 { + compatible = "cdns,ufshc", "jedec,ufs-2.0"; + reg = <0xfd030000 0x10000>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; + freq-table-hz = <0 0>, <0 0>; + clocks = <&ufs_core_clk>, <&ufs_phy_clk>; + clock-names = "core_clk", "phy_clk"; + }; diff --git a/dts/Bindings/ufs/ufshcd-pltfrm.txt b/dts/Bindings/ufs/ufshcd-pltfrm.txt index 2df00524bd..8cf59452c6 100644 --- a/dts/Bindings/ufs/ufshcd-pltfrm.txt +++ b/dts/Bindings/ufs/ufshcd-pltfrm.txt @@ -33,6 +33,12 @@ Optional properties: - clocks : List of phandle and clock specifier pairs - clock-names : List of clock input name strings sorted in the same order as the clocks property. + "ref_clk" indicates reference clock frequency. + UFS host supplies reference clock to UFS device and UFS device + specification allows host to provide one of the 4 frequencies (19.2 MHz, + 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is + parsed and used to update the reference clock setting in device. + Defaults to 26 MHz(as per specification) if not specified by host. - freq-table-hz : Array of <min max> operating frequencies stored in the same order as the clocks property. If this property is not defined or a value in the array is "0" then it is assumed |