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authorSascha Hauer <s.hauer@pengutronix.de>2019-08-19 08:56:07 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-08-19 08:56:07 +0200
commit2aab3dbb7e3d6dc24bf82a949ab4372a8d7e30e6 (patch)
tree13ae4927106696992ab8a0d8b1e362ceee6268c2 /dts/Bindings
parenta3e62ffc7341254fd754886e560865556bc731c8 (diff)
downloadbarebox-2aab3dbb7e3d6dc24bf82a949ab4372a8d7e30e6.tar.gz
dts: update to v5.2-rc7
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
-rw-r--r--dts/Bindings/riscv/cpus.yaml26
1 files changed, 14 insertions, 12 deletions
diff --git a/dts/Bindings/riscv/cpus.yaml b/dts/Bindings/riscv/cpus.yaml
index 27f02ec..f97a4ec 100644
--- a/dts/Bindings/riscv/cpus.yaml
+++ b/dts/Bindings/riscv/cpus.yaml
@@ -152,17 +152,19 @@ examples:
- |
// Example 2: Spike ISA Simulator with 1 Hart
cpus {
- cpu@0 {
- device_type = "cpu";
- reg = <0>;
- compatible = "riscv";
- riscv,isa = "rv64imafdc";
- mmu-type = "riscv,sv48";
- interrupt-controller {
- #interrupt-cells = <1>;
- interrupt-controller;
- compatible = "riscv,cpu-intc";
- };
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv48";
+ interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
};
...