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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 08:26:36 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-09-11 17:23:13 +0200 |
| commit | 6acd8ef6ccebfcd42e0ede49d6034beeb48b425a (patch) | |
| tree | 77ca233504153b50d7931e2af727fdc0dcecd943 /dts/Bindings | |
| parent | 35f607bc7da71b302fd6bf3d6d48d7ea66df1195 (diff) | |
| download | barebox-6acd8ef6ccebfcd42e0ede49d6034beeb48b425a.tar.gz barebox-6acd8ef6ccebfcd42e0ede49d6034beeb48b425a.tar.xz | |
dts: update to v4.19-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
| -rw-r--r-- | dts/Bindings/interrupt-controller/riscv,cpu-intc.txt | 14 | ||||
| -rw-r--r-- | dts/Bindings/watchdog/renesas-wdt.txt | 5 |
2 files changed, 14 insertions, 5 deletions
diff --git a/dts/Bindings/interrupt-controller/riscv,cpu-intc.txt b/dts/Bindings/interrupt-controller/riscv,cpu-intc.txt index b0a8af51c3..265b223cd9 100644 --- a/dts/Bindings/interrupt-controller/riscv,cpu-intc.txt +++ b/dts/Bindings/interrupt-controller/riscv,cpu-intc.txt @@ -11,7 +11,7 @@ The RISC-V supervisor ISA manual specifies three interrupt sources that are attached to every HLIC: software interrupts, the timer interrupt, and external interrupts. Software interrupts are used to send IPIs between cores. The timer interrupt comes from an architecturally mandated real-time timer that is -controller via Supervisor Binary Interface (SBI) calls and CSR reads. External +controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External interrupts connect all other device interrupts to the HLIC, which are routed via the platform-level interrupt controller (PLIC). @@ -25,7 +25,15 @@ in the system. Required properties: - compatible : "riscv,cpu-intc" -- #interrupt-cells : should be <1> +- #interrupt-cells : should be <1>. The interrupt sources are defined by the + RISC-V supervisor ISA manual, with only the following three interrupts being + defined for supervisor mode: + - Source 1 is the supervisor software interrupt, which can be sent by an SBI + call and is reserved for use by software. + - Source 5 is the supervisor timer interrupt, which can be configured by + SBI calls and implements a one-shot timer. + - Source 9 is the supervisor external interrupt, which chains to all other + device interrupts. - interrupt-controller : Identifies the node as an interrupt controller Furthermore, this interrupt-controller MUST be embedded inside the cpu @@ -38,7 +46,7 @@ An example device tree entry for a HLIC is show below. ... cpu1-intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc", "sifive,fu540-c000-cpu-intc"; + compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; diff --git a/dts/Bindings/watchdog/renesas-wdt.txt b/dts/Bindings/watchdog/renesas-wdt.txt index 5d47a26247..9407212a85 100644 --- a/dts/Bindings/watchdog/renesas-wdt.txt +++ b/dts/Bindings/watchdog/renesas-wdt.txt @@ -7,6 +7,7 @@ Required properties: Examples with soctypes are: - "renesas,r8a7743-wdt" (RZ/G1M) - "renesas,r8a7745-wdt" (RZ/G1E) + - "renesas,r8a774a1-wdt" (RZ/G2M) - "renesas,r8a7790-wdt" (R-Car H2) - "renesas,r8a7791-wdt" (R-Car M2-W) - "renesas,r8a7792-wdt" (R-Car V2H) @@ -21,8 +22,8 @@ Required properties: - "renesas,r7s72100-wdt" (RZ/A1) The generic compatible string must be: - "renesas,rza-wdt" for RZ/A - - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G - - "renesas,rcar-gen3-wdt" for R-Car Gen3 + - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G1 + - "renesas,rcar-gen3-wdt" for R-Car Gen3 and RZ/G2 - reg : Should contain WDT registers location and length - clocks : the clock feeding the watchdog timer. |