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authorSascha Hauer <s.hauer@pengutronix.de>2019-06-05 00:06:34 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-06-11 09:11:15 +0200
commitfffb86c826e95679abf0b5d8b90794c39218182e (patch)
tree6e3e2ba255349895dcf3f119a7c10faf3977ce35 /dts/Bindings
parent796af3473b8222bcd89aa63e9886c355a6baf95d (diff)
downloadbarebox-fffb86c826e95679abf0b5d8b90794c39218182e.tar.gz
dts: update to v5.2-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/Bindings')
-rw-r--r--dts/Bindings/Makefile2
-rw-r--r--dts/Bindings/arm/arm-boards4
-rw-r--r--dts/Bindings/arm/cpu-capacity.txt12
-rw-r--r--dts/Bindings/arm/omap/crossbar.txt2
-rw-r--r--dts/Bindings/clock/samsung,s5pv210-clock.txt2
-rw-r--r--dts/Bindings/interrupt-controller/arm,gic.yaml24
-rw-r--r--dts/Bindings/interrupt-controller/marvell,odmi-controller.txt2
-rw-r--r--dts/Bindings/leds/irled/spi-ir-led.txt2
-rw-r--r--dts/Bindings/mtd/amlogic,meson-nand.txt2
-rw-r--r--dts/Bindings/mtd/brcm,brcmnand.txt6
-rw-r--r--dts/Bindings/mtd/denali-nand.txt6
-rw-r--r--dts/Bindings/mtd/fsmc-nand.txt6
-rw-r--r--dts/Bindings/mtd/gpmc-nand.txt2
-rw-r--r--dts/Bindings/mtd/hisi504-nand.txt2
-rw-r--r--dts/Bindings/mtd/marvell-nand.txt14
-rw-r--r--dts/Bindings/mtd/mxc-nand.txt6
-rw-r--r--dts/Bindings/mtd/nvidia-tegra20-nand.txt6
-rw-r--r--dts/Bindings/mtd/oxnas-nand.txt2
-rw-r--r--dts/Bindings/mtd/qcom_nandc.txt4
-rw-r--r--dts/Bindings/mtd/samsung-s3c2410.txt6
-rw-r--r--dts/Bindings/mtd/stm32-fmc2-nand.txt6
-rw-r--r--dts/Bindings/mtd/tango-nand.txt2
-rw-r--r--dts/Bindings/mtd/vf610-nfc.txt8
-rw-r--r--dts/Bindings/sifive/sifive-blocks-ip-versioning.txt38
24 files changed, 103 insertions, 63 deletions
diff --git a/dts/Bindings/Makefile b/dts/Bindings/Makefile
index 63b139f..8a2774b 100644
--- a/dts/Bindings/Makefile
+++ b/dts/Bindings/Makefile
@@ -5,7 +5,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
DT_MK_SCHEMA_FLAGS := $(if $(DT_SCHEMA_FILES), -u)
quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
- cmd_chk_binding = $(DT_DOC_CHECKER) $< ; \
+ cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
$(DT_EXTRACT_EX) $< > $@
$(obj)/%.example.dts: $(src)/%.yaml FORCE
diff --git a/dts/Bindings/arm/arm-boards b/dts/Bindings/arm/arm-boards
index b6e810c..abff8d8 100644
--- a/dts/Bindings/arm/arm-boards
+++ b/dts/Bindings/arm/arm-boards
@@ -216,7 +216,7 @@ Example:
#size-cells = <0>;
A57_0: cpu@0 {
- compatible = "arm,cortex-a57","arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
@@ -225,7 +225,7 @@ Example:
.....
A53_0: cpu@100 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
diff --git a/dts/Bindings/arm/cpu-capacity.txt b/dts/Bindings/arm/cpu-capacity.txt
index 96fa46c..380e21c 100644
--- a/dts/Bindings/arm/cpu-capacity.txt
+++ b/dts/Bindings/arm/cpu-capacity.txt
@@ -118,7 +118,7 @@ cpus {
};
A57_0: cpu@0 {
- compatible = "arm,cortex-a57","arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
@@ -129,7 +129,7 @@ cpus {
};
A57_1: cpu@1 {
- compatible = "arm,cortex-a57","arm,armv8";
+ compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
@@ -140,7 +140,7 @@ cpus {
};
A53_0: cpu@100 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
@@ -151,7 +151,7 @@ cpus {
};
A53_1: cpu@101 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
@@ -162,7 +162,7 @@ cpus {
};
A53_2: cpu@102 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
@@ -173,7 +173,7 @@ cpus {
};
A53_3: cpu@103 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
diff --git a/dts/Bindings/arm/omap/crossbar.txt b/dts/Bindings/arm/omap/crossbar.txt
index 4cd5d87..a43e4c7 100644
--- a/dts/Bindings/arm/omap/crossbar.txt
+++ b/dts/Bindings/arm/omap/crossbar.txt
@@ -41,7 +41,7 @@ Examples:
Consumer:
========
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
-Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
+Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for
further details.
An interrupt consumer on an SoC using crossbar will use:
diff --git a/dts/Bindings/clock/samsung,s5pv210-clock.txt b/dts/Bindings/clock/samsung,s5pv210-clock.txt
index 15b48e2..a86c83b 100644
--- a/dts/Bindings/clock/samsung,s5pv210-clock.txt
+++ b/dts/Bindings/clock/samsung,s5pv210-clock.txt
@@ -35,7 +35,7 @@ board device tree, including the system base clock, as selected by XOM[0]
pin of the SoC. Refer to generic fixed rate clock bindings
documentation[1] for more information how to specify these clocks.
-[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
+[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml
Example: Clock controller node:
diff --git a/dts/Bindings/interrupt-controller/arm,gic.yaml b/dts/Bindings/interrupt-controller/arm,gic.yaml
index 54838d4..9a47820 100644
--- a/dts/Bindings/interrupt-controller/arm,gic.yaml
+++ b/dts/Bindings/interrupt-controller/arm,gic.yaml
@@ -92,6 +92,8 @@ properties:
minItems: 2
maxItems: 4
+ ranges: true
+
interrupts:
description: Interrupt source of the parent interrupt controller on
secondary GICs, or VGIC maintenance interrupt on primary GIC (see
@@ -197,28 +199,28 @@ examples:
interrupt-controller@e1101000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
interrupt-controller;
interrupts = <1 8 0xf04>;
- ranges = <0 0 0 0xe1100000 0 0x100000>;
- reg = <0x0 0xe1110000 0 0x01000>,
- <0x0 0xe112f000 0 0x02000>,
- <0x0 0xe1140000 0 0x10000>,
- <0x0 0xe1160000 0 0x10000>;
+ ranges = <0 0xe1100000 0x100000>;
+ reg = <0xe1110000 0x01000>,
+ <0xe112f000 0x02000>,
+ <0xe1140000 0x10000>,
+ <0xe1160000 0x10000>;
- v2m0: v2m@8000 {
+ v2m0: v2m@80000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
- reg = <0x0 0x80000 0 0x1000>;
+ reg = <0x80000 0x1000>;
};
//...
- v2mN: v2m@9000 {
+ v2mN: v2m@90000 {
compatible = "arm,gic-v2m-frame";
msi-controller;
- reg = <0x0 0x90000 0 0x1000>;
+ reg = <0x90000 0x1000>;
};
};
...
diff --git a/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt b/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt
index 930fb46..0ebfc95 100644
--- a/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt
+++ b/dts/Bindings/interrupt-controller/marvell,odmi-controller.txt
@@ -23,7 +23,7 @@ Required properties:
- marvell,spi-base : List of GIC base SPI interrupts, one for each
ODMI frame. Those SPI interrupts are 0-based,
i.e marvell,spi-base = <128> will use SPI #96.
- See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+ See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
for details about the GIC Device Tree binding.
Example:
diff --git a/dts/Bindings/leds/irled/spi-ir-led.txt b/dts/Bindings/leds/irled/spi-ir-led.txt
index 896b699..21882c8 100644
--- a/dts/Bindings/leds/irled/spi-ir-led.txt
+++ b/dts/Bindings/leds/irled/spi-ir-led.txt
@@ -15,7 +15,7 @@ Optional properties:
- power-supply: specifies the power source. It can either be a regulator
or a gpio which enables a regulator, i.e. a regulator-fixed as
described in
- Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+ Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
Example:
diff --git a/dts/Bindings/mtd/amlogic,meson-nand.txt b/dts/Bindings/mtd/amlogic,meson-nand.txt
index 3983c11..5794ab1 100644
--- a/dts/Bindings/mtd/amlogic,meson-nand.txt
+++ b/dts/Bindings/mtd/amlogic,meson-nand.txt
@@ -24,7 +24,7 @@ Optional children nodes:
Children nodes represent the available nand chips.
Other properties:
-see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
Example demonstrate on AXG SoC:
diff --git a/dts/Bindings/mtd/brcm,brcmnand.txt b/dts/Bindings/mtd/brcm,brcmnand.txt
index bcda1df..0b7c373 100644
--- a/dts/Bindings/mtd/brcm,brcmnand.txt
+++ b/dts/Bindings/mtd/brcm,brcmnand.txt
@@ -101,12 +101,12 @@ Required properties:
number (e.g., 0, 1, 2, etc.)
- #address-cells : see partition.txt
- #size-cells : see partition.txt
-- nand-ecc-strength : see nand.txt
-- nand-ecc-step-size : must be 512 or 1024. See nand.txt
+- nand-ecc-strength : see nand-controller.yaml
+- nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
Optional properties:
- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
- chip-select. See nand.txt
+ chip-select. See nand-controller.yaml
- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
expected for the ECC layout in use. This size, in
addition to the strength and step-size,
diff --git a/dts/Bindings/mtd/denali-nand.txt b/dts/Bindings/mtd/denali-nand.txt
index b14b675..b32aed1 100644
--- a/dts/Bindings/mtd/denali-nand.txt
+++ b/dts/Bindings/mtd/denali-nand.txt
@@ -22,16 +22,16 @@ Sub-nodes:
select is connected.
Optional properties:
- - nand-ecc-step-size: see nand.txt for details.
+ - nand-ecc-step-size: see nand-controller.yaml for details.
If present, the value must be
512 for "altr,socfpga-denali-nand"
1024 for "socionext,uniphier-denali-nand-v5a"
1024 for "socionext,uniphier-denali-nand-v5b"
- - nand-ecc-strength: see nand.txt for details. Valid values are:
+ - nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
8, 15 for "altr,socfpga-denali-nand"
8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
8, 16 for "socionext,uniphier-denali-nand-v5b"
- - nand-ecc-maximize: see nand.txt for details
+ - nand-ecc-maximize: see nand-controller.yaml for details
The chip nodes may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
diff --git a/dts/Bindings/mtd/fsmc-nand.txt b/dts/Bindings/mtd/fsmc-nand.txt
index 32636eb..6762d3c 100644
--- a/dts/Bindings/mtd/fsmc-nand.txt
+++ b/dts/Bindings/mtd/fsmc-nand.txt
@@ -30,9 +30,9 @@ Optional properties:
command is asserted. Zero means one cycle, 255 means 256
cycles.
- bank: default NAND bank to use (0-3 are valid, 0 is the default).
-- nand-ecc-mode : see nand.txt
-- nand-ecc-strength : see nand.txt
-- nand-ecc-step-size : see nand.txt
+- nand-ecc-mode : see nand-controller.yaml
+- nand-ecc-strength : see nand-controller.yaml
+- nand-ecc-step-size : see nand-controller.yaml
Can support 1-bit HW ECC (default) or if stronger correction is required,
software-based BCH.
diff --git a/dts/Bindings/mtd/gpmc-nand.txt b/dts/Bindings/mtd/gpmc-nand.txt
index c059ab7..44919d4 100644
--- a/dts/Bindings/mtd/gpmc-nand.txt
+++ b/dts/Bindings/mtd/gpmc-nand.txt
@@ -8,7 +8,7 @@ explained in a separate documents - please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
For NAND specific properties such as ECC modes or bus width, please refer to
-Documentation/devicetree/bindings/mtd/nand.txt
+Documentation/devicetree/bindings/mtd/nand-controller.yaml
Required properties:
diff --git a/dts/Bindings/mtd/hisi504-nand.txt b/dts/Bindings/mtd/hisi504-nand.txt
index 2e35f06..8963983 100644
--- a/dts/Bindings/mtd/hisi504-nand.txt
+++ b/dts/Bindings/mtd/hisi504-nand.txt
@@ -7,7 +7,7 @@ Required properties:
NAND controller's registers. The second contains base
physical address and size of NAND controller's buffer.
- interrupts: Interrupt number for nfc.
-- nand-bus-width: See nand.txt.
+- nand-bus-width: See nand-controller.yaml.
- nand-ecc-mode: Support none and hw ecc mode.
- #address-cells: Partition address, should be set 1.
- #size-cells: Partition size, should be set 1.
diff --git a/dts/Bindings/mtd/marvell-nand.txt b/dts/Bindings/mtd/marvell-nand.txt
index e0c7907..a2d9a0f 100644
--- a/dts/Bindings/mtd/marvell-nand.txt
+++ b/dts/Bindings/mtd/marvell-nand.txt
@@ -36,29 +36,29 @@ Children nodes represent the available NAND chips.
Required properties:
- reg: shall contain the native Chip Select ids (0-3).
-- nand-rb: see nand.txt (0-1).
+- nand-rb: see nand-controller.yaml (0-1).
Optional properties:
- marvell,nand-keep-config: orders the driver not to take the timings
from the core and leaving them completely untouched. Bootloader
timings will then be used.
- label: MTD name.
-- nand-on-flash-bbt: see nand.txt.
-- nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
-- nand-ecc-algo: see nand.txt. This property is essentially useful when
+- nand-on-flash-bbt: see nand-controller.yaml.
+- nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
+- nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
not using hardware ECC. Howerver, it may be added when using hardware
ECC for clarification but will be ignored by the driver because ECC
mode is chosen depending on the page size and the strength required by
the NAND chip. This value may be overwritten with nand-ecc-strength
property.
-- nand-ecc-strength: see nand.txt.
-- nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
+- nand-ecc-strength: see nand-controller.yaml.
+- nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
step size will shrink or grow in order to fit the required strength.
Step sizes are not completely random for all and follow certain
patterns described in AN-379, "Marvell SoC NFC ECC".
-See Documentation/devicetree/bindings/mtd/nand.txt for more details on
+See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
generic bindings.
diff --git a/dts/Bindings/mtd/mxc-nand.txt b/dts/Bindings/mtd/mxc-nand.txt
index b5833d1..2857c62 100644
--- a/dts/Bindings/mtd/mxc-nand.txt
+++ b/dts/Bindings/mtd/mxc-nand.txt
@@ -4,9 +4,9 @@ Required properties:
- compatible: "fsl,imxXX-nand"
- reg: address range of the nfc block
- interrupts: irq to be used
-- nand-bus-width: see nand.txt
-- nand-ecc-mode: see nand.txt
-- nand-on-flash-bbt: see nand.txt
+- nand-bus-width: see nand-controller.yaml
+- nand-ecc-mode: see nand-controller.yaml
+- nand-on-flash-bbt: see nand-controller.yaml
Example:
diff --git a/dts/Bindings/mtd/nvidia-tegra20-nand.txt b/dts/Bindings/mtd/nvidia-tegra20-nand.txt
index b2f2ca1..e737e5b 100644
--- a/dts/Bindings/mtd/nvidia-tegra20-nand.txt
+++ b/dts/Bindings/mtd/nvidia-tegra20-nand.txt
@@ -26,14 +26,14 @@ Optional children node properties:
"hw" is supported.
- nand-ecc-algo: string, algorithm of NAND ECC.
Supported values with "hw" ECC mode are: "rs", "bch".
-- nand-bus-width : See nand.txt
-- nand-on-flash-bbt: See nand.txt
+- nand-bus-width : See nand-controller.yaml
+- nand-on-flash-bbt: See nand-controller.yaml
- nand-ecc-strength: integer representing the number of bits to correct
per ECC step (always 512). Supported strength using HW ECC
modes are:
- RS: 4, 6, 8
- BCH: 4, 8, 14, 16
-- nand-ecc-maximize: See nand.txt
+- nand-ecc-maximize: See nand-controller.yaml
- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
are chosen.
- wp-gpios: GPIO specifier for the write protect pin.
diff --git a/dts/Bindings/mtd/oxnas-nand.txt b/dts/Bindings/mtd/oxnas-nand.txt
index 56d5c19..2ba07fc 100644
--- a/dts/Bindings/mtd/oxnas-nand.txt
+++ b/dts/Bindings/mtd/oxnas-nand.txt
@@ -1,6 +1,6 @@
* Oxford Semiconductor OXNAS NAND Controller
-Please refer to nand.txt for generic information regarding MTD NAND bindings.
+Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
Required properties:
- compatible: "oxsemi,ox820-nand"
diff --git a/dts/Bindings/mtd/qcom_nandc.txt b/dts/Bindings/mtd/qcom_nandc.txt
index 1123cc6..5c2fba4 100644
--- a/dts/Bindings/mtd/qcom_nandc.txt
+++ b/dts/Bindings/mtd/qcom_nandc.txt
@@ -47,8 +47,8 @@ Required properties:
- #size-cells: see partition.txt
Optional properties:
-- nand-bus-width: see nand.txt
-- nand-ecc-strength: see nand.txt. If not specified, then ECC strength will
+- nand-bus-width: see nand-controller.yaml
+- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
be used according to chip requirement and available
OOB size.
diff --git a/dts/Bindings/mtd/samsung-s3c2410.txt b/dts/Bindings/mtd/samsung-s3c2410.txt
index 0040eb8..09815c4 100644
--- a/dts/Bindings/mtd/samsung-s3c2410.txt
+++ b/dts/Bindings/mtd/samsung-s3c2410.txt
@@ -6,7 +6,7 @@ Required properties:
"samsung,s3c2412-nand"
"samsung,s3c2440-nand"
- reg : register's location and length.
-- #address-cells, #size-cells : see nand.txt
+- #address-cells, #size-cells : see nand-controller.yaml
- clocks : phandle to the nand controller clock
- clock-names : must contain "nand"
@@ -14,8 +14,8 @@ Optional child nodes:
Child nodes representing the available nand chips.
Optional child properties:
-- nand-ecc-mode : see nand.txt
-- nand-on-flash-bbt : see nand.txt
+- nand-ecc-mode : see nand-controller.yaml
+- nand-on-flash-bbt : see nand-controller.yaml
Each child device node may optionally contain a 'partitions' sub-node,
which further contains sub-nodes describing the flash partition mapping.
diff --git a/dts/Bindings/mtd/stm32-fmc2-nand.txt b/dts/Bindings/mtd/stm32-fmc2-nand.txt
index ad2bef8..e55895e 100644
--- a/dts/Bindings/mtd/stm32-fmc2-nand.txt
+++ b/dts/Bindings/mtd/stm32-fmc2-nand.txt
@@ -24,9 +24,9 @@ Required properties:
- reg: describes the CS lines assigned to the NAND device.
Optional properties:
-- nand-on-flash-bbt: see nand.txt
-- nand-ecc-strength: see nand.txt
-- nand-ecc-step-size: see nand.txt
+- nand-on-flash-bbt: see nand-controller.yaml
+- nand-ecc-strength: see nand-controller.yaml
+- nand-ecc-step-size: see nand-controller.yaml
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
diff --git a/dts/Bindings/mtd/tango-nand.txt b/dts/Bindings/mtd/tango-nand.txt
index cd1bf2a..91c8420 100644
--- a/dts/Bindings/mtd/tango-nand.txt
+++ b/dts/Bindings/mtd/tango-nand.txt
@@ -11,7 +11,7 @@ Required properties:
- #size-cells: <0>
Children nodes represent the available NAND chips.
-See Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
+See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
Example:
diff --git a/dts/Bindings/mtd/vf610-nfc.txt b/dts/Bindings/mtd/vf610-nfc.txt
index c96eeb6..7db5e6e 100644
--- a/dts/Bindings/mtd/vf610-nfc.txt
+++ b/dts/Bindings/mtd/vf610-nfc.txt
@@ -25,14 +25,14 @@ only handle one NAND chip.
Required properties:
- compatible: Should be set to "fsl,vf610-nfc-cs".
-- nand-bus-width: see nand.txt
-- nand-ecc-mode: see nand.txt
+- nand-bus-width: see nand-controller.yaml
+- nand-ecc-mode: see nand-controller.yaml
Required properties for hardware ECC:
-- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt)
+- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
- nand-ecc-step-size: step size equals page size, currently only 2k pages are
supported
-- nand-on-flash-bbt: see nand.txt
+- nand-on-flash-bbt: see nand-controller.yaml
Example:
diff --git a/dts/Bindings/sifive/sifive-blocks-ip-versioning.txt b/dts/Bindings/sifive/sifive-blocks-ip-versioning.txt
new file mode 100644
index 0000000..beaa3b6
--- /dev/null
+++ b/dts/Bindings/sifive/sifive-blocks-ip-versioning.txt
@@ -0,0 +1,38 @@
+DT compatible string versioning for SiFive open-source IP blocks
+
+This document describes the version specification for DT "compatible"
+strings for open-source SiFive IP blocks. HDL for these IP blocks
+can be found in this public repository:
+
+https://github.com/sifive/sifive-blocks
+
+IP block-specific DT compatible strings are contained within the HDL,
+in the form "sifive,<ip-block-name><integer version number>".
+
+An example is "sifive,uart0" from:
+
+https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
+
+Until these IP blocks (or IP integration) support version
+auto-discovery, the maintainers of these IP blocks intend to increment
+the suffixed number in the compatible string whenever the software
+interface to these IP blocks changes, or when the functionality of the
+underlying IP blocks changes in a way that software should be aware of.
+
+Driver developers can use compatible string "match" values such as
+"sifive,uart0" to indicate that their driver is compatible with the
+register interface and functionality associated with the relevant
+upstream sifive-blocks commits. It is expected that most drivers will
+match on these IP block-specific compatible strings.
+
+DT data authors, when writing data for a particular SoC, should
+continue to specify an SoC-specific compatible string value, such as
+"sifive,fu540-c000-uart". This way, if SoC-specific
+integration-specific bug fixes or workarounds are needed, the kernel
+or other system software can match on this string to apply them. The
+IP block-specific compatible string (such as "sifive,uart0") should
+then be specified as a subsequent value.
+
+An example of this style:
+
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";