dts: update to v5.3-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

12 files changed, 94 insertions, 4 deletions

diff --git a/dts/include/dt-bindings/clock/exynos4.h b/dts/include/dt-bindings/clock/exynos4.h
index a0439ce8e8..88ec3968b9 100644
--- a/dts/include/dt-bindings/clock/exynos4.h
+++ b/dts/include/dt-bindings/clock/exynos4.h
@@ -187,6 +187,7 @@
 #define CLK_MIPI_HSI		349 /* Exynos4210 only */
 #define CLK_PIXELASYNCM0	351
 #define CLK_PIXELASYNCM1	352
+#define CLK_ASYNC_G3D		353 /* Exynos4x12 only */
 #define CLK_PWM_ISP_SCLK	379 /* Exynos4x12 only */
 #define CLK_SPI0_ISP_SCLK	380 /* Exynos4x12 only */
 #define CLK_SPI1_ISP_SCLK	381 /* Exynos4x12 only */
diff --git a/dts/include/dt-bindings/clock/exynos5420.h b/dts/include/dt-bindings/clock/exynos5420.h
index 355f469943..02d5ac469a 100644
--- a/dts/include/dt-bindings/clock/exynos5420.h
+++ b/dts/include/dt-bindings/clock/exynos5420.h
@@ -60,6 +60,7 @@
 #define CLK_MAU_EPLL		159
 #define CLK_SCLK_HSIC_12M	160
 #define CLK_SCLK_MPHY_IXTAL24	161
+#define CLK_SCLK_BPLL		162
 
 /* gate clocks */
 #define CLK_UART0		257
@@ -195,6 +196,16 @@
 #define CLK_ACLK432_CAM		518
 #define CLK_ACLK_FL1550_CAM	519
 #define CLK_ACLK550_CAM		520
+#define CLK_CLKM_PHY0		521
+#define CLK_CLKM_PHY1		522
+#define CLK_ACLK_PPMU_DREX0_0	523
+#define CLK_ACLK_PPMU_DREX0_1	524
+#define CLK_ACLK_PPMU_DREX1_0	525
+#define CLK_ACLK_PPMU_DREX1_1	526
+#define CLK_PCLK_PPMU_DREX0_0	527
+#define CLK_PCLK_PPMU_DREX0_1	528
+#define CLK_PCLK_PPMU_DREX1_0	529
+#define CLK_PCLK_PPMU_DREX1_1	530
 
 /* mux clocks */
 #define CLK_MOUT_HDMI		640
@@ -217,6 +228,8 @@
 #define CLK_MOUT_EPLL		657
 #define CLK_MOUT_MAU_EPLL	658
 #define CLK_MOUT_USER_MAU_EPLL	659
+#define CLK_MOUT_SCLK_SPLL	660
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY	661
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
@@ -248,8 +261,11 @@
 #define CLK_DOUT_CCLK_DREX0	794
 #define CLK_DOUT_CLK2X_PHY0	795
 #define CLK_DOUT_PCLK_CORE_MEM	796
+#define CLK_FF_DOUT_SPLL2	797
+#define CLK_DOUT_PCLK_DREX0	798
+#define CLK_DOUT_PCLK_DREX1	799
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		797
+#define CLK_NR_CLKS		800
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
diff --git a/dts/include/dt-bindings/clock/g12a-clkc.h b/dts/include/dt-bindings/clock/g12a-clkc.h
index e10470ed7c..b6b127e456 100644
--- a/dts/include/dt-bindings/clock/g12a-clkc.h
+++ b/dts/include/dt-bindings/clock/g12a-clkc.h
@@ -136,5 +136,6 @@
 #define CLKID_VDEC_1				204
 #define CLKID_VDEC_HEVC				207
 #define CLKID_VDEC_HEVCF			210
+#define CLKID_TS				212
 
 #endif /* __G12A_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/imx8mm-clock.h b/dts/include/dt-bindings/clock/imx8mm-clock.h
index 1b4353e7b4..07e6c686f3 100644
--- a/dts/include/dt-bindings/clock/imx8mm-clock.h
+++ b/dts/include/dt-bindings/clock/imx8mm-clock.h
@@ -239,6 +239,15 @@
 
 #define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK	222
 
-#define IMX8MM_CLK_END				223
+#define IMX8MM_CLK_GPIO1_ROOT			223
+#define IMX8MM_CLK_GPIO2_ROOT			224
+#define IMX8MM_CLK_GPIO3_ROOT			225
+#define IMX8MM_CLK_GPIO4_ROOT			226
+#define IMX8MM_CLK_GPIO5_ROOT			227
+
+#define IMX8MM_CLK_SNVS_ROOT			228
+#define IMX8MM_CLK_GIC				229
+
+#define IMX8MM_CLK_END				230
 
 #endif
diff --git a/dts/include/dt-bindings/clock/imx8mq-clock.h b/dts/include/dt-bindings/clock/imx8mq-clock.h
index 6677e920dc..65463673d2 100644
--- a/dts/include/dt-bindings/clock/imx8mq-clock.h
+++ b/dts/include/dt-bindings/clock/imx8mq-clock.h
@@ -400,5 +400,8 @@
 #define IMX8MQ_CLK_GPIO4_ROOT			262
 #define IMX8MQ_CLK_GPIO5_ROOT			263
 
-#define IMX8MQ_CLK_END				264
+#define IMX8MQ_CLK_SNVS_ROOT			264
+#define IMX8MQ_CLK_GIC				265
+
+#define IMX8MQ_CLK_END				266
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/dts/include/dt-bindings/clock/meson8b-clkc.h b/dts/include/dt-bindings/clock/meson8b-clkc.h
index 47556539f0..68862aaf97 100644
--- a/dts/include/dt-bindings/clock/meson8b-clkc.h
+++ b/dts/include/dt-bindings/clock/meson8b-clkc.h
@@ -112,5 +112,8 @@
 #define CLKID_VDEC_HCODEC	199
 #define CLKID_VDEC_2		202
 #define CLKID_VDEC_HEVC		206
+#define CLKID_CTS_AMCLK		209
+#define CLKID_CTS_MCLK_I958	212
+#define CLKID_CTS_I958		213
 
 #endif /* __MESON8B_CLKC_H */
diff --git a/dts/include/dt-bindings/clock/mt8516-clk.h b/dts/include/dt-bindings/clock/mt8516-clk.h
index 9cfca53cd7..816447b98e 100644
--- a/dts/include/dt-bindings/clock/mt8516-clk.h
+++ b/dts/include/dt-bindings/clock/mt8516-clk.h
@@ -208,4 +208,21 @@
 #define CLK_TOP_MSDC2_INFRA		176
 #define CLK_TOP_NR_CLK			177
 
+/* AUDSYS */
+
+#define CLK_AUD_AFE			0
+#define CLK_AUD_I2S			1
+#define CLK_AUD_22M			2
+#define CLK_AUD_24M			3
+#define CLK_AUD_INTDIR			4
+#define CLK_AUD_APLL2_TUNER		5
+#define CLK_AUD_APLL_TUNER		6
+#define CLK_AUD_HDMI			7
+#define CLK_AUD_SPDF			8
+#define CLK_AUD_ADC			9
+#define CLK_AUD_DAC			10
+#define CLK_AUD_DAC_PREDIS		11
+#define CLK_AUD_TML			12
+#define CLK_AUD_NR_CLK			13
+
 #endif /* _DT_BINDINGS_CLK_MT8516_H */
diff --git a/dts/include/dt-bindings/clock/qcom,gcc-qcs404.h b/dts/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 454b3f43f5..2cd62c9856 100644
--- a/dts/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/dts/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -166,5 +166,12 @@
 #define GCC_PCIEPHY_0_PHY_BCR				12
 #define GCC_EMAC_BCR					13
 #define GCC_CDSP_RESTART				14
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES		15
+#define GCC_PCIE_0_AHB_ARES				16
+#define GCC_PCIE_0_AXI_SLAVE_ARES			17
+#define GCC_PCIE_0_AXI_MASTER_ARES			18
+#define GCC_PCIE_0_CORE_STICKY_ARES			19
+#define GCC_PCIE_0_SLEEP_ARES				20
+#define GCC_PCIE_0_PIPE_ARES				21
 
 #endif
diff --git a/dts/include/dt-bindings/clock/qcom,gpucc-msm8998.h b/dts/include/dt-bindings/clock/qcom,gpucc-msm8998.h
new file mode 100644
index 0000000000..2623570ee9
--- /dev/null
+++ b/dts/include/dt-bindings/clock/qcom,gpucc-msm8998.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019, Jeffrey Hugo
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H
+#define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H
+
+#define GPUPLL0						0
+#define GPUPLL0_OUT_EVEN				1
+#define RBCPR_CLK_SRC					2
+#define GFX3D_CLK_SRC					3
+#define RBBMTIMER_CLK_SRC				4
+#define GFX3D_ISENSE_CLK_SRC				5
+#define RBCPR_CLK					6
+#define GFX3D_CLK					7
+#define RBBMTIMER_CLK					8
+#define GFX3D_ISENSE_CLK				9
+#define GPUCC_CXO_CLK					10
+
+#define GPU_CX_BCR					0
+#define RBCPR_BCR					1
+#define GPU_GX_BCR					2
+#define GPU_ISENSE_BCR					3
+
+#define GPU_CX_GDSC					1
+#define GPU_GX_GDSC					2
+
+#endif
diff --git a/dts/include/dt-bindings/clock/rk3228-cru.h b/dts/include/dt-bindings/clock/rk3228-cru.h
index 3b245e3df8..de550ea56e 100644
--- a/dts/include/dt-bindings/clock/rk3228-cru.h
+++ b/dts/include/dt-bindings/clock/rk3228-cru.h
@@ -64,6 +64,7 @@
 #define SCLK_WIFI		141
 #define SCLK_OTGPHY0		142
 #define SCLK_OTGPHY1		143
+#define SCLK_HDMI_PHY		144
 
 /* dclk gates */
 #define DCLK_VOP		190
diff --git a/dts/include/dt-bindings/clock/rk3328-cru.h b/dts/include/dt-bindings/clock/rk3328-cru.h
index afb8113403..555b4ff660 100644
--- a/dts/include/dt-bindings/clock/rk3328-cru.h
+++ b/dts/include/dt-bindings/clock/rk3328-cru.h
@@ -164,6 +164,7 @@
 #define PCLK_DCF		233
 #define PCLK_SARADC		234
 #define PCLK_ACODECPHY		235
+#define PCLK_WDT		236
 
 /* hclk gates */
 #define HCLK_PERI		308
diff --git a/dts/include/dt-bindings/clock/stratix10-clock.h b/dts/include/dt-bindings/clock/stratix10-clock.h
index 0ac1c90a18..08b98e20b7 100644
--- a/dts/include/dt-bindings/clock/stratix10-clock.h
+++ b/dts/include/dt-bindings/clock/stratix10-clock.h
@@ -79,6 +79,8 @@
 #define STRATIX10_USB_CLK		59
 #define STRATIX10_SPI_M_CLK		60
 #define STRATIX10_NAND_CLK		61
-#define STRATIX10_NUM_CLKS		62
+#define STRATIX10_NAND_X_CLK		62
+#define STRATIX10_NAND_ECC_CLK		63
+#define STRATIX10_NUM_CLKS		64
 
 #endif	/* __STRATIX10_CLOCK_H */