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author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-11-10 14:10:56 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-11-10 15:07:14 +0100 |
commit | 4b689ab6bccaf4fa65f71644d1ca4c9d8358385a (patch) | |
tree | d97fbd8510349db6cfa668ed6353c61ba0e71f9c /dts/include/dt-bindings/mux/mux-j721e-wiz.h | |
parent | 9d115d95018b8025f0f35abfb88f78a42e103933 (diff) | |
parent | 85f8d17be5cc2708bd5f6414b8012d5b4c6821d2 (diff) | |
download | barebox-4b689ab6bccaf4fa65f71644d1ca4c9d8358385a.tar.gz barebox-4b689ab6bccaf4fa65f71644d1ca4c9d8358385a.tar.xz |
Merge branch 'for-next/dts'
Diffstat (limited to 'dts/include/dt-bindings/mux/mux-j721e-wiz.h')
-rw-r--r-- | dts/include/dt-bindings/mux/mux-j721e-wiz.h | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/dts/include/dt-bindings/mux/mux-j721e-wiz.h b/dts/include/dt-bindings/mux/mux-j721e-wiz.h deleted file mode 100644 index fd1c4ea9fc..0000000000 --- a/dts/include/dt-bindings/mux/mux-j721e-wiz.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for J721E WIZ. - */ - -#ifndef _DT_BINDINGS_J721E_WIZ -#define _DT_BINDINGS_J721E_WIZ - -#define SERDES0_LANE0_QSGMII_LANE1 0x0 -#define SERDES0_LANE0_PCIE0_LANE0 0x1 -#define SERDES0_LANE0_USB3_0_SWAP 0x2 - -#define SERDES0_LANE1_QSGMII_LANE2 0x0 -#define SERDES0_LANE1_PCIE0_LANE1 0x1 -#define SERDES0_LANE1_USB3_0 0x2 - -#define SERDES1_LANE0_QSGMII_LANE3 0x0 -#define SERDES1_LANE0_PCIE1_LANE0 0x1 -#define SERDES1_LANE0_USB3_1_SWAP 0x2 -#define SERDES1_LANE0_SGMII_LANE0 0x3 - -#define SERDES1_LANE1_QSGMII_LANE4 0x0 -#define SERDES1_LANE1_PCIE1_LANE1 0x1 -#define SERDES1_LANE1_USB3_1 0x2 -#define SERDES1_LANE1_SGMII_LANE1 0x3 - -#define SERDES2_LANE0_PCIE2_LANE0 0x1 -#define SERDES2_LANE0_SGMII_LANE0 0x3 -#define SERDES2_LANE0_USB3_1_SWAP 0x2 - -#define SERDES2_LANE1_PCIE2_LANE1 0x1 -#define SERDES2_LANE1_USB3_1 0x2 -#define SERDES2_LANE1_SGMII_LANE1 0x3 - -#define SERDES3_LANE0_PCIE3_LANE0 0x1 -#define SERDES3_LANE0_USB3_0_SWAP 0x2 - -#define SERDES3_LANE1_PCIE3_LANE1 0x1 -#define SERDES3_LANE1_USB3_0 0x2 - -#define SERDES4_LANE0_EDP_LANE0 0x0 -#define SERDES4_LANE0_QSGMII_LANE5 0x2 - -#define SERDES4_LANE1_EDP_LANE1 0x0 -#define SERDES4_LANE1_QSGMII_LANE6 0x2 - -#define SERDES4_LANE2_EDP_LANE2 0x0 -#define SERDES4_LANE2_QSGMII_LANE7 0x2 - -#define SERDES4_LANE3_EDP_LANE3 0x0 -#define SERDES4_LANE3_QSGMII_LANE8 0x2 - -#endif /* _DT_BINDINGS_J721E_WIZ */ |