diff options
author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-11-17 09:54:23 +0100 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-11-17 09:54:23 +0100 |
commit | 1f7229e657c3a32355c9ee912d412a806b13f58a (patch) | |
tree | de4a152c10230105446b3acd220f0c62dd8562c9 /dts/src/arc | |
parent | 68a902345d0643c303379599d7d29471ca296700 (diff) | |
download | barebox-1f7229e657c3a32355c9ee912d412a806b13f58a.tar.gz barebox-1f7229e657c3a32355c9ee912d412a806b13f58a.tar.xz |
dts: update to v4.14-rc7
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arc')
-rw-r--r-- | dts/src/arc/hsdk.dts | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/dts/src/arc/hsdk.dts b/dts/src/arc/hsdk.dts index 8adde1b492..8f627c200d 100644 --- a/dts/src/arc/hsdk.dts +++ b/dts/src/arc/hsdk.dts @@ -137,14 +137,15 @@ /* * DW sdio controller has external ciu clock divider * controlled via register in SDIO IP. Due to its - * unexpected default value (it should devide by 1 - * but it devides by 8) SDIO IP uses wrong clock and + * unexpected default value (it should divide by 1 + * but it divides by 8) SDIO IP uses wrong clock and * works unstable (see STAR 9001204800) + * We switched to the minimum possible value of the + * divisor (div-by-2) in HSDK platform code. * So add temporary fix and change clock frequency - * from 100000000 to 12500000 Hz until we fix dw sdio - * driver itself. + * to 50000000 Hz until we fix dw sdio driver itself. */ - clock-frequency = <12500000>; + clock-frequency = <50000000>; #clock-cells = <0>; }; |