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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-08-09 21:17:51 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-08-09 21:17:51 +0200 |
| commit | 6187b17da4b277417f34fe0b0b90bbaddcbc599e (patch) | |
| tree | 51cbbaa0fa325c592d084eb7d197a5df0e7a43bb /dts/src/arm/am33xx-clocks.dtsi | |
| parent | c53e1fc545e686e1f48c8efb9057fc72e158f183 (diff) | |
| download | barebox-6187b17da4b277417f34fe0b0b90bbaddcbc599e.tar.gz barebox-6187b17da4b277417f34fe0b0b90bbaddcbc599e.tar.xz | |
dts: update to v5.14-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/am33xx-clocks.dtsi')
| -rw-r--r-- | dts/src/arm/am33xx-clocks.dtsi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/dts/src/arm/am33xx-clocks.dtsi b/dts/src/arm/am33xx-clocks.dtsi index dced92a897..b7b7106f2d 100644 --- a/dts/src/arm/am33xx-clocks.dtsi +++ b/dts/src/arm/am33xx-clocks.dtsi @@ -164,7 +164,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0490>, <0x045c>, <0x0468>; + reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; }; dpll_core_x2_ck: dpll_core_x2_ck { @@ -204,7 +204,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0488>, <0x0420>, <0x042c>; + reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; }; dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { @@ -220,7 +220,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0494>, <0x0434>, <0x0440>; + reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; }; dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { @@ -244,7 +244,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x0498>, <0x0448>, <0x0454>; + reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; }; dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { @@ -261,7 +261,7 @@ #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; - reg = <0x048c>, <0x0470>, <0x049c>; + reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; }; dpll_per_m2_ck: dpll_per_m2_ck@4ac { |