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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-07-08 14:44:21 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-07-08 14:44:21 +0200 |
commit | 87360e3dd42bb627a9f2611f961728c0789e1c21 (patch) | |
tree | afefc88c862d9feafb0cdb075badeb8d32d8efd2 /dts/src/arm/exynos3250.dtsi | |
parent | 80936d6aaeea1b10ce4eb81c54eece2f55f8e209 (diff) | |
download | barebox-87360e3dd42bb627a9f2611f961728c0789e1c21.tar.gz barebox-87360e3dd42bb627a9f2611f961728c0789e1c21.tar.xz |
dts: update to v4.2-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/exynos3250.dtsi')
-rw-r--r-- | dts/src/arm/exynos3250.dtsi | 48 |
1 files changed, 47 insertions, 1 deletions
diff --git a/dts/src/arm/exynos3250.dtsi b/dts/src/arm/exynos3250.dtsi index e3bfb11c6e..d7201333e3 100644 --- a/dts/src/arm/exynos3250.dtsi +++ b/dts/src/arm/exynos3250.dtsi @@ -189,7 +189,7 @@ }; rtc: rtc@10070000 { - compatible = "samsung,exynos3250-rtc"; + compatible = "samsung,s3c6410-rtc"; reg = <0x10070000 0x100>; interrupts = <0 73 0>, <0 74 0>; interrupt-parent = <&pmu_system_controller>; @@ -243,6 +243,30 @@ interrupts = <0 240 0>; }; + jpeg: codec@11830000 { + compatible = "samsung,exynos3250-jpeg"; + reg = <0x11830000 0x1000>; + interrupts = <0 171 0>; + clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>; + clock-names = "jpeg", "sclk"; + power-domains = <&pd_cam>; + assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>; + assigned-clock-rates = <0>, <150000000>; + assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>; + iommus = <&sysmmu_jpeg>; + status = "disabled"; + }; + + sysmmu_jpeg: sysmmu@11A60000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11a60000 0x1000>; + interrupts = <0 156 0>, <0 161 0>; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>; + power-domains = <&pd_cam>; + #iommu-cells = <0>; + }; + fimd: fimd@11c00000 { compatible = "samsung,exynos3250-fimd"; reg = <0x11c00000 0x30000>; @@ -251,6 +275,7 @@ clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; power-domains = <&pd_lcd0>; + iommus = <&sysmmu_fimd0>; samsung,sysreg = <&sys_reg>; status = "disabled"; }; @@ -270,6 +295,16 @@ status = "disabled"; }; + sysmmu_fimd0: sysmmu@11E20000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x11e20000 0x1000>; + interrupts = <0 80 0>, <0 81 0>; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; + power-domains = <&pd_lcd0>; + #iommu-cells = <0>; + }; + hsotg: hsotg@12480000 { compatible = "snps,dwc2"; reg = <0x12480000 0x20000>; @@ -364,9 +399,20 @@ clock-names = "mfc", "sclk_mfc"; clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; power-domains = <&pd_mfc>; + iommus = <&sysmmu_mfc>; status = "disabled"; }; + sysmmu_mfc: sysmmu@13620000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x13620000 0x1000>; + interrupts = <0 96 0>, <0 98 0>; + clock-names = "sysmmu", "master"; + clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>; + power-domains = <&pd_mfc>; + #iommu-cells = <0>; + }; + serial_0: serial@13800000 { compatible = "samsung,exynos4210-uart"; reg = <0x13800000 0x100>; |