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authorSascha Hauer <s.hauer@pengutronix.de>2019-08-19 08:56:20 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-08-19 08:56:20 +0200
commit6940ba22c66ac1c713500027bf5f6832442a1410 (patch)
treea460f01b9807e1c17206a40dbc94b6f54167cf29 /dts/src/arm/exynos4.dtsi
parente66a790177410d7433e6672d97bb0b54455ba669 (diff)
downloadbarebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.gz
barebox-6940ba22c66ac1c713500027bf5f6832442a1410.tar.xz
dts: update to v5.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/exynos4.dtsi')
-rw-r--r--dts/src/arm/exynos4.dtsi16
1 files changed, 15 insertions, 1 deletions
diff --git a/dts/src/arm/exynos4.dtsi b/dts/src/arm/exynos4.dtsi
index 36ccf22743..1264cc431f 100644
--- a/dts/src/arm/exynos4.dtsi
+++ b/dts/src/arm/exynos4.dtsi
@@ -54,7 +54,7 @@
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
- interrupts = <2 2>, <3 2>;
+ status = "disabled";
};
soc: soc {
@@ -415,6 +415,20 @@
};
};
+ gpu: gpu@13000000 {
+ compatible = "samsung,exynos4210-mali", "arm,mali-400";
+ reg = <0x13000000 0x10000>;
+ /*
+ * CLK_G3D is not actually bus clock but a IP-level clock.
+ * The bus clock is not described in hardware manual.
+ */
+ clocks = <&clock CLK_G3D>,
+ <&clock CLK_SCLK_G3D>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_g3d>;
+ status = "disabled";
+ };
+
i2s1: i2s@13960000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13960000 0x100>;