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authorSascha Hauer <s.hauer@pengutronix.de>2018-02-27 09:40:19 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2018-03-01 14:29:51 +0100
commita9c5f6b9ec883ee9dafd6d393600acc6fd263043 (patch)
tree35621cff332a0c95509b04b2e4170f0eda1f0ecf /dts/src/arm/gemini-nas4220b.dts
parent5ba0e42cb24afdf59d48930daf495c148312fc67 (diff)
downloadbarebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.gz
barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.xz
dts: update to v4.16-rc1
Also includeded: ARM: dts: am33xx: do not delete no longer existing clocks Several clocks are removed from the am33xx dts files with v4.16-rc1. Remove the corresponding /delete-node/ directives aswell to avoid dtc breakage. Also included: ARM: dts: imx6qdl: SolidRun: Fix upstream include Upstream dts file way renamed, so change include name accordingly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/gemini-nas4220b.dts')
-rw-r--r--dts/src/arm/gemini-nas4220b.dts69
1 files changed, 69 insertions, 0 deletions
diff --git a/dts/src/arm/gemini-nas4220b.dts b/dts/src/arm/gemini-nas4220b.dts
index d6a22e677c..8bbb6f85d1 100644
--- a/dts/src/arm/gemini-nas4220b.dts
+++ b/dts/src/arm/gemini-nas4220b.dts
@@ -64,6 +64,19 @@
};
};
+ mdio0: ethernet-phy {
+ compatible = "virtual,mdio-gpio";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
+ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+ };
+
soc {
flash@30000000 {
status = "okay";
@@ -116,6 +129,50 @@
groups = "gpio1dgrp";
};
};
+ pinctrl-gmii {
+ mux {
+ function = "gmii";
+ groups = "gmii_gmac0_grp";
+ };
+ /* Settings come from OpenWRT */
+ conf0 {
+ pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
+ skew-delay = <0>;
+ };
+ conf1 {
+ pins = "T8 GMAC0 RXC", "T11 GMAC1 RXC";
+ skew-delay = <15>;
+ };
+ conf2 {
+ pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
+ skew-delay = <7>;
+ };
+ conf3 {
+ pins = "V7 GMAC0 TXC";
+ skew-delay = <11>;
+ };
+ conf4 {
+ pins = "P10 GMAC1 TXC";
+ skew-delay = <10>;
+ };
+ conf5 {
+ /* The data lines all have default skew */
+ pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
+ "P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
+ "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
+ "R7 GMAC0 TXD2", "P7 GMAC0 TXD3",
+ "R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
+ "V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
+ "R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
+ "U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
+ skew-delay = <7>;
+ };
+ /* Set up drive strength on GMAC0 to 16 mA */
+ conf6 {
+ groups = "gmii_gmac0_grp";
+ drive-strength = <16>;
+ };
+ };
};
};
@@ -130,6 +187,18 @@
pinctrl-0 = <&gpio1_default_pins>;
};
+ ethernet@60000000 {
+ status = "okay";
+
+ ethernet-port@0 {
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ };
+ ethernet-port@1 {
+ /* Not used in this platform */
+ };
+ };
+
ata@63000000 {
status = "okay";
};