dts: update to v6.5-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 0 insertions, 177 deletions

diff --git a/dts/src/arm/imx6q-gw54xx.dts b/dts/src/arm/imx6q-gw54xx.dts
deleted file mode 100644
index d5d46908cf..0000000000
--- a/dts/src/arm/imx6q-gw54xx.dts
+++ /dev/null
@@ -1,177 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2013 Gateworks Corporation
- */
-
-/dts-v1/;
-#include "imx6q.dtsi"
-#include "imx6qdl-gw54xx.dtsi"
-#include <dt-bindings/media/tda1997x.h>
-
-/ {
-	model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
-	compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
-
-	sound-digital {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "tda1997x-audio";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,bitclock-master = <&sound_codec>;
-		simple-audio-card,frame-master = <&sound_codec>;
-
-		sound_cpu: simple-audio-card,cpu {
-			sound-dai = <&ssi2>;
-		};
-
-		sound_codec: simple-audio-card,codec {
-			sound-dai = <&hdmi_receiver>;
-		};
-	};
-};
-
-&i2c3 {
-	adv7180: camera@20 {
-		compatible = "adi,adv7180";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_adv7180>;
-		reg = <0x20>;
-		powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
-
-		port {
-			adv7180_to_ipu2_csi1_mux: endpoint {
-				remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
-				bus-width = <8>;
-			};
-		};
-	};
-
-	hdmi_receiver: hdmi-receiver@48 {
-		compatible = "nxp,tda19971";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_tda1997x>;
-		reg = <0x48>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-		DOVDD-supply = <&reg_3p3v>;
-		AVDD-supply = <&sw4_reg>;
-		DVDD-supply = <&sw4_reg>;
-		#sound-dai-cells = <0>;
-		nxp,audout-format = "i2s";
-		nxp,audout-layout = <0>;
-		nxp,audout-width = <16>;
-		nxp,audout-mclk-fs = <128>;
-		/*
-		 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
-		 * and Y[11:4] across 16bits in the same cycle
-		 * which we map to VP[15:08]<->CSI_DATA[19:12]
-		 */
-		nxp,vidout-portcfg =
-			/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
-			< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
-			/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
-			< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
-			/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
-			< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
-			/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
-			< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
-
-		port {
-			tda1997x_to_ipu1_csi0_mux: endpoint {
-				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
-				bus-width = <16>;
-				hsync-active = <1>;
-				vsync-active = <1>;
-				data-active = <1>;
-			};
-		};
-	};
-};
-
-&ipu1_csi0_from_ipu1_csi0_mux {
-	bus-width = <16>;
-};
-
-&ipu1_csi0_mux_from_parallel_sensor {
-	remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
-	bus-width = <16>;
-};
-
-&ipu1_csi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ipu1_csi0>;
-};
-
-&ipu2_csi1_from_ipu2_csi1_mux {
-	bus-width = <8>;
-};
-
-&ipu2_csi1_mux_from_parallel_sensor {
-	remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
-	bus-width = <8>;
-};
-
-&ipu2_csi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ipu2_csi1>;
-};
-
-&sata {
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_adv7180: adv7180grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x0001b0b0
-			MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x4001b0b0
-		>;
-	};
-
-	pinctrl_ipu1_csi0: ipu1_csi0grp {
-		fsl,pins = <
-			MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18		0x1b0b0
-			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19		0x1b0b0
-			MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC		0x1b0b0
-			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	0x1b0b0
-			MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC		0x1b0b0
-		>;
-	};
-
-	pinctrl_ipu2_csi1: ipu2_csi1grp {
-		fsl,pins = <
-			MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19    0x1b0b0
-			MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18    0x1b0b0
-			MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17    0x1b0b0
-			MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16    0x1b0b0
-			MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15    0x1b0b0
-			MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14    0x1b0b0
-			MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13    0x1b0b0
-			MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12    0x1b0b0
-			MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC     0x1b0b0
-			MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC     0x1b0b0
-			MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK    0x1b0b0
-		>;
-	};
-
-	pinctrl_tda1997x: tda1997xgrp {
-		fsl,pins = <
-			MX6QDL_PAD_GPIO_7__GPIO1_IO07	0x1b0b0
-		>;
-	};
-};