dts: update to v6.5-rc1

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 0 insertions, 81 deletions

diff --git a/dts/src/arm/r8a7743-sk-rzg1m.dts b/dts/src/arm/r8a7743-sk-rzg1m.dts
deleted file mode 100644
index ff274bfcb6..0000000000
--- a/dts/src/arm/r8a7743-sk-rzg1m.dts
+++ /dev/null
@@ -1,81 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the SK-RZG1M board
- *
- * Copyright (C) 2016-2017 Cogent Embedded, Inc.
- */
-
-/dts-v1/;
-#include "r8a7743.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "SK-RZG1M";
-	compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
-
-	aliases {
-		serial0 = &scif0;
-	};
-
-	chosen {
-		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0 0x40000000 0 0x40000000>;
-	};
-
-	memory@200000000 {
-		device_type = "memory";
-		reg = <2 0x00000000 0 0x40000000>;
-	};
-};
-
-&extal_clk {
-	clock-frequency = <20000000>;
-};
-
-&pfc {
-	scif0_pins: scif0 {
-		groups = "scif0_data_d";
-		function = "scif0";
-	};
-
-	ether_pins: ether {
-		groups = "eth_link", "eth_mdio", "eth_rmii";
-		function = "eth";
-	};
-
-	phy1_pins: phy1 {
-		groups = "intc_irq0";
-		function = "intc";
-	};
-};
-
-&scif0 {
-	pinctrl-0 = <&scif0_pins>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-&ether {
-	pinctrl-0 = <&ether_pins>, <&phy1_pins>;
-	pinctrl-names = "default";
-
-	phy-handle = <&phy1>;
-	renesas,ether-link-active-low;
-	status = "okay";
-
-	phy1: ethernet-phy@1 {
-		compatible = "ethernet-phy-id0022.1537",
-			     "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-		interrupt-parent = <&irqc>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-		micrel,led-mode = <1>;
-		reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
-	};
-};