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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-02-27 09:40:19 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-03-01 14:29:51 +0100 |
| commit | a9c5f6b9ec883ee9dafd6d393600acc6fd263043 (patch) | |
| tree | 35621cff332a0c95509b04b2e4170f0eda1f0ecf /dts/src/arm/r8a7794.dtsi | |
| parent | 5ba0e42cb24afdf59d48930daf495c148312fc67 (diff) | |
| download | barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.gz barebox-a9c5f6b9ec883ee9dafd6d393600acc6fd263043.tar.xz | |
dts: update to v4.16-rc1
Also includeded:
ARM: dts: am33xx: do not delete no longer existing clocks
Several clocks are removed from the am33xx dts files with v4.16-rc1.
Remove the corresponding /delete-node/ directives aswell to avoid
dtc breakage.
Also included:
ARM: dts: imx6qdl: SolidRun: Fix upstream include
Upstream dts file way renamed, so change include name accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/r8a7794.dtsi')
| -rw-r--r-- | dts/src/arm/r8a7794.dtsi | 27 |
1 files changed, 17 insertions, 10 deletions
diff --git a/dts/src/arm/r8a7794.dtsi b/dts/src/arm/r8a7794.dtsi index 5643976c13..106b4e1649 100644 --- a/dts/src/arm/r8a7794.dtsi +++ b/dts/src/arm/r8a7794.dtsi @@ -37,6 +37,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "renesas,apmu"; cpu0: cpu@0 { device_type = "cpu"; @@ -66,6 +67,12 @@ }; }; + apmu@e6151000 { + compatible = "renesas,r8a7794-apmu", "renesas,apmu"; + reg = <0 0xe6151000 0 0x188>; + cpus = <&cpu0 &cpu1>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -181,7 +188,7 @@ }; cmt0: timer@ffca0000 { - compatible = "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7794-cmt0", "renesas,rcar-gen2-cmt0"; reg = <0 0xffca0000 0 0x1004>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; @@ -190,13 +197,11 @@ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; resets = <&cpg 124>; - renesas,channels-mask = <0x60>; - status = "disabled"; }; cmt1: timer@e6130000 { - compatible = "renesas,cmt-48-gen2"; + compatible = "renesas,r8a7794-cmt1", "renesas,rcar-gen2-cmt1"; reg = <0 0xe6130000 0 0x1004>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -211,8 +216,6 @@ power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; resets = <&cpg 329>; - renesas,channels-mask = <0xff>; - status = "disabled"; }; @@ -640,7 +643,8 @@ }; ether: ethernet@ee700000 { - compatible = "renesas,ether-r8a7794"; + compatible = "renesas,ether-r8a7794", + "renesas,rcar-gen2-ether"; reg = <0 0xee700000 0 0x400>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 813>; @@ -791,7 +795,8 @@ }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7794"; + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee100000 0 0x328>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 314>; @@ -805,7 +810,8 @@ }; sdhi1: sd@ee140000 { - compatible = "renesas,sdhi-r8a7794"; + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee140000 0 0x100>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 312>; @@ -819,7 +825,8 @@ }; sdhi2: sd@ee160000 { - compatible = "renesas,sdhi-r8a7794"; + compatible = "renesas,sdhi-r8a7794", + "renesas,rcar-gen2-sdhi"; reg = <0 0xee160000 0 0x100>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 311>; |