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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-07 08:12:11 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2018-12-07 08:12:11 +0100 |
| commit | e6defd1992be318c16957a881dde60114597bced (patch) | |
| tree | c3a48729af7ecce699e0fe92ba55eb4f371e635e /dts/src/arm/rk3288-veyron.dtsi | |
| parent | 718300767db51d2751cc2b223e777749704991ba (diff) | |
| download | barebox-e6defd1992be318c16957a881dde60114597bced.tar.gz barebox-e6defd1992be318c16957a881dde60114597bced.tar.xz | |
dts: update to v4.20-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm/rk3288-veyron.dtsi')
| -rw-r--r-- | dts/src/arm/rk3288-veyron.dtsi | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/dts/src/arm/rk3288-veyron.dtsi b/dts/src/arm/rk3288-veyron.dtsi index 2075120cfc..d8bf939a3a 100644 --- a/dts/src/arm/rk3288-veyron.dtsi +++ b/dts/src/arm/rk3288-veyron.dtsi @@ -10,7 +10,11 @@ #include "rk3288.dtsi" / { - memory@0 { + /* + * The default coreboot on veyron devices ignores memory@0 nodes + * and would instead create another memory node. + */ + memory { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; |