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author | Sascha Hauer <s.hauer@pengutronix.de> | 2017-10-16 11:28:54 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2017-10-16 11:28:54 +0200 |
commit | bee7083638439457f600252a8cea2c5e4165f5cd (patch) | |
tree | 1d10b86a19d4b3d7a4420d9d160e2f86eb45791b /dts/src/arm64/amlogic/meson-gxl.dtsi | |
parent | b2655c3cd112729e9f8bdda47044908472fce480 (diff) | |
download | barebox-bee7083638439457f600252a8cea2c5e4165f5cd.tar.gz barebox-bee7083638439457f600252a8cea2c5e4165f5cd.tar.xz |
dts: update to v4.14-rc4
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/amlogic/meson-gxl.dtsi')
-rw-r--r-- | dts/src/arm64/amlogic/meson-gxl.dtsi | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/dts/src/arm64/amlogic/meson-gxl.dtsi b/dts/src/arm64/amlogic/meson-gxl.dtsi index d6876e6497..d8dd3298b1 100644 --- a/dts/src/arm64/amlogic/meson-gxl.dtsi +++ b/dts/src/arm64/amlogic/meson-gxl.dtsi @@ -281,6 +281,17 @@ }; }; + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "BOOT_8"; + bias-pull-down; + }; + }; + nor_pins: nor { mux { groups = "nor_d", @@ -319,6 +330,17 @@ }; }; + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "CARD_2"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "CARD_2"; + bias-pull-down; + }; + }; + sdio_pins: sdio { mux { groups = "sdio_d0", @@ -331,6 +353,17 @@ }; }; + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "GPIOX_4"; + bias-pull-down; + }; + }; + sdio_irq_pins: sdio_irq { mux { groups = "sdio_irq"; @@ -603,21 +636,21 @@ &sd_emmc_a { clocks = <&clkc CLKID_SD_EMMC_A>, - <&xtal>, + <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_b { clocks = <&clkc CLKID_SD_EMMC_B>, - <&xtal>, + <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_c { clocks = <&clkc CLKID_SD_EMMC_C>, - <&xtal>, + <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; |