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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-14 09:05:53 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-02-18 08:32:25 +0100 |
| commit | 81ce4a7dec8ba066c73692e10634091b14c1e494 (patch) | |
| tree | d61574b25fda47711e3efab57c7a5739de477565 /dts/src/arm64/bitmain | |
| parent | 84b7f86bef670f6751d67131738555fa53ca3f6b (diff) | |
| download | barebox-81ce4a7dec8ba066c73692e10634091b14c1e494.tar.gz barebox-81ce4a7dec8ba066c73692e10634091b14c1e494.tar.xz | |
dts: update to v5.6-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/bitmain')
| -rw-r--r-- | dts/src/arm64/bitmain/bm1880-sophon-edge.dts | 9 | ||||
| -rw-r--r-- | dts/src/arm64/bitmain/bm1880.dtsi | 28 |
2 files changed, 28 insertions, 9 deletions
diff --git a/dts/src/arm64/bitmain/bm1880-sophon-edge.dts b/dts/src/arm64/bitmain/bm1880-sophon-edge.dts index 3e8c70778e..7a2c7f9c26 100644 --- a/dts/src/arm64/bitmain/bm1880-sophon-edge.dts +++ b/dts/src/arm64/bitmain/bm1880-sophon-edge.dts @@ -49,12 +49,6 @@ reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB }; - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <500000000>; - #clock-cells = <0>; - }; - soc { gpio0: gpio@50027000 { porta: gpio-controller@0 { @@ -173,21 +167,18 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &uart2 { status = "okay"; - clocks = <&uart_clk>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_default>; }; diff --git a/dts/src/arm64/bitmain/bm1880.dtsi b/dts/src/arm64/bitmain/bm1880.dtsi index d65453f99a..fa6e6905f5 100644 --- a/dts/src/arm64/bitmain/bm1880.dtsi +++ b/dts/src/arm64/bitmain/bm1880.dtsi @@ -4,6 +4,7 @@ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> */ +#include <dt-bindings/clock/bm1880-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/bitmain,bm1880-reset.h> @@ -66,6 +67,12 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + osc: osc { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -94,6 +101,15 @@ reg = <0x400 0x120>; }; + clk: clock-controller@e8 { + compatible = "bitmain,bm1880-clk"; + reg = <0xe8 0x0c>, <0x800 0xb0>; + reg-names = "pll", "sys"; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + }; + rst: reset-controller@c00 { compatible = "bitmain,bm1880-reset"; reg = <0xc00 0x8>; @@ -158,6 +174,9 @@ uart0: serial@58018000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x58018000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -168,6 +187,9 @@ uart1: serial@5801A000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801a000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -178,6 +200,9 @@ uart2: serial@5801C000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801c000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; @@ -188,6 +213,9 @@ uart3: serial@5801E000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x5801e000 0x0 0x2000>; + clocks = <&clk BM1880_CLK_UART_500M>, + <&clk BM1880_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; |