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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-04-12 10:22:44 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-04-14 09:33:24 +0200 |
| commit | b01786baa849369ff2345c51e63857c952a01130 (patch) | |
| tree | 43970a0ff46d32b8cad45b1dc3f3ca638e04fc5e /dts/src/arm64/freescale/imx8mm-venice-gw72xx-0x-rs485.dts | |
| parent | 610797b376e65475f7aed1218a085ff8701da474 (diff) | |
| download | barebox-b01786baa849369ff2345c51e63857c952a01130.tar.gz barebox-b01786baa849369ff2345c51e63857c952a01130.tar.xz | |
dts: update to v5.18-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/freescale/imx8mm-venice-gw72xx-0x-rs485.dts')
| -rw-r--r-- | dts/src/arm64/freescale/imx8mm-venice-gw72xx-0x-rs485.dts | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/dts/src/arm64/freescale/imx8mm-venice-gw72xx-0x-rs485.dts b/dts/src/arm64/freescale/imx8mm-venice-gw72xx-0x-rs485.dts new file mode 100644 index 0000000000..cc0a287226 --- /dev/null +++ b/dts/src/arm64/freescale/imx8mm-venice-gw72xx-0x-rs485.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS485 HD: + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven high (active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be pulled high + */ + +#include <dt-bindings/gpio/gpio.h> + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; |