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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-05 12:56:25 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-07 11:41:05 +0100 |
commit | 6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef (patch) | |
tree | 5d16ca525c12dddb21d9c4750dfd1a1e354eb731 /dts/src/arm64/freescale/imx8mp.dtsi | |
parent | 93c4690b4921d3149db3fcf5b62a8aa5010a4ae7 (diff) | |
download | barebox-6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef.tar.gz barebox-6ea3de1b8ce7a0154233bd75e77e6e44a525d0ef.tar.xz |
dts: update to v5.11-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/freescale/imx8mp.dtsi')
-rw-r--r-- | dts/src/arm64/freescale/imx8mp.dtsi | 45 |
1 files changed, 41 insertions, 4 deletions
diff --git a/dts/src/arm64/freescale/imx8mp.dtsi b/dts/src/arm64/freescale/imx8mp.dtsi index 6038f66aef..ecccfbb4f5 100644 --- a/dts/src/arm64/freescale/imx8mp.dtsi +++ b/dts/src/arm64/freescale/imx8mp.dtsi @@ -133,6 +133,13 @@ clock-output-names = "clk_ext4"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -202,10 +209,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; @@ -545,6 +552,36 @@ status = "disabled"; }; + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 5>; + status = "disabled"; + }; + crypto: crypto@30900000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; |