diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-11-09 12:38:26 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-11-09 13:42:10 +0100 |
| commit | 119c632f12509eab4bc58daf629c4b16fffcedca (patch) | |
| tree | 34366b3095d957178b46be47f628a3926ad35ac3 /dts/src/arm64/freescale/imx8mq-pico-pi.dts | |
| parent | 89b766c63f94b5fe94db75a6f197c9e6c0f9da7e (diff) | |
| download | barebox-119c632f12509eab4bc58daf629c4b16fffcedca.tar.gz barebox-119c632f12509eab4bc58daf629c4b16fffcedca.tar.xz | |
dts: update to v5.10-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/freescale/imx8mq-pico-pi.dts')
| -rw-r--r-- | dts/src/arm64/freescale/imx8mq-pico-pi.dts | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/dts/src/arm64/freescale/imx8mq-pico-pi.dts b/dts/src/arm64/freescale/imx8mq-pico-pi.dts index 59da96b714..89cbec5c41 100644 --- a/dts/src/arm64/freescale/imx8mq-pico-pi.dts +++ b/dts/src/arm64/freescale/imx8mq-pico-pi.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "imx8mq.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> / { model = "TechNexion PICO-PI-8M"; @@ -70,7 +71,7 @@ clock-names = "osc"; clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; regulators { @@ -297,7 +298,7 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 >; @@ -335,7 +336,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 @@ -351,7 +352,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 @@ -367,7 +368,7 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2grpgpio { + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 >; @@ -385,7 +386,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 @@ -397,7 +398,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 |