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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-08-24 08:46:04 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-08-25 15:39:39 +0200 |
| commit | eddd8312948329e28f00a6f1ca52b3e7f3c330ee (patch) | |
| tree | 1b4ef77f92f72af55f853e09be1789a4206fbcb6 /dts/src/arm64/nvidia/tegra186.dtsi | |
| parent | eed776a50f486d4c1951da32a30d3fd1588ac6e2 (diff) | |
| download | barebox-eddd8312948329e28f00a6f1ca52b3e7f3c330ee.tar.gz barebox-eddd8312948329e28f00a6f1ca52b3e7f3c330ee.tar.xz | |
dts: update to v6.0-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/nvidia/tegra186.dtsi')
| -rw-r--r-- | dts/src/arm64/nvidia/tegra186.dtsi | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/dts/src/arm64/nvidia/tegra186.dtsi b/dts/src/arm64/nvidia/tegra186.dtsi index 0e9afc3e2f..59a10fb184 100644 --- a/dts/src/arm64/nvidia/tegra186.dtsi +++ b/dts/src/arm64/nvidia/tegra186.dtsi @@ -509,6 +509,29 @@ status = "disabled"; }; + tegra_ope1: processing-engine@2908000 { + compatible = "nvidia,tegra186-ope", + "nvidia,tegra210-ope"; + reg = <0x2908000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sound-name-prefix = "OPE1"; + status = "disabled"; + + equalizer@2908100 { + compatible = "nvidia,tegra186-peq", + "nvidia,tegra210-peq"; + reg = <0x2908100 0x100>; + }; + + dynamic-range-compressor@2908200 { + compatible = "nvidia,tegra186-mbdrc", + "nvidia,tegra210-mbdrc"; + reg = <0x2908200 0x200>; + }; + }; + tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra186-amixer", "nvidia,tegra210-amixer"; @@ -576,7 +599,7 @@ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; + status = "okay"; }; uarta: serial@3100000 { @@ -1461,6 +1484,17 @@ iommus = <&smmu TEGRA186_SID_HOST1X>; + /* Context isolation domains */ + iommu-map = < + 0 &smmu TEGRA186_SID_HOST1X_CTX0 1 + 1 &smmu TEGRA186_SID_HOST1X_CTX1 1 + 2 &smmu TEGRA186_SID_HOST1X_CTX2 1 + 3 &smmu TEGRA186_SID_HOST1X_CTX3 1 + 4 &smmu TEGRA186_SID_HOST1X_CTX4 1 + 5 &smmu TEGRA186_SID_HOST1X_CTX5 1 + 6 &smmu TEGRA186_SID_HOST1X_CTX6 1 + 7 &smmu TEGRA186_SID_HOST1X_CTX7 1>; + dpaux1: dpaux@15040000 { compatible = "nvidia,tegra186-dpaux"; reg = <0x15040000 0x10000>; @@ -1820,6 +1854,7 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x30000000 0x50000>; + no-memory-wc; cpu_bpmp_tx: sram@4e000 { reg = <0x4e000 0x1000>; |