diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2023-03-15 10:57:00 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-03-15 13:24:47 +0100 |
| commit | 03b1dd74aa6e8307dde254efe7f1450630362a8a (patch) | |
| tree | 66ee5ede9991313a2ce7a9171d51312ffd9d9a26 /dts/src/arm64/nvidia | |
| parent | dd86cdf21582baec789488301b881f8b183cbdfa (diff) | |
| download | barebox-03b1dd74aa6e8307dde254efe7f1450630362a8a.tar.gz barebox-03b1dd74aa6e8307dde254efe7f1450630362a8a.tar.xz | |
dts: update to v6.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/nvidia')
23 files changed, 8367 insertions, 8033 deletions
diff --git a/dts/src/arm64/nvidia/tegra132-norrin.dts b/dts/src/arm64/nvidia/tegra132-norrin.dts index 3e8dee85d5..d4c034ac12 100644 --- a/dts/src/arm64/nvidia/tegra132-norrin.dts +++ b/dts/src/arm64/nvidia/tegra132-norrin.dts @@ -1030,6 +1030,14 @@ gpio-keys { compatible = "gpio-keys"; + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-source; + }; + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; @@ -1038,14 +1046,6 @@ debounce-interval = <1>; wakeup-source; }; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - wakeup-source; - }; }; panel: panel { diff --git a/dts/src/arm64/nvidia/tegra132.dtsi b/dts/src/arm64/nvidia/tegra132.dtsi index 858fc01cec..c017764bc2 100644 --- a/dts/src/arm64/nvidia/tegra132.dtsi +++ b/dts/src/arm64/nvidia/tegra132.dtsi @@ -893,122 +893,6 @@ }; }; - thermal-zones { - cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <102000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; - - trips { - mem_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - mem_throttle_trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - - gpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; - - trips { - gpu_shutdown_trip { - temperature = <101000>; - hysteresis = <1000>; - type = "critical"; - }; - - gpu_throttle_trip: throttle-trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - - pllx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; - - trips { - pllx_shutdown_trip { - temperature = <105000>; - hysteresis = <1000>; - type = "critical"; - }; - pllx_throttle_trip { - temperature = <99000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ - }; - }; - }; - ahub@70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, @@ -1255,6 +1139,122 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu_shutdown_trip { + temperature = <105000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_throttle_trip: throttle-trip { + temperature = <102000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + + trips { + mem_shutdown_trip { + temperature = <101000>; + hysteresis = <1000>; + type = "critical"; + }; + mem_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + + gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + + trips { + gpu_shutdown_trip { + temperature = <101000>; + hysteresis = <1000>; + type = "critical"; + }; + + gpu_throttle_trip: throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + + pllx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx_shutdown_trip { + temperature = <105000>; + hysteresis = <1000>; + type = "critical"; + }; + pllx_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 diff --git a/dts/src/arm64/nvidia/tegra186-p2771-0000.dts b/dts/src/arm64/nvidia/tegra186-p2771-0000.dts index 47cf2013af..15aa49fc45 100644 --- a/dts/src/arm64/nvidia/tegra186-p2771-0000.dts +++ b/dts/src/arm64/nvidia/tegra186-p2771-0000.dts @@ -13,1095 +13,9 @@ aconnect@2900000 { status = "okay"; - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - ahub@2900800 { status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0_ep: endpoint { - remote-endpoint = <&admaif0_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1_ep: endpoint { - remote-endpoint = <&admaif1_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2_ep: endpoint { - remote-endpoint = <&admaif2_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3_ep: endpoint { - remote-endpoint = <&admaif3_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4_ep: endpoint { - remote-endpoint = <&admaif4_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5_ep: endpoint { - remote-endpoint = <&admaif5_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6_ep: endpoint { - remote-endpoint = <&admaif6_ep>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7_ep: endpoint { - remote-endpoint = <&admaif7_ep>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8_ep: endpoint { - remote-endpoint = <&admaif8_ep>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9_ep: endpoint { - remote-endpoint = <&admaif9_ep>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10_ep: endpoint { - remote-endpoint = <&admaif10_ep>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11_ep: endpoint { - remote-endpoint = <&admaif11_ep>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12_ep: endpoint { - remote-endpoint = <&admaif12_ep>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13_ep: endpoint { - remote-endpoint = <&admaif13_ep>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14_ep: endpoint { - remote-endpoint = <&admaif14_ep>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15_ep: endpoint { - remote-endpoint = <&admaif15_ep>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16_ep: endpoint { - remote-endpoint = <&admaif16_ep>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17_ep: endpoint { - remote-endpoint = <&admaif17_ep>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18_ep: endpoint { - remote-endpoint = <&admaif18_ep>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19_ep: endpoint { - remote-endpoint = <&admaif19_ep>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1_ep: endpoint { - remote-endpoint = <&i2s1_cif_ep>; - }; - }; - - xbar_i2s2_port: port@15 { - reg = <0x15>; - - xbar_i2s2_ep: endpoint { - remote-endpoint = <&i2s2_cif_ep>; - }; - }; - - xbar_i2s3_port: port@16 { - reg = <0x16>; - - xbar_i2s3_ep: endpoint { - remote-endpoint = <&i2s3_cif_ep>; - }; - }; - - xbar_i2s4_port: port@17 { - reg = <0x17>; - - xbar_i2s4_ep: endpoint { - remote-endpoint = <&i2s4_cif_ep>; - }; - }; - - xbar_i2s5_port: port@18 { - reg = <0x18>; - - xbar_i2s5_ep: endpoint { - remote-endpoint = <&i2s5_cif_ep>; - }; - }; - - xbar_i2s6_port: port@19 { - reg = <0x19>; - - xbar_i2s6_ep: endpoint { - remote-endpoint = <&i2s6_cif_ep>; - }; - }; - - xbar_dmic1_port: port@1a { - reg = <0x1a>; - - xbar_dmic1_ep: endpoint { - remote-endpoint = <&dmic1_cif_ep>; - }; - }; - - xbar_dmic2_port: port@1b { - reg = <0x1b>; - - xbar_dmic2_ep: endpoint { - remote-endpoint = <&dmic2_cif_ep>; - }; - }; - - xbar_dmic3_port: port@1c { - reg = <0x1c>; - - xbar_dmic3_ep: endpoint { - remote-endpoint = <&dmic3_cif_ep>; - }; - }; - - xbar_dspk1_port: port@1e { - reg = <0x1e>; - - xbar_dspk1_ep: endpoint { - remote-endpoint = <&dspk1_cif_ep>; - }; - }; - - xbar_dspk2_port: port@1f { - reg = <0x1f>; - - xbar_dspk2_ep: endpoint { - remote-endpoint = <&dspk2_cif_ep>; - }; - }; - - xbar_sfc1_in_port: port@20 { - reg = <0x20>; - - xbar_sfc1_in_ep: endpoint { - remote-endpoint = <&sfc1_cif_in_ep>; - }; - }; - - port@21 { - reg = <0x21>; - - xbar_sfc1_out_ep: endpoint { - remote-endpoint = <&sfc1_cif_out_ep>; - }; - }; - - xbar_sfc2_in_port: port@22 { - reg = <0x22>; - - xbar_sfc2_in_ep: endpoint { - remote-endpoint = <&sfc2_cif_in_ep>; - }; - }; - - port@23 { - reg = <0x23>; - - xbar_sfc2_out_ep: endpoint { - remote-endpoint = <&sfc2_cif_out_ep>; - }; - }; - - xbar_sfc3_in_port: port@24 { - reg = <0x24>; - - xbar_sfc3_in_ep: endpoint { - remote-endpoint = <&sfc3_cif_in_ep>; - }; - }; - - port@25 { - reg = <0x25>; - - xbar_sfc3_out_ep: endpoint { - remote-endpoint = <&sfc3_cif_out_ep>; - }; - }; - - xbar_sfc4_in_port: port@26 { - reg = <0x26>; - - xbar_sfc4_in_ep: endpoint { - remote-endpoint = <&sfc4_cif_in_ep>; - }; - }; - - port@27 { - reg = <0x27>; - - xbar_sfc4_out_ep: endpoint { - remote-endpoint = <&sfc4_cif_out_ep>; - }; - }; - - xbar_mvc1_in_port: port@28 { - reg = <0x28>; - - xbar_mvc1_in_ep: endpoint { - remote-endpoint = <&mvc1_cif_in_ep>; - }; - }; - - port@29 { - reg = <0x29>; - - xbar_mvc1_out_ep: endpoint { - remote-endpoint = <&mvc1_cif_out_ep>; - }; - }; - - xbar_mvc2_in_port: port@2a { - reg = <0x2a>; - - xbar_mvc2_in_ep: endpoint { - remote-endpoint = <&mvc2_cif_in_ep>; - }; - }; - - port@2b { - reg = <0x2b>; - - xbar_mvc2_out_ep: endpoint { - remote-endpoint = <&mvc2_cif_out_ep>; - }; - }; - - xbar_amx1_in1_port: port@2c { - reg = <0x2c>; - - xbar_amx1_in1_ep: endpoint { - remote-endpoint = <&amx1_in1_ep>; - }; - }; - - xbar_amx1_in2_port: port@2d { - reg = <0x2d>; - - xbar_amx1_in2_ep: endpoint { - remote-endpoint = <&amx1_in2_ep>; - }; - }; - - xbar_amx1_in3_port: port@2e { - reg = <0x2e>; - - xbar_amx1_in3_ep: endpoint { - remote-endpoint = <&amx1_in3_ep>; - }; - }; - - xbar_amx1_in4_port: port@2f { - reg = <0x2f>; - - xbar_amx1_in4_ep: endpoint { - remote-endpoint = <&amx1_in4_ep>; - }; - }; - - port@30 { - reg = <0x30>; - - xbar_amx1_out_ep: endpoint { - remote-endpoint = <&amx1_out_ep>; - }; - }; - - xbar_amx2_in1_port: port@31 { - reg = <0x31>; - - xbar_amx2_in1_ep: endpoint { - remote-endpoint = <&amx2_in1_ep>; - }; - }; - - xbar_amx2_in2_port: port@32 { - reg = <0x32>; - - xbar_amx2_in2_ep: endpoint { - remote-endpoint = <&amx2_in2_ep>; - }; - }; - - xbar_amx2_in3_port: port@33 { - reg = <0x33>; - - xbar_amx2_in3_ep: endpoint { - remote-endpoint = <&amx2_in3_ep>; - }; - }; - - xbar_amx2_in4_port: port@34 { - reg = <0x34>; - - xbar_amx2_in4_ep: endpoint { - remote-endpoint = <&amx2_in4_ep>; - }; - }; - - port@35 { - reg = <0x35>; - - xbar_amx2_out_ep: endpoint { - remote-endpoint = <&amx2_out_ep>; - }; - }; - - xbar_amx3_in1_port: port@36 { - reg = <0x36>; - - xbar_amx3_in1_ep: endpoint { - remote-endpoint = <&amx3_in1_ep>; - }; - }; - - xbar_amx3_in2_port: port@37 { - reg = <0x37>; - - xbar_amx3_in2_ep: endpoint { - remote-endpoint = <&amx3_in2_ep>; - }; - }; - - xbar_amx3_in3_port: port@38 { - reg = <0x38>; - - xbar_amx3_in3_ep: endpoint { - remote-endpoint = <&amx3_in3_ep>; - }; - }; - - xbar_amx3_in4_port: port@39 { - reg = <0x39>; - - xbar_amx3_in4_ep: endpoint { - remote-endpoint = <&amx3_in4_ep>; - }; - }; - - port@3a { - reg = <0x3a>; - - xbar_amx3_out_ep: endpoint { - remote-endpoint = <&amx3_out_ep>; - }; - }; - - xbar_amx4_in1_port: port@3b { - reg = <0x3b>; - - xbar_amx4_in1_ep: endpoint { - remote-endpoint = <&amx4_in1_ep>; - }; - }; - - xbar_amx4_in2_port: port@3c { - reg = <0x3c>; - - xbar_amx4_in2_ep: endpoint { - remote-endpoint = <&amx4_in2_ep>; - }; - }; - - xbar_amx4_in3_port: port@3d { - reg = <0x3d>; - - xbar_amx4_in3_ep: endpoint { - remote-endpoint = <&amx4_in3_ep>; - }; - }; - - xbar_amx4_in4_port: port@3e { - reg = <0x3e>; - - xbar_amx4_in4_ep: endpoint { - remote-endpoint = <&amx4_in4_ep>; - }; - }; - - port@3f { - reg = <0x3f>; - - xbar_amx4_out_ep: endpoint { - remote-endpoint = <&amx4_out_ep>; - }; - }; - - xbar_adx1_in_port: port@40 { - reg = <0x40>; - - xbar_adx1_in_ep: endpoint { - remote-endpoint = <&adx1_in_ep>; - }; - }; - - port@41 { - reg = <0x41>; - - xbar_adx1_out1_ep: endpoint { - remote-endpoint = <&adx1_out1_ep>; - }; - }; - - port@42 { - reg = <0x42>; - - xbar_adx1_out2_ep: endpoint { - remote-endpoint = <&adx1_out2_ep>; - }; - }; - - port@43 { - reg = <0x43>; - - xbar_adx1_out3_ep: endpoint { - remote-endpoint = <&adx1_out3_ep>; - }; - }; - - port@44 { - reg = <0x44>; - - xbar_adx1_out4_ep: endpoint { - remote-endpoint = <&adx1_out4_ep>; - }; - }; - - xbar_adx2_in_port: port@45 { - reg = <0x45>; - - xbar_adx2_in_ep: endpoint { - remote-endpoint = <&adx2_in_ep>; - }; - }; - - port@46 { - reg = <0x46>; - - xbar_adx2_out1_ep: endpoint { - remote-endpoint = <&adx2_out1_ep>; - }; - }; - - port@47 { - reg = <0x47>; - - xbar_adx2_out2_ep: endpoint { - remote-endpoint = <&adx2_out2_ep>; - }; - }; - - port@48 { - reg = <0x48>; - - xbar_adx2_out3_ep: endpoint { - remote-endpoint = <&adx2_out3_ep>; - }; - }; - - port@49 { - reg = <0x49>; - - xbar_adx2_out4_ep: endpoint { - remote-endpoint = <&adx2_out4_ep>; - }; - }; - - xbar_adx3_in_port: port@4a { - reg = <0x4a>; - - xbar_adx3_in_ep: endpoint { - remote-endpoint = <&adx3_in_ep>; - }; - }; - - port@4b { - reg = <0x4b>; - - xbar_adx3_out1_ep: endpoint { - remote-endpoint = <&adx3_out1_ep>; - }; - }; - - port@4c { - reg = <0x4c>; - - xbar_adx3_out2_ep: endpoint { - remote-endpoint = <&adx3_out2_ep>; - }; - }; - - port@4d { - reg = <0x4d>; - - xbar_adx3_out3_ep: endpoint { - remote-endpoint = <&adx3_out3_ep>; - }; - }; - - port@4e { - reg = <0x4e>; - - xbar_adx3_out4_ep: endpoint { - remote-endpoint = <&adx3_out4_ep>; - }; - }; - - xbar_adx4_in_port: port@4f { - reg = <0x4f>; - - xbar_adx4_in_ep: endpoint { - remote-endpoint = <&adx4_in_ep>; - }; - }; - - port@50 { - reg = <0x50>; - - xbar_adx4_out1_ep: endpoint { - remote-endpoint = <&adx4_out1_ep>; - }; - }; - - port@51 { - reg = <0x51>; - - xbar_adx4_out2_ep: endpoint { - remote-endpoint = <&adx4_out2_ep>; - }; - }; - - port@52 { - reg = <0x52>; - - xbar_adx4_out3_ep: endpoint { - remote-endpoint = <&adx4_out3_ep>; - }; - }; - - port@53 { - reg = <0x53>; - - xbar_adx4_out4_ep: endpoint { - remote-endpoint = <&adx4_out4_ep>; - }; - }; - - xbar_mixer_in1_port: port@54 { - reg = <0x54>; - - xbar_mixer_in1_ep: endpoint { - remote-endpoint = <&mixer_in1_ep>; - }; - }; - - xbar_mixer_in2_port: port@55 { - reg = <0x55>; - - xbar_mixer_in2_ep: endpoint { - remote-endpoint = <&mixer_in2_ep>; - }; - }; - - xbar_mixer_in3_port: port@56 { - reg = <0x56>; - - xbar_mixer_in3_ep: endpoint { - remote-endpoint = <&mixer_in3_ep>; - }; - }; - - xbar_mixer_in4_port: port@57 { - reg = <0x57>; - - xbar_mixer_in4_ep: endpoint { - remote-endpoint = <&mixer_in4_ep>; - }; - }; - - xbar_mixer_in5_port: port@58 { - reg = <0x58>; - - xbar_mixer_in5_ep: endpoint { - remote-endpoint = <&mixer_in5_ep>; - }; - }; - - xbar_mixer_in6_port: port@59 { - reg = <0x59>; - - xbar_mixer_in6_ep: endpoint { - remote-endpoint = <&mixer_in6_ep>; - }; - }; - - xbar_mixer_in7_port: port@5a { - reg = <0x5a>; - - xbar_mixer_in7_ep: endpoint { - remote-endpoint = <&mixer_in7_ep>; - }; - }; - - xbar_mixer_in8_port: port@5b { - reg = <0x5b>; - - xbar_mixer_in8_ep: endpoint { - remote-endpoint = <&mixer_in8_ep>; - }; - }; - - xbar_mixer_in9_port: port@5c { - reg = <0x5c>; - - xbar_mixer_in9_ep: endpoint { - remote-endpoint = <&mixer_in9_ep>; - }; - }; - - xbar_mixer_in10_port: port@5d { - reg = <0x5d>; - - xbar_mixer_in10_ep: endpoint { - remote-endpoint = <&mixer_in10_ep>; - }; - }; - - port@5e { - reg = <0x5e>; - - xbar_mixer_out1_ep: endpoint { - remote-endpoint = <&mixer_out1_ep>; - }; - }; - - port@5f { - reg = <0x5f>; - - xbar_mixer_out2_ep: endpoint { - remote-endpoint = <&mixer_out2_ep>; - }; - }; - - port@60 { - reg = <0x60>; - - xbar_mixer_out3_ep: endpoint { - remote-endpoint = <&mixer_out3_ep>; - }; - }; - - port@61 { - reg = <0x61>; - - xbar_mixer_out4_ep: endpoint { - remote-endpoint = <&mixer_out4_ep>; - }; - }; - - port@62 { - reg = <0x62>; - - xbar_mixer_out5_ep: endpoint { - remote-endpoint = <&mixer_out5_ep>; - }; - }; - - xbar_asrc_in1_port: port@63 { - reg = <0x63>; - - xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; - }; - }; - - port@64 { - reg = <0x64>; - - xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; - }; - }; - - xbar_asrc_in2_port: port@65 { - reg = <0x65>; - - xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; - }; - }; - - port@66 { - reg = <0x66>; - - xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; - }; - }; - - xbar_asrc_in3_port: port@67 { - reg = <0x67>; - - xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; - }; - }; - - port@68 { - reg = <0x68>; - - xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; - }; - }; - - xbar_asrc_in4_port: port@69 { - reg = <0x69>; - - xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; - }; - }; - - port@6a { - reg = <0x6a>; - - xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; - }; - }; - - xbar_asrc_in5_port: port@6b { - reg = <0x6b>; - - xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; - }; - }; - - port@6c { - reg = <0x6c>; - - xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; - }; - }; - - xbar_asrc_in6_port: port@6d { - reg = <0x6d>; - - xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; - }; - }; - - port@6e { - reg = <0x6e>; - - xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; - }; - }; - - xbar_asrc_in7_port: port@6f { - reg = <0x6f>; - - xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; - }; - }; - - xbar_ope1_in_port: port@70 { - reg = <0x70>; - - xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; - }; - }; - - port@71 { - reg = <0x71>; - - xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; - }; - }; - }; - - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; - }; - }; - }; - i2s@2901000 { status = "okay"; @@ -1258,131 +172,6 @@ }; }; - dmic@2904000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic3_ep>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dspk@2905000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dspk1_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk1_ep>; - }; - }; - - dspk1_port: port@1 { - reg = <1>; - - dspk1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dspk@2905100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dspk2_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk2_ep>; - }; - }; - - dspk2_port: port@1 { - reg = <1>; - - dspk2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - sfc@2902000 { status = "okay"; @@ -1485,56 +274,6 @@ }; }; - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - amx@2903000 { status = "okay"; @@ -1927,6 +666,131 @@ }; }; + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; + }; + + dspk2_port: port@1 { + reg = <1>; + + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + processing-engine@2908000 { status = "okay"; @@ -1952,6 +816,56 @@ }; }; + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + amixer@290bb00 { status = "okay"; @@ -2081,6 +995,175 @@ }; }; + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + asrc@2910000 { status = "okay"; @@ -2184,7 +1267,7 @@ }; }; - asrc_out6_port: port@c { + asrc_out6_port: port@c { reg = <0xc>; asrc_out6_ep: endpoint { @@ -2193,6 +1276,923 @@ }; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2_ep: endpoint { + remote-endpoint = <&i2s2_cif_ep>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4_ep: endpoint { + remote-endpoint = <&i2s4_cif_ep>; + }; + }; + + xbar_i2s5_port: port@18 { + reg = <0x18>; + + xbar_i2s5_ep: endpoint { + remote-endpoint = <&i2s5_cif_ep>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6_ep: endpoint { + remote-endpoint = <&i2s6_cif_ep>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3_ep: endpoint { + remote-endpoint = <&dmic3_cif_ep>; + }; + }; + + xbar_dspk1_port: port@1e { + reg = <0x1e>; + + xbar_dspk1_ep: endpoint { + remote-endpoint = <&dspk1_cif_ep>; + }; + }; + + xbar_dspk2_port: port@1f { + reg = <0x1f>; + + xbar_dspk2_ep: endpoint { + remote-endpoint = <&dspk2_cif_ep>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in_ep: endpoint { + remote-endpoint = <&sfc1_cif_in_ep>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out_ep: endpoint { + remote-endpoint = <&sfc1_cif_out_ep>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in_ep: endpoint { + remote-endpoint = <&sfc2_cif_in_ep>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out_ep: endpoint { + remote-endpoint = <&sfc2_cif_out_ep>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in_ep: endpoint { + remote-endpoint = <&sfc3_cif_in_ep>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out_ep: endpoint { + remote-endpoint = <&sfc3_cif_out_ep>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in_ep: endpoint { + remote-endpoint = <&sfc4_cif_in_ep>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out_ep: endpoint { + remote-endpoint = <&sfc4_cif_out_ep>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in_ep: endpoint { + remote-endpoint = <&mvc1_cif_in_ep>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out_ep: endpoint { + remote-endpoint = <&mvc1_cif_out_ep>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in_ep: endpoint { + remote-endpoint = <&mvc2_cif_in_ep>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out_ep: endpoint { + remote-endpoint = <&mvc2_cif_out_ep>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1_ep: endpoint { + remote-endpoint = <&amx1_in1_ep>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2_ep: endpoint { + remote-endpoint = <&amx1_in2_ep>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3_ep: endpoint { + remote-endpoint = <&amx1_in3_ep>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4_ep: endpoint { + remote-endpoint = <&amx1_in4_ep>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out_ep: endpoint { + remote-endpoint = <&amx1_out_ep>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1_ep: endpoint { + remote-endpoint = <&amx2_in1_ep>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2_ep: endpoint { + remote-endpoint = <&amx2_in2_ep>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3_ep: endpoint { + remote-endpoint = <&amx2_in3_ep>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4_ep: endpoint { + remote-endpoint = <&amx2_in4_ep>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out_ep: endpoint { + remote-endpoint = <&amx2_out_ep>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1_ep: endpoint { + remote-endpoint = <&amx3_in1_ep>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2_ep: endpoint { + remote-endpoint = <&amx3_in2_ep>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3_ep: endpoint { + remote-endpoint = <&amx3_in3_ep>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4_ep: endpoint { + remote-endpoint = <&amx3_in4_ep>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out_ep: endpoint { + remote-endpoint = <&amx3_out_ep>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1_ep: endpoint { + remote-endpoint = <&amx4_in1_ep>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2_ep: endpoint { + remote-endpoint = <&amx4_in2_ep>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3_ep: endpoint { + remote-endpoint = <&amx4_in3_ep>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4_ep: endpoint { + remote-endpoint = <&amx4_in4_ep>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out_ep: endpoint { + remote-endpoint = <&amx4_out_ep>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in_ep: endpoint { + remote-endpoint = <&adx1_in_ep>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1_ep: endpoint { + remote-endpoint = <&adx1_out1_ep>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2_ep: endpoint { + remote-endpoint = <&adx1_out2_ep>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3_ep: endpoint { + remote-endpoint = <&adx1_out3_ep>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4_ep: endpoint { + remote-endpoint = <&adx1_out4_ep>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in_ep: endpoint { + remote-endpoint = <&adx2_in_ep>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1_ep: endpoint { + remote-endpoint = <&adx2_out1_ep>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2_ep: endpoint { + remote-endpoint = <&adx2_out2_ep>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3_ep: endpoint { + remote-endpoint = <&adx2_out3_ep>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4_ep: endpoint { + remote-endpoint = <&adx2_out4_ep>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in_ep: endpoint { + remote-endpoint = <&adx3_in_ep>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1_ep: endpoint { + remote-endpoint = <&adx3_out1_ep>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2_ep: endpoint { + remote-endpoint = <&adx3_out2_ep>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3_ep: endpoint { + remote-endpoint = <&adx3_out3_ep>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4_ep: endpoint { + remote-endpoint = <&adx3_out4_ep>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in_ep: endpoint { + remote-endpoint = <&adx4_in_ep>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1_ep: endpoint { + remote-endpoint = <&adx4_out1_ep>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2_ep: endpoint { + remote-endpoint = <&adx4_out2_ep>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3_ep: endpoint { + remote-endpoint = <&adx4_out3_ep>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4_ep: endpoint { + remote-endpoint = <&adx4_out4_ep>; + }; + }; + + xbar_mixer_in1_port: port@54 { + reg = <0x54>; + + xbar_mixer_in1_ep: endpoint { + remote-endpoint = <&mixer_in1_ep>; + }; + }; + + xbar_mixer_in2_port: port@55 { + reg = <0x55>; + + xbar_mixer_in2_ep: endpoint { + remote-endpoint = <&mixer_in2_ep>; + }; + }; + + xbar_mixer_in3_port: port@56 { + reg = <0x56>; + + xbar_mixer_in3_ep: endpoint { + remote-endpoint = <&mixer_in3_ep>; + }; + }; + + xbar_mixer_in4_port: port@57 { + reg = <0x57>; + + xbar_mixer_in4_ep: endpoint { + remote-endpoint = <&mixer_in4_ep>; + }; + }; + + xbar_mixer_in5_port: port@58 { + reg = <0x58>; + + xbar_mixer_in5_ep: endpoint { + remote-endpoint = <&mixer_in5_ep>; + }; + }; + + xbar_mixer_in6_port: port@59 { + reg = <0x59>; + + xbar_mixer_in6_ep: endpoint { + remote-endpoint = <&mixer_in6_ep>; + }; + }; + + xbar_mixer_in7_port: port@5a { + reg = <0x5a>; + + xbar_mixer_in7_ep: endpoint { + remote-endpoint = <&mixer_in7_ep>; + }; + }; + + xbar_mixer_in8_port: port@5b { + reg = <0x5b>; + + xbar_mixer_in8_ep: endpoint { + remote-endpoint = <&mixer_in8_ep>; + }; + }; + + xbar_mixer_in9_port: port@5c { + reg = <0x5c>; + + xbar_mixer_in9_ep: endpoint { + remote-endpoint = <&mixer_in9_ep>; + }; + }; + + xbar_mixer_in10_port: port@5d { + reg = <0x5d>; + + xbar_mixer_in10_ep: endpoint { + remote-endpoint = <&mixer_in10_ep>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mixer_out1_ep: endpoint { + remote-endpoint = <&mixer_out1_ep>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mixer_out2_ep: endpoint { + remote-endpoint = <&mixer_out2_ep>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mixer_out3_ep: endpoint { + remote-endpoint = <&mixer_out3_ep>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mixer_out4_ep: endpoint { + remote-endpoint = <&mixer_out4_ep>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mixer_out5_ep: endpoint { + remote-endpoint = <&mixer_out5_ep>; + }; + }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; }; }; @@ -2283,6 +2283,10 @@ vmmc-supply = <&vdd_sd>; }; + sata@3507000 { + status = "okay"; + }; + hda@3510000 { nvidia,model = "NVIDIA Jetson TX2 HDA"; status = "okay"; @@ -2471,10 +2475,6 @@ }; }; - sata@3507000 { - status = "okay"; - }; - gpio-keys { compatible = "gpio-keys"; @@ -2489,21 +2489,21 @@ wakeup-source; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) + key-volume-down { + label = "Volume Down"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; + linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <10>; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) + key-volume-up { + label = "Volume Up"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; + linux,code = <KEY_VOLUMEUP>; debounce-interval = <10>; }; }; diff --git a/dts/src/arm64/nvidia/tegra186-p3310.dtsi b/dts/src/arm64/nvidia/tegra186-p3310.dtsi index aff857df25..a4264ea417 100644 --- a/dts/src/arm64/nvidia/tegra186-p3310.dtsi +++ b/dts/src/arm64/nvidia/tegra186-p3310.dtsi @@ -190,32 +190,6 @@ nvidia,invert-interrupt; }; - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - cpu@4 { - enable-method = "psci"; - }; - - cpu@5 { - enable-method = "psci"; - }; - }; - bpmp { i2c { status = "okay"; @@ -235,6 +209,23 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -284,23 +275,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; @@ -387,6 +361,32 @@ }; }; + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + + cpu@4 { + enable-method = "psci"; + }; + + cpu@5 { + enable-method = "psci"; + }; + }; + psci { compatible = "arm,psci-1.0"; status = "okay"; diff --git a/dts/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts b/dts/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts index 3e83a4d52e..26f7165193 100644 --- a/dts/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/dts/src/arm64/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -56,6 +56,490 @@ }; }; + aconnect@2900000 { + status = "okay"; + + ahub@2900800 { + status = "okay"; + + i2s@2901000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + i2s@2901200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0_ep: endpoint { + remote-endpoint = <&admaif0_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1_ep: endpoint { + remote-endpoint = <&admaif1_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2_ep: endpoint { + remote-endpoint = <&admaif2_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3_ep: endpoint { + remote-endpoint = <&admaif3_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4_ep: endpoint { + remote-endpoint = <&admaif4_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5_ep: endpoint { + remote-endpoint = <&admaif5_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6_ep: endpoint { + remote-endpoint = <&admaif6_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7_ep: endpoint { + remote-endpoint = <&admaif7_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8_ep: endpoint { + remote-endpoint = <&admaif8_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9_ep: endpoint { + remote-endpoint = <&admaif9_ep>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10_ep: endpoint { + remote-endpoint = <&admaif10_ep>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11_ep: endpoint { + remote-endpoint = <&admaif11_ep>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12_ep: endpoint { + remote-endpoint = <&admaif12_ep>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13_ep: endpoint { + remote-endpoint = <&admaif13_ep>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14_ep: endpoint { + remote-endpoint = <&admaif14_ep>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15_ep: endpoint { + remote-endpoint = <&admaif15_ep>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16_ep: endpoint { + remote-endpoint = <&admaif16_ep>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17_ep: endpoint { + remote-endpoint = <&admaif17_ep>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18_ep: endpoint { + remote-endpoint = <&admaif18_ep>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19_ep: endpoint { + remote-endpoint = <&admaif19_ep>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1_ep: endpoint { + remote-endpoint = <&i2s1_cif_ep>; + }; + }; + + xbar_i2s3_port: port@16 { + reg = <0x16>; + + xbar_i2s3_ep: endpoint { + remote-endpoint = <&i2s3_cif_ep>; + }; + }; + + xbar_dmic1_port: port@1a { + reg = <0x1a>; + + xbar_dmic1_ep: endpoint { + remote-endpoint = <&dmic1_cif_ep>; + }; + }; + + xbar_dmic2_port: port@1b { + reg = <0x1b>; + + xbar_dmic2_ep: endpoint { + remote-endpoint = <&dmic2_cif_ep>; + }; + }; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + memory-controller@2c00000 { status = "okay"; }; @@ -349,73 +833,6 @@ status = "okay"; }; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_POWER>; - debounce-interval = <10>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEUP>; - debounce-interval = <10>; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) - GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_VOLUMEDOWN>; - debounce-interval = <10>; - }; - }; - - cpus { - cpu@0 { - enable-method = "psci"; - }; - - cpu@1 { - enable-method = "psci"; - }; - - cpu@2 { - enable-method = "psci"; - }; - - cpu@3 { - enable-method = "psci"; - }; - - cpu@4 { - enable-method = "psci"; - }; - - cpu@5 { - enable-method = "psci"; - }; - }; - bpmp { i2c { status = "okay"; @@ -435,6 +852,23 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -484,23 +918,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; @@ -587,12 +1004,79 @@ }; }; + cpus { + cpu@0 { + enable-method = "psci"; + }; + + cpu@1 { + enable-method = "psci"; + }; + + cpu@2 { + enable-method = "psci"; + }; + + cpu@3 { + enable-method = "psci"; + }; + + cpu@4 { + enable-method = "psci"; + }; + + cpu@5 { + enable-method = "psci"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 0) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_POWER>; + debounce-interval = <10>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 2) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <10>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio_aon TEGRA186_AON_GPIO(FF, 1) + GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <10>; + }; + }; + psci { compatible = "arm,psci-1.0"; status = "okay"; method = "smc"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm4 0 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + gnd: regulator-gnd { compatible = "regulator-fixed"; regulator-name = "GND"; @@ -632,6 +1116,26 @@ vin-supply = <&vdd_5v0_sys>; }; + sound { + compatible = "nvidia,tegra186-audio-graph-card"; + status = "okay"; + + dais = /* FE */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* Router */ + <&xbar_i2s1_port>, <&xbar_i2s3_port>, + <&xbar_dmic1_port>, <&xbar_dmic2_port>, + /* I/O */ + <&i2s1_port>, <&i2s3_port>, + <&dmic1_port>, <&dmic2_port>; + + label = "NVIDIA Jetson TX2 NX APE"; + }; + thermal-zones { cpu-thermal { polling-delay = <0>; @@ -715,508 +1219,4 @@ }; }; }; - - aconnect@2900000 { - status = "okay"; - - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - - ahub@2900800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0_ep: endpoint { - remote-endpoint = <&admaif0_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1_ep: endpoint { - remote-endpoint = <&admaif1_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2_ep: endpoint { - remote-endpoint = <&admaif2_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3_ep: endpoint { - remote-endpoint = <&admaif3_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4_ep: endpoint { - remote-endpoint = <&admaif4_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5_ep: endpoint { - remote-endpoint = <&admaif5_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6_ep: endpoint { - remote-endpoint = <&admaif6_ep>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7_ep: endpoint { - remote-endpoint = <&admaif7_ep>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8_ep: endpoint { - remote-endpoint = <&admaif8_ep>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9_ep: endpoint { - remote-endpoint = <&admaif9_ep>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10_ep: endpoint { - remote-endpoint = <&admaif10_ep>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11_ep: endpoint { - remote-endpoint = <&admaif11_ep>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12_ep: endpoint { - remote-endpoint = <&admaif12_ep>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13_ep: endpoint { - remote-endpoint = <&admaif13_ep>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14_ep: endpoint { - remote-endpoint = <&admaif14_ep>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15_ep: endpoint { - remote-endpoint = <&admaif15_ep>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16_ep: endpoint { - remote-endpoint = <&admaif16_ep>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17_ep: endpoint { - remote-endpoint = <&admaif17_ep>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18_ep: endpoint { - remote-endpoint = <&admaif18_ep>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19_ep: endpoint { - remote-endpoint = <&admaif19_ep>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1_ep: endpoint { - remote-endpoint = <&i2s1_cif_ep>; - }; - }; - - xbar_i2s3_port: port@16 { - reg = <0x16>; - - xbar_i2s3_ep: endpoint { - remote-endpoint = <&i2s3_cif_ep>; - }; - }; - - xbar_dmic1_port: port@1a { - reg = <0x1a>; - - xbar_dmic1_ep: endpoint { - remote-endpoint = <&dmic1_cif_ep>; - }; - }; - - xbar_dmic2_port: port@1b { - reg = <0x1b>; - - xbar_dmic2_ep: endpoint { - remote-endpoint = <&dmic2_cif_ep>; - }; - }; - }; - - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; - }; - }; - }; - - i2s@2901000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s1_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s1_ep>; - }; - }; - - i2s1_port: port@1 { - reg = <1>; - - i2s1_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ - }; - }; - }; - }; - - i2s@2901200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s3_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s3_ep>; - }; - }; - - i2s3_port: port@1 { - reg = <1>; - - i2s3_dap_ep: endpoint { - dai-format = "i2s"; - /* Placeholder for external Codec */ - }; - }; - }; - }; - - dmic@2904000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - }; - }; - - sound { - compatible = "nvidia,tegra186-audio-graph-card"; - status = "okay"; - - dais = /* FE */ - <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, - <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, - <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, - <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, - <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, - /* Router */ - <&xbar_i2s1_port>, <&xbar_i2s3_port>, - <&xbar_dmic1_port>, <&xbar_dmic2_port>, - /* I/O */ - <&i2s1_port>, <&i2s3_port>, - <&dmic1_port>, <&dmic2_port>; - - label = "NVIDIA Jetson TX2 NX APE"; - }; }; diff --git a/dts/src/arm64/nvidia/tegra186.dtsi b/dts/src/arm64/nvidia/tegra186.dtsi index b3f1494c02..efc4508213 100644 --- a/dts/src/arm64/nvidia/tegra186.dtsi +++ b/dts/src/arm64/nvidia/tegra186.dtsi @@ -129,62 +129,6 @@ ranges = <0x02900000 0x0 0x02900000 0x200000>; status = "disabled"; - adma: dma-controller@2930000 { - compatible = "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&bpmp TEGRA186_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra186-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = <GIC_SPI 145 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&bpmp TEGRA186_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra186-ahub"; reg = <0x02900800 0x800>; @@ -197,52 +141,6 @@ ranges = <0x02900800 0x02900800 0x11800>; status = "disabled"; - tegra_admaif: admaif@290f000 { - compatible = "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; - dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>; - dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20"; - status = "disabled"; - }; - tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; @@ -327,78 +225,6 @@ status = "disabled"; }; - tegra_dmic1: dmic@2904000 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@2904100 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@2904200 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - - tegra_dmic4: dmic@2904300 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; - clocks = <&bpmp TEGRA186_CLK_DMIC4>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC4"; - status = "disabled"; - }; - - tegra_dspk1: dspk@2905000 { - compatible = "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; - clocks = <&bpmp TEGRA186_CLK_DSPK1>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK1"; - status = "disabled"; - }; - - tegra_dspk2: dspk@2905100 { - compatible = "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; - clocks = <&bpmp TEGRA186_CLK_DSPK2>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK2"; - status = "disabled"; - }; - tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; @@ -431,22 +257,6 @@ status = "disabled"; }; - tegra_mvc1: mvc@290a000 { - compatible = "nvidia,tegra186-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a000 0x200>; - sound-name-prefix = "MVC1"; - status = "disabled"; - }; - - tegra_mvc2: mvc@290a200 { - compatible = "nvidia,tegra186-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a200 0x200>; - sound-name-prefix = "MVC2"; - status = "disabled"; - }; - tegra_amx1: amx@2903000 { compatible = "nvidia,tegra186-amx", "nvidia,tegra210-amx"; @@ -511,6 +321,78 @@ status = "disabled"; }; + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra186-ope", "nvidia,tegra210-ope"; @@ -534,6 +416,22 @@ }; }; + tegra_mvc1: mvc@290a000 { + compatible = "nvidia,tegra186-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a000 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@290a200 { + compatible = "nvidia,tegra186-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a200 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra186-amixer", "nvidia,tegra210-amixer"; @@ -542,6 +440,52 @@ status = "disabled"; }; + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + }; + tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra186-asrc"; reg = <0x2910000 0x2000>; @@ -549,6 +493,62 @@ status = "disabled"; }; }; + + adma: dma-controller@2930000 { + compatible = "nvidia,tegra186-adma"; + reg = <0x02930000 0x20000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&bpmp TEGRA186_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra186-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x02a41000 0x1000>, + <0x02a42000 0x2000>; + interrupts = <GIC_SPI 145 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&bpmp TEGRA186_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; }; mc: memory-controller@2c00000 { @@ -674,8 +674,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C1>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; status = "disabled"; @@ -691,8 +689,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C3>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; status = "disabled"; @@ -712,8 +708,6 @@ pinctrl-names = "default", "idle"; pinctrl-0 = <&state_dpaux1_i2c>; pinctrl-1 = <&state_dpaux1_off>; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; status = "disabled"; @@ -747,8 +741,6 @@ pinctrl-names = "default", "idle"; pinctrl-0 = <&state_dpaux_i2c>; pinctrl-1 = <&state_dpaux_off>; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; status = "disabled"; @@ -764,8 +756,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C7>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; status = "disabled"; @@ -781,8 +771,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C9>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; status = "disabled"; @@ -970,6 +958,34 @@ status = "disabled"; }; + sata@3507000 { + compatible = "nvidia,tegra186-ahci"; + reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ + <0x0 0x03500000 0x0 0x00007000>, /* SATA */ + <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SATA>; + + clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, + <&bpmp TEGRA186_CLK_PLLP>; + assigned-clock-rates = <102000000>, + <204000000>; + resets = <&bpmp TEGRA186_RESET_SATA>, + <&bpmp TEGRA186_RESET_SATACOLD>; + reset-names = "sata", "sata-cold"; + status = "disabled"; + }; + hda@3510000 { compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; reg = <0x0 0x03510000 0x0 0x10000>; @@ -1195,8 +1211,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C2>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 22>, <&gpcdma 22>; dma-names = "rx", "tx"; status = "disabled"; @@ -1212,8 +1226,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA186_RESET_I2C8>; reset-names = "i2c"; - iommus = <&smmu TEGRA186_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 0>, <&gpcdma 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -1286,18 +1298,13 @@ #interrupt-cells = <2>; interrupt-controller; - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - sdmmc1_1v8: sdmmc1-1v8 { pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; - sdmmc2_3v3: sdmmc2-3v3 { - pins = "sdmmc2-hv"; + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; @@ -1306,8 +1313,8 @@ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; + sdmmc2_3v3: sdmmc2-3v3 { + pins = "sdmmc2-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; @@ -1315,6 +1322,11 @@ pins = "sdmmc3-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; }; ccplex@e000000 { @@ -1894,34 +1906,6 @@ }; }; - sata@3507000 { - compatible = "nvidia,tegra186-ahci"; - reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ - <0x0 0x03500000 0x0 0x00007000>, /* SATA */ - <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; - interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, - <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA186_SID_SATA>; - - clocks = <&bpmp TEGRA186_CLK_SATA>, - <&bpmp TEGRA186_CLK_SATA_OOB>; - clock-names = "sata", "sata-oob"; - assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, - <&bpmp TEGRA186_CLK_SATA_OOB>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, - <&bpmp TEGRA186_CLK_PLLP>; - assigned-clock-rates = <102000000>, - <204000000>; - resets = <&bpmp TEGRA186_RESET_SATA>, - <&bpmp TEGRA186_RESET_SATACOLD>; - reset-names = "sata", "sata-cold"; - status = "disabled"; - }; - bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, @@ -2052,14 +2036,7 @@ }; }; - pmu_denver { - compatible = "nvidia,denver-pmu"; - interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&denver_0 &denver_1>; - }; - - pmu_a57 { + pmu-a57 { compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, @@ -2068,6 +2045,13 @@ interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; }; + pmu-denver { + compatible = "nvidia,denver-pmu"; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&denver_0 &denver_1>; + }; + sound { status = "disabled"; diff --git a/dts/src/arm64/nvidia/tegra194-p2888.dtsi b/dts/src/arm64/nvidia/tegra194-p2888.dtsi index cd272d407e..5b59c1986e 100644 --- a/dts/src/arm64/nvidia/tegra194-p2888.dtsi +++ b/dts/src/arm64/nvidia/tegra194-p2888.dtsi @@ -147,6 +147,24 @@ pinctrl-names = "default"; pinctrl-0 = <&max20024_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max20024_default: pinmux { gpio0 { pins = "gpio0"; @@ -190,24 +208,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; diff --git a/dts/src/arm64/nvidia/tegra194-p2972-0000.dts b/dts/src/arm64/nvidia/tegra194-p2972-0000.dts index bc1041d11f..64a3398fe7 100644 --- a/dts/src/arm64/nvidia/tegra194-p2972-0000.dts +++ b/dts/src/arm64/nvidia/tegra194-p2972-0000.dts @@ -14,16 +14,1115 @@ aconnect@2900000 { status = "okay"; - dma-controller@2930000 { + ahub@2900800 { status = "okay"; - }; - interrupt-controller@2a40000 { - status = "okay"; - }; + i2s@2901000 { + status = "okay"; - ahub@2900800 { - status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s1_ep>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap_ep: endpoint { + dai-format = "i2s"; + remote-endpoint = <&rt5658_ep>; + }; + }; + }; + }; + + i2s@2901100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s2_ep>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s4_ep>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901500 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s6_ep>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + sfc@2902000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc1_in_ep>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc1_out_ep>; + }; + }; + }; + }; + + sfc@2902200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc2_in_ep>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc2_out_ep>; + }; + }; + }; + }; + + sfc@2902400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc3_in_ep>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc3_out_ep>; + }; + }; + }; + }; + + sfc@2902600 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc4_in_ep>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc4_out_ep>; + }; + }; + }; + }; + + amx@2903000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1_ep: endpoint { + remote-endpoint = <&xbar_amx1_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2_ep: endpoint { + remote-endpoint = <&xbar_amx1_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3_ep: endpoint { + remote-endpoint = <&xbar_amx1_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4_ep: endpoint { + remote-endpoint = <&xbar_amx1_in4_ep>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out_ep: endpoint { + remote-endpoint = <&xbar_amx1_out_ep>; + }; + }; + }; + }; + + amx@2903100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1_ep: endpoint { + remote-endpoint = <&xbar_amx2_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2_ep: endpoint { + remote-endpoint = <&xbar_amx2_in2_ep>; + }; + }; + + amx2_in3_port: port@2 { + reg = <2>; + + amx2_in3_ep: endpoint { + remote-endpoint = <&xbar_amx2_in3_ep>; + }; + }; + + amx2_in4_port: port@3 { + reg = <3>; + + amx2_in4_ep: endpoint { + remote-endpoint = <&xbar_amx2_in4_ep>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out_ep: endpoint { + remote-endpoint = <&xbar_amx2_out_ep>; + }; + }; + }; + }; + + amx@2903200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1_ep: endpoint { + remote-endpoint = <&xbar_amx3_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2_ep: endpoint { + remote-endpoint = <&xbar_amx3_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3_ep: endpoint { + remote-endpoint = <&xbar_amx3_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4_ep: endpoint { + remote-endpoint = <&xbar_amx3_in4_ep>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out_ep: endpoint { + remote-endpoint = <&xbar_amx3_out_ep>; + }; + }; + }; + }; + + amx@2903300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1_ep: endpoint { + remote-endpoint = <&xbar_amx4_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2_ep: endpoint { + remote-endpoint = <&xbar_amx4_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3_ep: endpoint { + remote-endpoint = <&xbar_amx4_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4_ep: endpoint { + remote-endpoint = <&xbar_amx4_in4_ep>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out_ep: endpoint { + remote-endpoint = <&xbar_amx4_out_ep>; + }; + }; + }; + }; + + adx@2903800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in_ep: endpoint { + remote-endpoint = <&xbar_adx1_in_ep>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1_ep: endpoint { + remote-endpoint = <&xbar_adx1_out1_ep>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2_ep: endpoint { + remote-endpoint = <&xbar_adx1_out2_ep>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3_ep: endpoint { + remote-endpoint = <&xbar_adx1_out3_ep>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4_ep: endpoint { + remote-endpoint = <&xbar_adx1_out4_ep>; + }; + }; + }; + }; + + adx@2903900 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in_ep: endpoint { + remote-endpoint = <&xbar_adx2_in_ep>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1_ep: endpoint { + remote-endpoint = <&xbar_adx2_out1_ep>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2_ep: endpoint { + remote-endpoint = <&xbar_adx2_out2_ep>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3_ep: endpoint { + remote-endpoint = <&xbar_adx2_out3_ep>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4_ep: endpoint { + remote-endpoint = <&xbar_adx2_out4_ep>; + }; + }; + }; + }; + + adx@2903a00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in_ep: endpoint { + remote-endpoint = <&xbar_adx3_in_ep>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1_ep: endpoint { + remote-endpoint = <&xbar_adx3_out1_ep>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2_ep: endpoint { + remote-endpoint = <&xbar_adx3_out2_ep>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3_ep: endpoint { + remote-endpoint = <&xbar_adx3_out3_ep>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4_ep: endpoint { + remote-endpoint = <&xbar_adx3_out4_ep>; + }; + }; + }; + }; + + adx@2903b00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in_ep: endpoint { + remote-endpoint = <&xbar_adx4_in_ep>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1_ep: endpoint { + remote-endpoint = <&xbar_adx4_out1_ep>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2_ep: endpoint { + remote-endpoint = <&xbar_adx4_out2_ep>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3_ep: endpoint { + remote-endpoint = <&xbar_adx4_out3_ep>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4_ep: endpoint { + remote-endpoint = <&xbar_adx4_out4_ep>; + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + + amixer@290bb00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mixer_in1_ep: endpoint { + remote-endpoint = <&xbar_mixer_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + mixer_in2_ep: endpoint { + remote-endpoint = <&xbar_mixer_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + mixer_in3_ep: endpoint { + remote-endpoint = <&xbar_mixer_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + mixer_in4_ep: endpoint { + remote-endpoint = <&xbar_mixer_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + mixer_in5_ep: endpoint { + remote-endpoint = <&xbar_mixer_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + mixer_in6_ep: endpoint { + remote-endpoint = <&xbar_mixer_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + mixer_in7_ep: endpoint { + remote-endpoint = <&xbar_mixer_in7_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + mixer_in8_ep: endpoint { + remote-endpoint = <&xbar_mixer_in8_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + mixer_in9_ep: endpoint { + remote-endpoint = <&xbar_mixer_in9_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + mixer_in10_ep: endpoint { + remote-endpoint = <&xbar_mixer_in10_ep>; + }; + }; + + mixer_out1_port: port@a { + reg = <0xa>; + + mixer_out1_ep: endpoint { + remote-endpoint = <&xbar_mixer_out1_ep>; + }; + }; + + mixer_out2_port: port@b { + reg = <0xb>; + + mixer_out2_ep: endpoint { + remote-endpoint = <&xbar_mixer_out2_ep>; + }; + }; + + mixer_out3_port: port@c { + reg = <0xc>; + + mixer_out3_ep: endpoint { + remote-endpoint = <&xbar_mixer_out3_ep>; + }; + }; + + mixer_out4_port: port@d { + reg = <0xd>; + + mixer_out4_ep: endpoint { + remote-endpoint = <&xbar_mixer_out4_ep>; + }; + }; + + mixer_out5_port: port@e { + reg = <0xe>; + + mixer_out5_ep: endpoint { + remote-endpoint = <&xbar_mixer_out5_ep>; + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; ports { #address-cells = <1>; @@ -885,1113 +1984,14 @@ }; }; }; + }; - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; - }; - }; - }; - - i2s@2901000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s1_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s1_ep>; - }; - }; - - i2s1_port: port@1 { - reg = <1>; - - i2s1_dap_ep: endpoint { - dai-format = "i2s"; - remote-endpoint = <&rt5658_ep>; - }; - }; - }; - }; - - i2s@2901100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s2_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s2_ep>; - }; - }; - - i2s2_port: port@1 { - reg = <1>; - - i2s2_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - i2s@2901300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s4_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s4_ep>; - }; - }; - - i2s4_port: port@1 { - reg = <1>; - - i2s4_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - i2s@2901500 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s6_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s6_ep>; - }; - }; - - i2s6_port: port@1 { - reg = <1>; - - i2s6_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic3_ep>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - sfc@2902000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc1_in_ep>; - }; - }; - - sfc1_out_port: port@1 { - reg = <1>; - - sfc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc1_out_ep>; - }; - }; - }; - }; - - sfc@2902200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc2_in_ep>; - }; - }; - - sfc2_out_port: port@1 { - reg = <1>; - - sfc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc2_out_ep>; - }; - }; - }; - }; - - sfc@2902400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc3_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc3_in_ep>; - }; - }; - - sfc3_out_port: port@1 { - reg = <1>; - - sfc3_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc3_out_ep>; - }; - }; - }; - }; - - sfc@2902600 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc4_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc4_in_ep>; - }; - }; - - sfc4_out_port: port@1 { - reg = <1>; - - sfc4_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc4_out_ep>; - }; - }; - }; - }; - - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - - amx@2903000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx1_in1_ep: endpoint { - remote-endpoint = <&xbar_amx1_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx1_in2_ep: endpoint { - remote-endpoint = <&xbar_amx1_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx1_in3_ep: endpoint { - remote-endpoint = <&xbar_amx1_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx1_in4_ep: endpoint { - remote-endpoint = <&xbar_amx1_in4_ep>; - }; - }; - - amx1_out_port: port@4 { - reg = <4>; - - amx1_out_ep: endpoint { - remote-endpoint = <&xbar_amx1_out_ep>; - }; - }; - }; - }; - - amx@2903100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx2_in1_ep: endpoint { - remote-endpoint = <&xbar_amx2_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx2_in2_ep: endpoint { - remote-endpoint = <&xbar_amx2_in2_ep>; - }; - }; - - amx2_in3_port: port@2 { - reg = <2>; - - amx2_in3_ep: endpoint { - remote-endpoint = <&xbar_amx2_in3_ep>; - }; - }; - - amx2_in4_port: port@3 { - reg = <3>; - - amx2_in4_ep: endpoint { - remote-endpoint = <&xbar_amx2_in4_ep>; - }; - }; - - amx2_out_port: port@4 { - reg = <4>; - - amx2_out_ep: endpoint { - remote-endpoint = <&xbar_amx2_out_ep>; - }; - }; - }; - }; - - amx@2903200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx3_in1_ep: endpoint { - remote-endpoint = <&xbar_amx3_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx3_in2_ep: endpoint { - remote-endpoint = <&xbar_amx3_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx3_in3_ep: endpoint { - remote-endpoint = <&xbar_amx3_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx3_in4_ep: endpoint { - remote-endpoint = <&xbar_amx3_in4_ep>; - }; - }; - - amx3_out_port: port@4 { - reg = <4>; - - amx3_out_ep: endpoint { - remote-endpoint = <&xbar_amx3_out_ep>; - }; - }; - }; - }; - - amx@2903300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx4_in1_ep: endpoint { - remote-endpoint = <&xbar_amx4_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx4_in2_ep: endpoint { - remote-endpoint = <&xbar_amx4_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx4_in3_ep: endpoint { - remote-endpoint = <&xbar_amx4_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx4_in4_ep: endpoint { - remote-endpoint = <&xbar_amx4_in4_ep>; - }; - }; - - amx4_out_port: port@4 { - reg = <4>; - - amx4_out_ep: endpoint { - remote-endpoint = <&xbar_amx4_out_ep>; - }; - }; - }; - }; - - adx@2903800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx1_in_ep: endpoint { - remote-endpoint = <&xbar_adx1_in_ep>; - }; - }; - - adx1_out1_port: port@1 { - reg = <1>; - - adx1_out1_ep: endpoint { - remote-endpoint = <&xbar_adx1_out1_ep>; - }; - }; - - adx1_out2_port: port@2 { - reg = <2>; - - adx1_out2_ep: endpoint { - remote-endpoint = <&xbar_adx1_out2_ep>; - }; - }; - - adx1_out3_port: port@3 { - reg = <3>; - - adx1_out3_ep: endpoint { - remote-endpoint = <&xbar_adx1_out3_ep>; - }; - }; - - adx1_out4_port: port@4 { - reg = <4>; - - adx1_out4_ep: endpoint { - remote-endpoint = <&xbar_adx1_out4_ep>; - }; - }; - }; - }; - - adx@2903900 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx2_in_ep: endpoint { - remote-endpoint = <&xbar_adx2_in_ep>; - }; - }; - - adx2_out1_port: port@1 { - reg = <1>; - - adx2_out1_ep: endpoint { - remote-endpoint = <&xbar_adx2_out1_ep>; - }; - }; - - adx2_out2_port: port@2 { - reg = <2>; - - adx2_out2_ep: endpoint { - remote-endpoint = <&xbar_adx2_out2_ep>; - }; - }; - - adx2_out3_port: port@3 { - reg = <3>; - - adx2_out3_ep: endpoint { - remote-endpoint = <&xbar_adx2_out3_ep>; - }; - }; - - adx2_out4_port: port@4 { - reg = <4>; - - adx2_out4_ep: endpoint { - remote-endpoint = <&xbar_adx2_out4_ep>; - }; - }; - }; - }; - - adx@2903a00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx3_in_ep: endpoint { - remote-endpoint = <&xbar_adx3_in_ep>; - }; - }; - - adx3_out1_port: port@1 { - reg = <1>; - - adx3_out1_ep: endpoint { - remote-endpoint = <&xbar_adx3_out1_ep>; - }; - }; - - adx3_out2_port: port@2 { - reg = <2>; - - adx3_out2_ep: endpoint { - remote-endpoint = <&xbar_adx3_out2_ep>; - }; - }; - - adx3_out3_port: port@3 { - reg = <3>; - - adx3_out3_ep: endpoint { - remote-endpoint = <&xbar_adx3_out3_ep>; - }; - }; - - adx3_out4_port: port@4 { - reg = <4>; - - adx3_out4_ep: endpoint { - remote-endpoint = <&xbar_adx3_out4_ep>; - }; - }; - }; - }; - - adx@2903b00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx4_in_ep: endpoint { - remote-endpoint = <&xbar_adx4_in_ep>; - }; - }; - - adx4_out1_port: port@1 { - reg = <1>; - - adx4_out1_ep: endpoint { - remote-endpoint = <&xbar_adx4_out1_ep>; - }; - }; - - adx4_out2_port: port@2 { - reg = <2>; - - adx4_out2_ep: endpoint { - remote-endpoint = <&xbar_adx4_out2_ep>; - }; - }; - - adx4_out3_port: port@3 { - reg = <3>; - - adx4_out3_ep: endpoint { - remote-endpoint = <&xbar_adx4_out3_ep>; - }; - }; - - adx4_out4_port: port@4 { - reg = <4>; - - adx4_out4_ep: endpoint { - remote-endpoint = <&xbar_adx4_out4_ep>; - }; - }; - }; - }; - - processing-engine@2908000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; - }; - - ope1_out_port: port@1 { - reg = <0x1>; - - ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; - }; - }; - }; - - amixer@290bb00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - mixer_in1_ep: endpoint { - remote-endpoint = <&xbar_mixer_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - mixer_in2_ep: endpoint { - remote-endpoint = <&xbar_mixer_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - mixer_in3_ep: endpoint { - remote-endpoint = <&xbar_mixer_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - mixer_in4_ep: endpoint { - remote-endpoint = <&xbar_mixer_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - mixer_in5_ep: endpoint { - remote-endpoint = <&xbar_mixer_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - mixer_in6_ep: endpoint { - remote-endpoint = <&xbar_mixer_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - mixer_in7_ep: endpoint { - remote-endpoint = <&xbar_mixer_in7_ep>; - }; - }; - - port@7 { - reg = <0x7>; - - mixer_in8_ep: endpoint { - remote-endpoint = <&xbar_mixer_in8_ep>; - }; - }; - - port@8 { - reg = <0x8>; - - mixer_in9_ep: endpoint { - remote-endpoint = <&xbar_mixer_in9_ep>; - }; - }; - - port@9 { - reg = <0x9>; - - mixer_in10_ep: endpoint { - remote-endpoint = <&xbar_mixer_in10_ep>; - }; - }; - - mixer_out1_port: port@a { - reg = <0xa>; - - mixer_out1_ep: endpoint { - remote-endpoint = <&xbar_mixer_out1_ep>; - }; - }; - - mixer_out2_port: port@b { - reg = <0xb>; - - mixer_out2_ep: endpoint { - remote-endpoint = <&xbar_mixer_out2_ep>; - }; - }; - - mixer_out3_port: port@c { - reg = <0xc>; - - mixer_out3_ep: endpoint { - remote-endpoint = <&xbar_mixer_out3_ep>; - }; - }; - - mixer_out4_port: port@d { - reg = <0xd>; - - mixer_out4_ep: endpoint { - remote-endpoint = <&xbar_mixer_out4_ep>; - }; - }; - - mixer_out5_port: port@e { - reg = <0xe>; - - mixer_out5_ep: endpoint { - remote-endpoint = <&xbar_mixer_out5_ep>; - }; - }; - }; - }; - - asrc@2910000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; - }; - - asrc_out1_port: port@7 { - reg = <0x7>; - - asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; - }; - - asrc_out2_port: port@8 { - reg = <0x8>; - - asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; - }; - - asrc_out3_port: port@9 { - reg = <0x9>; - - asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; - }; - - asrc_out4_port: port@a { - reg = <0xa>; - - asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; - }; - - asrc_out5_port: port@b { - reg = <0xb>; - - asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; - }; - - asrc_out6_port: port@c { - reg = <0xc>; + dma-controller@2930000 { + status = "okay"; + }; - asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; - }; - }; - }; + interrupt-controller@2a40000 { + status = "okay"; }; }; @@ -2184,75 +2184,67 @@ GPIO_ACTIVE_LOW>; }; }; - }; - pcie@14100000 { - status = "okay"; + pcie@14100000 { + status = "okay"; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - phys = <&p2u_hsio_0>; - phy-names = "p2u-0"; - }; - - pcie@14140000 { - status = "okay"; + phys = <&p2u_hsio_0>; + phy-names = "p2u-0"; + }; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + pcie@14140000 { + status = "okay"; - phys = <&p2u_hsio_7>; - phy-names = "p2u-0"; - }; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - pcie@14180000 { - status = "okay"; + phys = <&p2u_hsio_7>; + phy-names = "p2u-0"; + }; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + pcie@14180000 { + status = "okay"; - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, - <&p2u_hsio_5>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - pcie@141a0000 { - status = "okay"; + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, + <&p2u_hsio_5>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; - vddio-pex-ctl-supply = <&vdd_1v8ao>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - vpcie12v-supply = <&vdd_12v_pcie>; + pcie@141a0000 { + status = "okay"; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; + vddio-pex-ctl-supply = <&vdd_1v8ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + vpcie12v-supply = <&vdd_12v_pcie>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; - pcie-ep@141a0000 { - status = "disabled"; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + pcie-ep@141a0000 { + status = "disabled"; - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) - GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) + GPIO_ACTIVE_HIGH>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm4 0 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; }; gpio-keys { @@ -2279,6 +2271,14 @@ }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm4 0 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + sound { compatible = "nvidia,tegra186-audio-graph-card"; status = "okay"; diff --git a/dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi b/dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi index f212f6aced..4a17ea5e40 100644 --- a/dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi +++ b/dts/src/arm64/nvidia/tegra194-p3509-0000.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/gpio/tegra194-gpio.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/input/gpio-keys.h> @@ -8,16 +9,1165 @@ aconnect@2900000 { status = "okay"; - dma-controller@2930000 { + ahub@2900800 { status = "okay"; - }; - interrupt-controller@2a40000 { - status = "okay"; - }; + i2s@2901200 { + status = "okay"; - ahub@2900800 { - status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s3_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s3_ep>; + }; + }; + + i2s3_port: port@1 { + reg = <1>; + + i2s3_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + i2s@2901400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s5_cif_ep: endpoint { + remote-endpoint = <&xbar_i2s5_ep>; + }; + }; + + i2s5_port: port@1 { + reg = <1>; + + i2s5_dap_ep: endpoint { + dai-format = "i2s"; + /* Place holder for external Codec */ + }; + }; + }; + }; + + sfc@2902000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc1_in_ep>; + convert-rate = <44100>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc1_out_ep>; + convert-rate = <48000>; + }; + }; + }; + }; + + sfc@2902200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc2_in_ep>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc2_out_ep>; + }; + }; + }; + }; + + sfc@2902400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc3_in_ep>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc3_out_ep>; + }; + }; + }; + }; + + sfc@2902600 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in_ep: endpoint { + remote-endpoint = <&xbar_sfc4_in_ep>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out_ep: endpoint { + remote-endpoint = <&xbar_sfc4_out_ep>; + }; + }; + }; + }; + + amx@2903000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1_ep: endpoint { + remote-endpoint = <&xbar_amx1_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2_ep: endpoint { + remote-endpoint = <&xbar_amx1_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3_ep: endpoint { + remote-endpoint = <&xbar_amx1_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4_ep: endpoint { + remote-endpoint = <&xbar_amx1_in4_ep>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out_ep: endpoint { + remote-endpoint = <&xbar_amx1_out_ep>; + }; + }; + }; + }; + + amx@2903100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1_ep: endpoint { + remote-endpoint = <&xbar_amx2_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2_ep: endpoint { + remote-endpoint = <&xbar_amx2_in2_ep>; + }; + }; + + amx2_in3_port: port@2 { + reg = <2>; + + amx2_in3_ep: endpoint { + remote-endpoint = <&xbar_amx2_in3_ep>; + }; + }; + + amx2_in4_port: port@3 { + reg = <3>; + + amx2_in4_ep: endpoint { + remote-endpoint = <&xbar_amx2_in4_ep>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out_ep: endpoint { + remote-endpoint = <&xbar_amx2_out_ep>; + }; + }; + }; + }; + + amx@2903200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1_ep: endpoint { + remote-endpoint = <&xbar_amx3_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2_ep: endpoint { + remote-endpoint = <&xbar_amx3_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3_ep: endpoint { + remote-endpoint = <&xbar_amx3_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4_ep: endpoint { + remote-endpoint = <&xbar_amx3_in4_ep>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out_ep: endpoint { + remote-endpoint = <&xbar_amx3_out_ep>; + }; + }; + }; + }; + + amx@2903300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1_ep: endpoint { + remote-endpoint = <&xbar_amx4_in1_ep>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2_ep: endpoint { + remote-endpoint = <&xbar_amx4_in2_ep>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3_ep: endpoint { + remote-endpoint = <&xbar_amx4_in3_ep>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4_ep: endpoint { + remote-endpoint = <&xbar_amx4_in4_ep>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out_ep: endpoint { + remote-endpoint = <&xbar_amx4_out_ep>; + }; + }; + }; + }; + + adx@2903800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in_ep: endpoint { + remote-endpoint = <&xbar_adx1_in_ep>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1_ep: endpoint { + remote-endpoint = <&xbar_adx1_out1_ep>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2_ep: endpoint { + remote-endpoint = <&xbar_adx1_out2_ep>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3_ep: endpoint { + remote-endpoint = <&xbar_adx1_out3_ep>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4_ep: endpoint { + remote-endpoint = <&xbar_adx1_out4_ep>; + }; + }; + }; + }; + + adx@2903900 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in_ep: endpoint { + remote-endpoint = <&xbar_adx2_in_ep>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1_ep: endpoint { + remote-endpoint = <&xbar_adx2_out1_ep>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2_ep: endpoint { + remote-endpoint = <&xbar_adx2_out2_ep>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3_ep: endpoint { + remote-endpoint = <&xbar_adx2_out3_ep>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4_ep: endpoint { + remote-endpoint = <&xbar_adx2_out4_ep>; + }; + }; + }; + }; + + adx@2903a00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in_ep: endpoint { + remote-endpoint = <&xbar_adx3_in_ep>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1_ep: endpoint { + remote-endpoint = <&xbar_adx3_out1_ep>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2_ep: endpoint { + remote-endpoint = <&xbar_adx3_out2_ep>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3_ep: endpoint { + remote-endpoint = <&xbar_adx3_out3_ep>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4_ep: endpoint { + remote-endpoint = <&xbar_adx3_out4_ep>; + }; + }; + }; + }; + + adx@2903b00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in_ep: endpoint { + remote-endpoint = <&xbar_adx4_in_ep>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1_ep: endpoint { + remote-endpoint = <&xbar_adx4_out1_ep>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2_ep: endpoint { + remote-endpoint = <&xbar_adx4_out2_ep>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3_ep: endpoint { + remote-endpoint = <&xbar_adx4_out3_ep>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4_ep: endpoint { + remote-endpoint = <&xbar_adx4_out4_ep>; + }; + }; + }; + }; + + dmic@2904000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dmic@2904300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic4_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic4_ep>; + }; + }; + + dmic4_port: port@1 { + reg = <1>; + + dmic4_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk1_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk1_ep>; + }; + }; + + dspk1_port: port@1 { + reg = <1>; + + dspk1_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + dspk@2905100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dspk2_cif_ep: endpoint { + remote-endpoint = <&xbar_dspk2_ep>; + }; + }; + + dspk2_port: port@1 { + reg = <1>; + + dspk2_dap_ep: endpoint { + /* Place holder for external Codec */ + }; + }; + }; + }; + + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + + amixer@290bb00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mixer_in1_ep: endpoint { + remote-endpoint = <&xbar_mixer_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + mixer_in2_ep: endpoint { + remote-endpoint = <&xbar_mixer_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + mixer_in3_ep: endpoint { + remote-endpoint = <&xbar_mixer_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + mixer_in4_ep: endpoint { + remote-endpoint = <&xbar_mixer_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + mixer_in5_ep: endpoint { + remote-endpoint = <&xbar_mixer_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + mixer_in6_ep: endpoint { + remote-endpoint = <&xbar_mixer_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + mixer_in7_ep: endpoint { + remote-endpoint = <&xbar_mixer_in7_ep>; + }; + }; + + port@7 { + reg = <0x7>; + + mixer_in8_ep: endpoint { + remote-endpoint = <&xbar_mixer_in8_ep>; + }; + }; + + port@8 { + reg = <0x8>; + + mixer_in9_ep: endpoint { + remote-endpoint = <&xbar_mixer_in9_ep>; + }; + }; + + port@9 { + reg = <0x9>; + + mixer_in10_ep: endpoint { + remote-endpoint = <&xbar_mixer_in10_ep>; + }; + }; + + mixer_out1_port: port@a { + reg = <0xa>; + + mixer_out1_ep: endpoint { + remote-endpoint = <&xbar_mixer_out1_ep>; + }; + }; + + mixer_out2_port: port@b { + reg = <0xb>; + + mixer_out2_ep: endpoint { + remote-endpoint = <&xbar_mixer_out2_ep>; + }; + }; + + mixer_out3_port: port@c { + reg = <0xc>; + + mixer_out3_ep: endpoint { + remote-endpoint = <&xbar_mixer_out3_ep>; + }; + }; + + mixer_out4_port: port@d { + reg = <0xd>; + + mixer_out4_ep: endpoint { + remote-endpoint = <&xbar_mixer_out4_ep>; + }; + }; + + mixer_out5_port: port@e { + reg = <0xe>; + + mixer_out5_ep: endpoint { + remote-endpoint = <&xbar_mixer_out5_ep>; + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0_ep: endpoint { + remote-endpoint = <&xbar_admaif0_ep>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1_ep: endpoint { + remote-endpoint = <&xbar_admaif1_ep>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2_ep: endpoint { + remote-endpoint = <&xbar_admaif2_ep>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3_ep: endpoint { + remote-endpoint = <&xbar_admaif3_ep>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4_ep: endpoint { + remote-endpoint = <&xbar_admaif4_ep>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5_ep: endpoint { + remote-endpoint = <&xbar_admaif5_ep>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6_ep: endpoint { + remote-endpoint = <&xbar_admaif6_ep>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7_ep: endpoint { + remote-endpoint = <&xbar_admaif7_ep>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8_ep: endpoint { + remote-endpoint = <&xbar_admaif8_ep>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9_ep: endpoint { + remote-endpoint = <&xbar_admaif9_ep>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10_ep: endpoint { + remote-endpoint = <&xbar_admaif10_ep>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11_ep: endpoint { + remote-endpoint = <&xbar_admaif11_ep>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12_ep: endpoint { + remote-endpoint = <&xbar_admaif12_ep>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13_ep: endpoint { + remote-endpoint = <&xbar_admaif13_ep>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14_ep: endpoint { + remote-endpoint = <&xbar_admaif14_ep>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15_ep: endpoint { + remote-endpoint = <&xbar_admaif15_ep>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16_ep: endpoint { + remote-endpoint = <&xbar_admaif16_ep>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17_ep: endpoint { + remote-endpoint = <&xbar_admaif17_ep>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18_ep: endpoint { + remote-endpoint = <&xbar_admaif18_ep>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19_ep: endpoint { + remote-endpoint = <&xbar_admaif19_ep>; + }; + }; + }; + }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; ports { #address-cells = <1>; @@ -895,1168 +2045,15 @@ }; }; }; + }; - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0_ep: endpoint { - remote-endpoint = <&xbar_admaif0_ep>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1_ep: endpoint { - remote-endpoint = <&xbar_admaif1_ep>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2_ep: endpoint { - remote-endpoint = <&xbar_admaif2_ep>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3_ep: endpoint { - remote-endpoint = <&xbar_admaif3_ep>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4_ep: endpoint { - remote-endpoint = <&xbar_admaif4_ep>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5_ep: endpoint { - remote-endpoint = <&xbar_admaif5_ep>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6_ep: endpoint { - remote-endpoint = <&xbar_admaif6_ep>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7_ep: endpoint { - remote-endpoint = <&xbar_admaif7_ep>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8_ep: endpoint { - remote-endpoint = <&xbar_admaif8_ep>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9_ep: endpoint { - remote-endpoint = <&xbar_admaif9_ep>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10_ep: endpoint { - remote-endpoint = <&xbar_admaif10_ep>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11_ep: endpoint { - remote-endpoint = <&xbar_admaif11_ep>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12_ep: endpoint { - remote-endpoint = <&xbar_admaif12_ep>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13_ep: endpoint { - remote-endpoint = <&xbar_admaif13_ep>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14_ep: endpoint { - remote-endpoint = <&xbar_admaif14_ep>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15_ep: endpoint { - remote-endpoint = <&xbar_admaif15_ep>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16_ep: endpoint { - remote-endpoint = <&xbar_admaif16_ep>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17_ep: endpoint { - remote-endpoint = <&xbar_admaif17_ep>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18_ep: endpoint { - remote-endpoint = <&xbar_admaif18_ep>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19_ep: endpoint { - remote-endpoint = <&xbar_admaif19_ep>; - }; - }; - }; - }; - - i2s@2901200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s3_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s3_ep>; - }; - }; - - i2s3_port: port@1 { - reg = <1>; - - i2s3_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - i2s@2901400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s5_cif_ep: endpoint { - remote-endpoint = <&xbar_i2s5_ep>; - }; - }; - - i2s5_port: port@1 { - reg = <1>; - - i2s5_dap_ep: endpoint { - dai-format = "i2s"; - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dmic@2904300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic4_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic4_ep>; - }; - }; - - dmic4_port: port@1 { - reg = <1>; - - dmic4_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dspk@2905000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dspk1_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk1_ep>; - }; - }; - - dspk1_port: port@1 { - reg = <1>; - - dspk1_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - dspk@2905100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dspk2_cif_ep: endpoint { - remote-endpoint = <&xbar_dspk2_ep>; - }; - }; - - dspk2_port: port@1 { - reg = <1>; - - dspk2_dap_ep: endpoint { - /* Place holder for external Codec */ - }; - }; - }; - }; - - sfc@2902000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc1_in_ep>; - convert-rate = <44100>; - }; - }; - - sfc1_out_port: port@1 { - reg = <1>; - - sfc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc1_out_ep>; - convert-rate = <48000>; - }; - }; - }; - }; - - sfc@2902200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc2_in_ep>; - }; - }; - - sfc2_out_port: port@1 { - reg = <1>; - - sfc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc2_out_ep>; - }; - }; - }; - }; - - sfc@2902400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc3_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc3_in_ep>; - }; - }; - - sfc3_out_port: port@1 { - reg = <1>; - - sfc3_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc3_out_ep>; - }; - }; - }; - }; - - sfc@2902600 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc4_cif_in_ep: endpoint { - remote-endpoint = <&xbar_sfc4_in_ep>; - }; - }; - - sfc4_out_port: port@1 { - reg = <1>; - - sfc4_cif_out_ep: endpoint { - remote-endpoint = <&xbar_sfc4_out_ep>; - }; - }; - }; - }; - - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - - amx@2903000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx1_in1_ep: endpoint { - remote-endpoint = <&xbar_amx1_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx1_in2_ep: endpoint { - remote-endpoint = <&xbar_amx1_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx1_in3_ep: endpoint { - remote-endpoint = <&xbar_amx1_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx1_in4_ep: endpoint { - remote-endpoint = <&xbar_amx1_in4_ep>; - }; - }; - - amx1_out_port: port@4 { - reg = <4>; - - amx1_out_ep: endpoint { - remote-endpoint = <&xbar_amx1_out_ep>; - }; - }; - }; - }; - - amx@2903100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx2_in1_ep: endpoint { - remote-endpoint = <&xbar_amx2_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx2_in2_ep: endpoint { - remote-endpoint = <&xbar_amx2_in2_ep>; - }; - }; - - amx2_in3_port: port@2 { - reg = <2>; - - amx2_in3_ep: endpoint { - remote-endpoint = <&xbar_amx2_in3_ep>; - }; - }; - - amx2_in4_port: port@3 { - reg = <3>; - - amx2_in4_ep: endpoint { - remote-endpoint = <&xbar_amx2_in4_ep>; - }; - }; - - amx2_out_port: port@4 { - reg = <4>; - - amx2_out_ep: endpoint { - remote-endpoint = <&xbar_amx2_out_ep>; - }; - }; - }; - }; - - amx@2903200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx3_in1_ep: endpoint { - remote-endpoint = <&xbar_amx3_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx3_in2_ep: endpoint { - remote-endpoint = <&xbar_amx3_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx3_in3_ep: endpoint { - remote-endpoint = <&xbar_amx3_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx3_in4_ep: endpoint { - remote-endpoint = <&xbar_amx3_in4_ep>; - }; - }; - - amx3_out_port: port@4 { - reg = <4>; - - amx3_out_ep: endpoint { - remote-endpoint = <&xbar_amx3_out_ep>; - }; - }; - }; - }; - - amx@2903300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx4_in1_ep: endpoint { - remote-endpoint = <&xbar_amx4_in1_ep>; - }; - }; - - port@1 { - reg = <1>; - - amx4_in2_ep: endpoint { - remote-endpoint = <&xbar_amx4_in2_ep>; - }; - }; - - port@2 { - reg = <2>; - - amx4_in3_ep: endpoint { - remote-endpoint = <&xbar_amx4_in3_ep>; - }; - }; - - port@3 { - reg = <3>; - - amx4_in4_ep: endpoint { - remote-endpoint = <&xbar_amx4_in4_ep>; - }; - }; - - amx4_out_port: port@4 { - reg = <4>; - - amx4_out_ep: endpoint { - remote-endpoint = <&xbar_amx4_out_ep>; - }; - }; - }; - }; - - adx@2903800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx1_in_ep: endpoint { - remote-endpoint = <&xbar_adx1_in_ep>; - }; - }; - - adx1_out1_port: port@1 { - reg = <1>; - - adx1_out1_ep: endpoint { - remote-endpoint = <&xbar_adx1_out1_ep>; - }; - }; - - adx1_out2_port: port@2 { - reg = <2>; - - adx1_out2_ep: endpoint { - remote-endpoint = <&xbar_adx1_out2_ep>; - }; - }; - - adx1_out3_port: port@3 { - reg = <3>; - - adx1_out3_ep: endpoint { - remote-endpoint = <&xbar_adx1_out3_ep>; - }; - }; - - adx1_out4_port: port@4 { - reg = <4>; - - adx1_out4_ep: endpoint { - remote-endpoint = <&xbar_adx1_out4_ep>; - }; - }; - }; - }; - - adx@2903900 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx2_in_ep: endpoint { - remote-endpoint = <&xbar_adx2_in_ep>; - }; - }; - - adx2_out1_port: port@1 { - reg = <1>; - - adx2_out1_ep: endpoint { - remote-endpoint = <&xbar_adx2_out1_ep>; - }; - }; - - adx2_out2_port: port@2 { - reg = <2>; - - adx2_out2_ep: endpoint { - remote-endpoint = <&xbar_adx2_out2_ep>; - }; - }; - - adx2_out3_port: port@3 { - reg = <3>; - - adx2_out3_ep: endpoint { - remote-endpoint = <&xbar_adx2_out3_ep>; - }; - }; - - adx2_out4_port: port@4 { - reg = <4>; - - adx2_out4_ep: endpoint { - remote-endpoint = <&xbar_adx2_out4_ep>; - }; - }; - }; - }; - - adx@2903a00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx3_in_ep: endpoint { - remote-endpoint = <&xbar_adx3_in_ep>; - }; - }; - - adx3_out1_port: port@1 { - reg = <1>; - - adx3_out1_ep: endpoint { - remote-endpoint = <&xbar_adx3_out1_ep>; - }; - }; - - adx3_out2_port: port@2 { - reg = <2>; - - adx3_out2_ep: endpoint { - remote-endpoint = <&xbar_adx3_out2_ep>; - }; - }; - - adx3_out3_port: port@3 { - reg = <3>; - - adx3_out3_ep: endpoint { - remote-endpoint = <&xbar_adx3_out3_ep>; - }; - }; - - adx3_out4_port: port@4 { - reg = <4>; - - adx3_out4_ep: endpoint { - remote-endpoint = <&xbar_adx3_out4_ep>; - }; - }; - }; - }; - - adx@2903b00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx4_in_ep: endpoint { - remote-endpoint = <&xbar_adx4_in_ep>; - }; - }; - - adx4_out1_port: port@1 { - reg = <1>; - - adx4_out1_ep: endpoint { - remote-endpoint = <&xbar_adx4_out1_ep>; - }; - }; - - adx4_out2_port: port@2 { - reg = <2>; - - adx4_out2_ep: endpoint { - remote-endpoint = <&xbar_adx4_out2_ep>; - }; - }; - - adx4_out3_port: port@3 { - reg = <3>; - - adx4_out3_ep: endpoint { - remote-endpoint = <&xbar_adx4_out3_ep>; - }; - }; - - adx4_out4_port: port@4 { - reg = <4>; - - adx4_out4_ep: endpoint { - remote-endpoint = <&xbar_adx4_out4_ep>; - }; - }; - }; - }; - - processing-engine@2908000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; - }; - - ope1_out_port: port@1 { - reg = <0x1>; - - ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; - }; - }; - }; - - amixer@290bb00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - mixer_in1_ep: endpoint { - remote-endpoint = <&xbar_mixer_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - mixer_in2_ep: endpoint { - remote-endpoint = <&xbar_mixer_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - mixer_in3_ep: endpoint { - remote-endpoint = <&xbar_mixer_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - mixer_in4_ep: endpoint { - remote-endpoint = <&xbar_mixer_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - mixer_in5_ep: endpoint { - remote-endpoint = <&xbar_mixer_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - mixer_in6_ep: endpoint { - remote-endpoint = <&xbar_mixer_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - mixer_in7_ep: endpoint { - remote-endpoint = <&xbar_mixer_in7_ep>; - }; - }; - - port@7 { - reg = <0x7>; - - mixer_in8_ep: endpoint { - remote-endpoint = <&xbar_mixer_in8_ep>; - }; - }; - - port@8 { - reg = <0x8>; - - mixer_in9_ep: endpoint { - remote-endpoint = <&xbar_mixer_in9_ep>; - }; - }; - - port@9 { - reg = <0x9>; - - mixer_in10_ep: endpoint { - remote-endpoint = <&xbar_mixer_in10_ep>; - }; - }; - - mixer_out1_port: port@a { - reg = <0xa>; - - mixer_out1_ep: endpoint { - remote-endpoint = <&xbar_mixer_out1_ep>; - }; - }; - - mixer_out2_port: port@b { - reg = <0xb>; - - mixer_out2_ep: endpoint { - remote-endpoint = <&xbar_mixer_out2_ep>; - }; - }; - - mixer_out3_port: port@c { - reg = <0xc>; - - mixer_out3_ep: endpoint { - remote-endpoint = <&xbar_mixer_out3_ep>; - }; - }; - - mixer_out4_port: port@d { - reg = <0xd>; - - mixer_out4_ep: endpoint { - remote-endpoint = <&xbar_mixer_out4_ep>; - }; - }; - - mixer_out5_port: port@e { - reg = <0xe>; - - mixer_out5_ep: endpoint { - remote-endpoint = <&xbar_mixer_out5_ep>; - }; - }; - }; - }; - - asrc@2910000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; - }; - - asrc_out1_port: port@7 { - reg = <0x7>; - - asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; - }; - - asrc_out2_port: port@8 { - reg = <0x8>; - - asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; - }; - - asrc_out3_port: port@9 { - reg = <0x9>; - - asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; - }; - - asrc_out4_port: port@a { - reg = <0xa>; - - asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; - }; - - asrc_out5_port: port@b { - reg = <0xb>; - - asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; - }; - - asrc_out6_port: port@c { - reg = <0xc>; - - asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; - }; - }; - }; + dma-controller@2930000 { + status = "okay"; }; - }; - ddc: i2c@3190000 { - status = "okay"; + interrupt-controller@2a40000 { + status = "okay"; + }; }; i2c@3160000 { @@ -2073,6 +2070,26 @@ }; }; + ddc: i2c@3190000 { + status = "okay"; + }; + + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + + pwm@32d0000 { + status = "okay"; + }; + hda@3510000 { nvidia,model = "NVIDIA Jetson Xavier NX HDA"; status = "okay"; @@ -2141,15 +2158,6 @@ }; }; - usb@3610000 { - status = "okay"; - - phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, - <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, - <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; - phy-names = "usb2-1", "usb2-2", "usb3-2"; - }; - usb@3550000 { status = "okay"; @@ -2157,20 +2165,13 @@ phy-names = "usb2-0"; }; - spi@3270000 { + usb@3610000 { status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <102000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - }; - - pwm@32d0000 { - status = "okay"; + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-1", "usb2-2", "usb3-2"; }; host1x@13e00000 { @@ -2209,54 +2210,46 @@ GPIO_ACTIVE_LOW>; }; }; - }; - - pcie@14160000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8ao>; - phys = <&p2u_hsio_11>; - phy-names = "p2u-0"; - }; + pcie@14160000 { + status = "okay"; - pcie@141a0000 { - status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + phys = <&p2u_hsio_11>; + phy-names = "p2u-0"; + }; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; + pcie@141a0000 { + status = "okay"; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - pcie-ep@141a0000 { - status = "disabled"; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; - vddio-pex-ctl-supply = <&vdd_1v8ao>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; + pcie-ep@141a0000 { + status = "disabled"; - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) - GPIO_ACTIVE_HIGH>; + vddio-pex-ctl-supply = <&vdd_1v8ao>; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) + GPIO_ACTIVE_HIGH>; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm6 0 45334>; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; }; gpio-keys { @@ -2283,6 +2276,14 @@ }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm6 0 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; regulator-name = "VDD_5V_SYS"; diff --git a/dts/src/arm64/nvidia/tegra194-p3668.dtsi b/dts/src/arm64/nvidia/tegra194-p3668.dtsi index 0751edddf7..58f190b0f8 100644 --- a/dts/src/arm64/nvidia/tegra194-p3668.dtsi +++ b/dts/src/arm64/nvidia/tegra194-p3668.dtsi @@ -121,6 +121,24 @@ pinctrl-names = "default"; pinctrl-0 = <&max20024_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,shutdown-fps-time-period-us = <640>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + max20024_default: pinmux { gpio0 { pins = "gpio0"; @@ -164,24 +182,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,shutdown-fps-time-period-us = <640>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,shutdown-fps-time-period-us = <640>; - }; - }; - regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; diff --git a/dts/src/arm64/nvidia/tegra194.dtsi b/dts/src/arm64/nvidia/tegra194.dtsi index 4afcbd60e1..133dbe5b42 100644 --- a/dts/src/arm64/nvidia/tegra194.dtsi +++ b/dts/src/arm64/nvidia/tegra194.dtsi @@ -19,21 +19,22 @@ /* control backbone */ bus@0 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; apbmisc: misc@100000 { compatible = "nvidia,tegra194-misc"; - reg = <0x00100000 0xf000>, - <0x0010f000 0x1000>; + reg = <0x0 0x00100000 0x0 0xf000>, + <0x0 0x0010f000 0x0 0x1000>; }; gpio: gpio@2200000 { compatible = "nvidia,tegra194-gpio"; reg-names = "security", "gpio"; - reg = <0x2200000 0x10000>, - <0x2210000 0x10000>; + reg = <0x0 0x2200000 0x0 0x10000>, + <0x0 0x2210000 0x0 0x10000>; interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, @@ -91,7 +92,7 @@ cbb-noc@2300000 { compatible = "nvidia,tegra194-cbb-noc"; - reg = <0x02300000 0x1000>; + reg = <0x0 0x02300000 0x0 0x1000>; interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; @@ -101,20 +102,48 @@ axi2apb: axi2apb@2390000 { compatible = "nvidia,tegra194-axi2apb"; - reg = <0x2390000 0x1000>, - <0x23a0000 0x1000>, - <0x23b0000 0x1000>, - <0x23c0000 0x1000>, - <0x23d0000 0x1000>, - <0x23e0000 0x1000>; + reg = <0x0 0x2390000 0x0 0x1000>, + <0x0 0x23a0000 0x0 0x1000>, + <0x0 0x23b0000 0x0 0x1000>, + <0x0 0x23c0000 0x0 0x1000>, + <0x0 0x23d0000 0x0 0x1000>, + <0x0 0x23e0000 0x0 0x1000>; + status = "okay"; + }; + + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra194-pinmux"; + reg = <0x0 0x2430000 0x0 0x17000>; status = "okay"; + + pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { + clkreq { + nvidia,pins = "pex_l5_clkreq_n_pgg0"; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + }; + + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { + pex_rst { + nvidia,pins = "pex_l5_rst_n_pgg1"; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + }; }; ethernet@2490000 { compatible = "nvidia,tegra194-eqos", "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; - reg = <0x02490000 0x10000>; + reg = <0x0 0x02490000 0x0 0x10000>; interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, <&bpmp TEGRA194_CLK_EQOS_AXI>, @@ -140,7 +169,7 @@ gpcdma: dma-controller@2600000 { compatible = "nvidia,tegra194-gpcdma", "nvidia,tegra186-gpcdma"; - reg = <0x2600000 0x210000>; + reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA194_RESET_GPCDMA>; reset-names = "gpcdma"; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, @@ -189,137 +218,30 @@ <&bpmp TEGRA194_CLK_APB2APE>; clock-names = "ape", "apb2ape"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900000 0x02900000 0x200000>; status = "disabled"; - adma: dma-controller@2930000 { - compatible = "nvidia,tegra194-adma", - "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; - interrupt-parent = <&agic>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&bpmp TEGRA194_CLK_AHUB>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@2a40000 { - compatible = "nvidia,tegra194-agic", - "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; - interrupts = <GIC_SPI 145 - (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&bpmp TEGRA194_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra194-ahub", "nvidia,tegra186-ahub"; - reg = <0x02900800 0x800>; + reg = <0x0 0x02900800 0x0 0x800>; clocks = <&bpmp TEGRA194_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900800 0x02900800 0x11800>; status = "disabled"; - tegra_admaif: admaif@290f000 { - compatible = "nvidia,tegra194-admaif", - "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; - dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>; - dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20"; - status = "disabled"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_APE>; - }; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901000 0x100>; + reg = <0x0 0x2901000 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S1>, <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -333,7 +255,7 @@ tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901100 0x100>; + reg = <0x0 0x2901100 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S2>, <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -347,7 +269,7 @@ tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901200 0x100>; + reg = <0x0 0x2901200 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S3>, <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -361,7 +283,7 @@ tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901300 0x100>; + reg = <0x0 0x2901300 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S4>, <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -375,7 +297,7 @@ tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901400 0x100>; + reg = <0x0 0x2901400 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S5>, <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -389,7 +311,7 @@ tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901500 0x100>; + reg = <0x0 0x2901500 0x0 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S6>, <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -400,88 +322,10 @@ status = "disabled"; }; - tegra_dmic1: dmic@2904000 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@2904100 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@2904200 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - - tegra_dmic4: dmic@2904300 { - compatible = "nvidia,tegra194-dmic", - "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; - clocks = <&bpmp TEGRA194_CLK_DMIC4>; - clock-names = "dmic"; - assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC4"; - status = "disabled"; - }; - - tegra_dspk1: dspk@2905000 { - compatible = "nvidia,tegra194-dspk", - "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; - clocks = <&bpmp TEGRA194_CLK_DSPK1>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK1"; - status = "disabled"; - }; - - tegra_dspk2: dspk@2905100 { - compatible = "nvidia,tegra194-dspk", - "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; - clocks = <&bpmp TEGRA194_CLK_DSPK2>; - clock-names = "dspk"; - assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; - assigned-clock-rates = <12288000>; - sound-name-prefix = "DSPK2"; - status = "disabled"; - }; - tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902000 0x200>; + reg = <0x0 0x2902000 0x0 0x200>; sound-name-prefix = "SFC1"; status = "disabled"; }; @@ -489,7 +333,7 @@ tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902200 0x200>; + reg = <0x0 0x2902200 0x0 0x200>; sound-name-prefix = "SFC2"; status = "disabled"; }; @@ -497,7 +341,7 @@ tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902400 0x200>; + reg = <0x0 0x2902400 0x0 0x200>; sound-name-prefix = "SFC3"; status = "disabled"; }; @@ -505,51 +349,35 @@ tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902600 0x200>; + reg = <0x0 0x2902600 0x0 0x200>; sound-name-prefix = "SFC4"; status = "disabled"; }; - tegra_mvc1: mvc@290a000 { - compatible = "nvidia,tegra194-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a000 0x200>; - sound-name-prefix = "MVC1"; - status = "disabled"; - }; - - tegra_mvc2: mvc@290a200 { - compatible = "nvidia,tegra194-mvc", - "nvidia,tegra210-mvc"; - reg = <0x290a200 0x200>; - sound-name-prefix = "MVC2"; - status = "disabled"; - }; - tegra_amx1: amx@2903000 { compatible = "nvidia,tegra194-amx"; - reg = <0x2903000 0x100>; + reg = <0x0 0x2903000 0x0 0x100>; sound-name-prefix = "AMX1"; status = "disabled"; }; tegra_amx2: amx@2903100 { compatible = "nvidia,tegra194-amx"; - reg = <0x2903100 0x100>; + reg = <0x0 0x2903100 0x0 0x100>; sound-name-prefix = "AMX2"; status = "disabled"; }; tegra_amx3: amx@2903200 { compatible = "nvidia,tegra194-amx"; - reg = <0x2903200 0x100>; + reg = <0x0 0x2903200 0x0 0x100>; sound-name-prefix = "AMX3"; status = "disabled"; }; tegra_amx4: amx@2903300 { compatible = "nvidia,tegra194-amx"; - reg = <0x2903300 0x100>; + reg = <0x0 0x2903300 0x0 0x100>; sound-name-prefix = "AMX4"; status = "disabled"; }; @@ -557,7 +385,7 @@ tegra_adx1: adx@2903800 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x2903800 0x100>; + reg = <0x0 0x2903800 0x0 0x100>; sound-name-prefix = "ADX1"; status = "disabled"; }; @@ -565,7 +393,7 @@ tegra_adx2: adx@2903900 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x2903900 0x100>; + reg = <0x0 0x2903900 0x0 0x100>; sound-name-prefix = "ADX2"; status = "disabled"; }; @@ -573,7 +401,7 @@ tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x2903a00 0x100>; + reg = <0x0 0x2903a00 0x0 0x100>; sound-name-prefix = "ADX3"; status = "disabled"; }; @@ -581,100 +409,276 @@ tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x2903b00 0x100>; + reg = <0x0 0x2903b00 0x0 0x100>; sound-name-prefix = "ADX4"; status = "disabled"; }; + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x2904000 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x2904100 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x2904200 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x0 0x2904300 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra194-dspk", + "nvidia,tegra186-dspk"; + reg = <0x0 0x2905000 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra194-dspk", + "nvidia,tegra186-dspk"; + reg = <0x0 0x2905100 0x0 0x100>; + clocks = <&bpmp TEGRA194_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra194-ope", "nvidia,tegra210-ope"; - reg = <0x2908000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x0 0x2908000 0x0 0x100>; sound-name-prefix = "OPE1"; status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + equalizer@2908100 { compatible = "nvidia,tegra194-peq", "nvidia,tegra210-peq"; - reg = <0x2908100 0x100>; + reg = <0x0 0x2908100 0x0 0x100>; }; dynamic-range-compressor@2908200 { compatible = "nvidia,tegra194-mbdrc", "nvidia,tegra210-mbdrc"; - reg = <0x2908200 0x200>; + reg = <0x0 0x2908200 0x0 0x200>; }; }; + tegra_mvc1: mvc@290a000 { + compatible = "nvidia,tegra194-mvc", + "nvidia,tegra210-mvc"; + reg = <0x0 0x290a000 0x0 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@290a200 { + compatible = "nvidia,tegra194-mvc", + "nvidia,tegra210-mvc"; + reg = <0x0 0x290a200 0x0 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra194-amixer", "nvidia,tegra210-amixer"; - reg = <0x290bb00 0x800>; + reg = <0x0 0x290bb00 0x0 0x800>; sound-name-prefix = "MIXER1"; status = "disabled"; }; + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra194-admaif", + "nvidia,tegra186-admaif"; + reg = <0x0 0x0290f000 0x0 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_APE>; + }; + tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra194-asrc", "nvidia,tegra186-asrc"; - reg = <0x2910000 0x2000>; + reg = <0x0 0x2910000 0x0 0x2000>; sound-name-prefix = "ASRC1"; status = "disabled"; }; }; - }; - pinmux: pinmux@2430000 { - compatible = "nvidia,tegra194-pinmux"; - reg = <0x2430000 0x17000>; - status = "okay"; - - pex_rst_c5_out_state: pinmux-pex-rst-c5-out { - pex_rst { - nvidia,pins = "pex_l5_rst_n_pgg1"; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - nvidia,io-hv = <TEGRA_PIN_ENABLE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - }; + adma: dma-controller@2930000 { + compatible = "nvidia,tegra194-adma", + "nvidia,tegra186-adma"; + reg = <0x0 0x02930000 0x0 0x20000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&bpmp TEGRA194_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; }; - clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir { - clkreq { - nvidia,pins = "pex_l5_clkreq_n_pgg0"; - nvidia,schmitt = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - nvidia,io-hv = <TEGRA_PIN_ENABLE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - }; + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra194-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x02a41000 0x0 0x1000>, + <0x0 0x02a42000 0x0 0x2000>; + interrupts = <GIC_SPI 145 + (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&bpmp TEGRA194_CLK_APE>; + clock-names = "clk"; + status = "disabled"; }; }; mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x10000>, /* MC-SID */ - <0x02c10000 0x10000>, /* MC Broadcast*/ - <0x02c20000 0x10000>, /* MC0 */ - <0x02c30000 0x10000>, /* MC1 */ - <0x02c40000 0x10000>, /* MC2 */ - <0x02c50000 0x10000>, /* MC3 */ - <0x02b80000 0x10000>, /* MC4 */ - <0x02b90000 0x10000>, /* MC5 */ - <0x02ba0000 0x10000>, /* MC6 */ - <0x02bb0000 0x10000>, /* MC7 */ - <0x01700000 0x10000>, /* MC8 */ - <0x01710000 0x10000>, /* MC9 */ - <0x01720000 0x10000>, /* MC10 */ - <0x01730000 0x10000>, /* MC11 */ - <0x01740000 0x10000>, /* MC12 */ - <0x01750000 0x10000>, /* MC13 */ - <0x01760000 0x10000>, /* MC14 */ - <0x01770000 0x10000>; /* MC15 */ + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ + <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ + <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ + <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ + <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ + <0x0 0x01700000 0x0 0x10000>, /* MC8 */ + <0x0 0x01710000 0x0 0x10000>, /* MC9 */ + <0x0 0x01720000 0x0 0x10000>, /* MC10 */ + <0x0 0x01730000 0x0 0x10000>, /* MC11 */ + <0x0 0x01740000 0x0 0x10000>, /* MC12 */ + <0x0 0x01750000 0x0 0x10000>, /* MC13 */ + <0x0 0x01760000 0x0 0x10000>, /* MC14 */ + <0x0 0x01770000 0x0 0x10000>; /* MC15 */ reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; @@ -684,10 +688,9 @@ #address-cells = <2>; #size-cells = <2>; - - ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, - <0x02b80000 0x0 0x02b80000 0x0 0x040000>, - <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; /* * Bit 39 of addresses passing through the memory @@ -704,7 +707,7 @@ * * Limit the DMA range for memory clients to [38:0]. */ - dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; emc: external-memory-controller@2c60000 { compatible = "nvidia,tegra194-emc"; @@ -722,7 +725,7 @@ timer@3010000 { compatible = "nvidia,tegra186-timer"; - reg = <0x03010000 0x000e0000>; + reg = <0x0 0x03010000 0x0 0x000e0000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, @@ -738,7 +741,7 @@ uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03100000 0x40>; + reg = <0x0 0x03100000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTA>; @@ -750,7 +753,7 @@ uartb: serial@3110000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03110000 0x40>; + reg = <0x0 0x03110000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTB>; @@ -762,7 +765,7 @@ uartd: serial@3130000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03130000 0x40>; + reg = <0x0 0x03130000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTD>; @@ -774,7 +777,7 @@ uarte: serial@3140000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03140000 0x40>; + reg = <0x0 0x03140000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTE>; @@ -786,7 +789,7 @@ uartf: serial@3150000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03150000 0x40>; + reg = <0x0 0x03150000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTF>; @@ -798,7 +801,7 @@ gen1_i2c: i2c@3160000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x03160000 0x10000>; + reg = <0x0 0x03160000 0x0 0x10000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -806,8 +809,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C1>; reset-names = "i2c"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; status = "disabled"; @@ -815,7 +816,7 @@ uarth: serial@3170000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x03170000 0x40>; + reg = <0x0 0x03170000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTH>; @@ -827,7 +828,7 @@ cam_i2c: i2c@3180000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x03180000 0x10000>; + reg = <0x0 0x03180000 0x0 0x10000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -835,8 +836,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C3>; reset-names = "i2c"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; status = "disabled"; @@ -845,7 +844,7 @@ /* shares pads with dpaux1 */ dp_aux_ch1_i2c: i2c@3190000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x03190000 0x10000>; + reg = <0x0 0x03190000 0x0 0x10000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -856,8 +855,6 @@ pinctrl-0 = <&state_dpaux1_i2c>; pinctrl-1 = <&state_dpaux1_off>; pinctrl-names = "default", "idle"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; status = "disabled"; @@ -866,7 +863,7 @@ /* shares pads with dpaux0 */ dp_aux_ch0_i2c: i2c@31b0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x031b0000 0x10000>; + reg = <0x0 0x031b0000 0x0 0x10000>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -877,8 +874,6 @@ pinctrl-0 = <&state_dpaux0_i2c>; pinctrl-1 = <&state_dpaux0_off>; pinctrl-names = "default", "idle"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; status = "disabled"; @@ -887,7 +882,7 @@ /* shares pads with dpaux2 */ dp_aux_ch2_i2c: i2c@31c0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x031c0000 0x10000>; + reg = <0x0 0x031c0000 0x0 0x10000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -898,8 +893,6 @@ pinctrl-0 = <&state_dpaux2_i2c>; pinctrl-1 = <&state_dpaux2_off>; pinctrl-names = "default", "idle"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; status = "disabled"; @@ -908,7 +901,7 @@ /* shares pads with dpaux3 */ dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x031e0000 0x10000>; + reg = <0x0 0x031e0000 0x0 0x10000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -919,8 +912,6 @@ pinctrl-0 = <&state_dpaux3_i2c>; pinctrl-1 = <&state_dpaux3_off>; pinctrl-names = "default", "idle"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; status = "disabled"; @@ -928,7 +919,7 @@ spi@3270000 { compatible = "nvidia,tegra194-qspi"; - reg = <0x3270000 0x1000>; + reg = <0x0 0x3270000 0x0 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -939,23 +930,10 @@ status = "disabled"; }; - spi@3300000 { - compatible = "nvidia,tegra194-qspi"; - reg = <0x3300000 0x1000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&bpmp TEGRA194_CLK_QSPI1>, - <&bpmp TEGRA194_CLK_QSPI1_PM>; - clock-names = "qspi", "qspi_out"; - resets = <&bpmp TEGRA194_RESET_QSPI1>; - status = "disabled"; - }; - pwm1: pwm@3280000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x3280000 0x10000>; + reg = <0x0 0x3280000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM1>; resets = <&bpmp TEGRA194_RESET_PWM1>; reset-names = "pwm"; @@ -966,7 +944,7 @@ pwm2: pwm@3290000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x3290000 0x10000>; + reg = <0x0 0x3290000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM2>; resets = <&bpmp TEGRA194_RESET_PWM2>; reset-names = "pwm"; @@ -977,7 +955,7 @@ pwm3: pwm@32a0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32a0000 0x10000>; + reg = <0x0 0x32a0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM3>; resets = <&bpmp TEGRA194_RESET_PWM3>; reset-names = "pwm"; @@ -988,7 +966,7 @@ pwm5: pwm@32c0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32c0000 0x10000>; + reg = <0x0 0x32c0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM5>; resets = <&bpmp TEGRA194_RESET_PWM5>; reset-names = "pwm"; @@ -999,7 +977,7 @@ pwm6: pwm@32d0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32d0000 0x10000>; + reg = <0x0 0x32d0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM6>; resets = <&bpmp TEGRA194_RESET_PWM6>; reset-names = "pwm"; @@ -1010,7 +988,7 @@ pwm7: pwm@32e0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32e0000 0x10000>; + reg = <0x0 0x32e0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM7>; resets = <&bpmp TEGRA194_RESET_PWM7>; reset-names = "pwm"; @@ -1021,7 +999,7 @@ pwm8: pwm@32f0000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0x32f0000 0x10000>; + reg = <0x0 0x32f0000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM8>; resets = <&bpmp TEGRA194_RESET_PWM8>; reset-names = "pwm"; @@ -1029,9 +1007,22 @@ #pwm-cells = <2>; }; + spi@3300000 { + compatible = "nvidia,tegra194-qspi"; + reg = <0x0 0x3300000 0x0 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA194_CLK_QSPI1>, + <&bpmp TEGRA194_CLK_QSPI1_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA194_RESET_QSPI1>; + status = "disabled"; + }; + sdmmc1: mmc@3400000 { compatible = "nvidia,tegra194-sdhci"; - reg = <0x03400000 0x10000>; + reg = <0x0 0x03400000 0x0 0x10000>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC1>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; @@ -1070,7 +1061,7 @@ sdmmc3: mmc@3440000 { compatible = "nvidia,tegra194-sdhci"; - reg = <0x03440000 0x10000>; + reg = <0x0 0x03440000 0x0 0x10000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC3>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; @@ -1110,7 +1101,7 @@ sdmmc4: mmc@3460000 { compatible = "nvidia,tegra194-sdhci"; - reg = <0x03460000 0x10000>; + reg = <0x0 0x03460000 0x0 0x10000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SDMMC4>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; @@ -1147,7 +1138,7 @@ hda@3510000 { compatible = "nvidia,tegra194-hda"; - reg = <0x3510000 0x10000>; + reg = <0x0 0x3510000 0x0 0x10000>; interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_HDA>, <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, @@ -1166,8 +1157,8 @@ xusb_padctl: padctl@3520000 { compatible = "nvidia,tegra194-xusb-padctl"; - reg = <0x03520000 0x1000>, - <0x03540000 0x1000>; + reg = <0x0 0x03520000 0x0 0x1000>, + <0x0 0x03540000 0x0 0x1000>; reg-names = "padctl", "ao"; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; @@ -1274,8 +1265,8 @@ usb@3550000 { compatible = "nvidia,tegra194-xudc"; - reg = <0x03550000 0x8000>, - <0x03558000 0x1000>; + reg = <0x0 0x03550000 0x0 0x8000>, + <0x0 0x03558000 0x0 0x1000>; reg-names = "base", "fpci"; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, @@ -1291,13 +1282,14 @@ <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; power-domain-names = "dev", "ss"; nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; status = "disabled"; }; usb@3610000 { compatible = "nvidia,tegra194-xusb"; - reg = <0x03610000 0x40000>, - <0x03600000 0x10000>; + reg = <0x0 0x03610000 0x0 0x40000>, + <0x0 0x03600000 0x0 0x10000>; reg-names = "hcd", "fpci"; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, @@ -1331,7 +1323,7 @@ fuse@3820000 { compatible = "nvidia,tegra194-efuse"; - reg = <0x03820000 0x10000>; + reg = <0x0 0x03820000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_FUSE>; clock-names = "fuse"; }; @@ -1340,10 +1332,10 @@ compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x03881000 0x1000>, - <0x03882000 0x2000>, - <0x03884000 0x2000>, - <0x03886000 0x2000>; + reg = <0x0 0x03881000 0x0 0x1000>, + <0x0 0x03882000 0x0 0x2000>, + <0x0 0x03884000 0x0 0x2000>, + <0x0 0x03886000 0x0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-parent = <&gic>; @@ -1351,7 +1343,7 @@ cec@3960000 { compatible = "nvidia,tegra194-cec"; - reg = <0x03960000 0x10000>; + reg = <0x0 0x03960000 0x0 0x10000>; interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_CEC>; clock-names = "cec"; @@ -1360,7 +1352,7 @@ hte_lic: hardware-timestamp@3aa0000 { compatible = "nvidia,tegra194-gte-lic"; - reg = <0x3aa0000 0x10000>; + reg = <0x0 0x3aa0000 0x0 0x10000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; nvidia,int-threshold = <1>; nvidia,slices = <11>; @@ -1370,7 +1362,7 @@ hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra194-hsp"; - reg = <0x03c00000 0xa0000>; + reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -1388,7 +1380,7 @@ p2u_hsio_0: phy@3e10000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e10000 0x10000>; + reg = <0x0 0x03e10000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1396,7 +1388,7 @@ p2u_hsio_1: phy@3e20000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e20000 0x10000>; + reg = <0x0 0x03e20000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1404,7 +1396,7 @@ p2u_hsio_2: phy@3e30000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e30000 0x10000>; + reg = <0x0 0x03e30000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1412,7 +1404,7 @@ p2u_hsio_3: phy@3e40000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e40000 0x10000>; + reg = <0x0 0x03e40000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1420,7 +1412,7 @@ p2u_hsio_4: phy@3e50000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e50000 0x10000>; + reg = <0x0 0x03e50000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1428,7 +1420,7 @@ p2u_hsio_5: phy@3e60000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e60000 0x10000>; + reg = <0x0 0x03e60000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1436,7 +1428,7 @@ p2u_hsio_6: phy@3e70000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e70000 0x10000>; + reg = <0x0 0x03e70000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1444,7 +1436,7 @@ p2u_hsio_7: phy@3e80000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e80000 0x10000>; + reg = <0x0 0x03e80000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1452,7 +1444,7 @@ p2u_hsio_8: phy@3e90000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03e90000 0x10000>; + reg = <0x0 0x03e90000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1460,7 +1452,7 @@ p2u_hsio_9: phy@3ea0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ea0000 0x10000>; + reg = <0x0 0x03ea0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1468,7 +1460,7 @@ p2u_nvhs_0: phy@3eb0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03eb0000 0x10000>; + reg = <0x0 0x03eb0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1476,7 +1468,7 @@ p2u_nvhs_1: phy@3ec0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ec0000 0x10000>; + reg = <0x0 0x03ec0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1484,7 +1476,7 @@ p2u_nvhs_2: phy@3ed0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ed0000 0x10000>; + reg = <0x0 0x03ed0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1492,7 +1484,7 @@ p2u_nvhs_3: phy@3ee0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ee0000 0x10000>; + reg = <0x0 0x03ee0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1500,7 +1492,7 @@ p2u_nvhs_4: phy@3ef0000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03ef0000 0x10000>; + reg = <0x0 0x03ef0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1508,7 +1500,7 @@ p2u_nvhs_5: phy@3f00000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f00000 0x10000>; + reg = <0x0 0x03f00000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1516,7 +1508,7 @@ p2u_nvhs_6: phy@3f10000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f10000 0x10000>; + reg = <0x0 0x03f10000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1524,7 +1516,7 @@ p2u_nvhs_7: phy@3f20000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f20000 0x10000>; + reg = <0x0 0x03f20000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1532,7 +1524,7 @@ p2u_hsio_10: phy@3f30000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f30000 0x10000>; + reg = <0x0 0x03f30000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1540,7 +1532,7 @@ p2u_hsio_11: phy@3f40000 { compatible = "nvidia,tegra194-p2u"; - reg = <0x03f40000 0x10000>; + reg = <0x0 0x03f40000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1548,7 +1540,7 @@ sce-noc@b600000 { compatible = "nvidia,tegra194-sce-noc"; - reg = <0xb600000 0x1000>; + reg = <0x0 0xb600000 0x0 0x1000>; interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; @@ -1558,7 +1550,7 @@ rce-noc@be00000 { compatible = "nvidia,tegra194-rce-noc"; - reg = <0xbe00000 0x1000>; + reg = <0x0 0xbe00000 0x0 0x1000>; interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; @@ -1568,7 +1560,7 @@ hsp_aon: hsp@c150000 { compatible = "nvidia,tegra194-hsp"; - reg = <0x0c150000 0x90000>; + reg = <0x0 0x0c150000 0x0 0x90000>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, @@ -1583,7 +1575,7 @@ hte_aon: hardware-timestamp@c1e0000 { compatible = "nvidia,tegra194-gte-aon"; - reg = <0xc1e0000 0x10000>; + reg = <0x0 0xc1e0000 0x0 0x10000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; nvidia,int-threshold = <1>; nvidia,slices = <3>; @@ -1593,7 +1585,7 @@ gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x0c240000 0x10000>; + reg = <0x0 0x0c240000 0x0 0x10000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -1601,8 +1593,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C2>; reset-names = "i2c"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 22>, <&gpcdma 22>; dma-names = "rx", "tx"; status = "disabled"; @@ -1610,7 +1600,7 @@ gen8_i2c: i2c@c250000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x0c250000 0x10000>; + reg = <0x0 0x0c250000 0x0 0x10000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -1618,8 +1608,6 @@ clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C8>; reset-names = "i2c"; - iommus = <&smmu TEGRA194_SID_GPCDMA_0>; - dma-coherent; dmas = <&gpcdma 0>, <&gpcdma 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -1627,7 +1615,7 @@ uartc: serial@c280000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x0c280000 0x40>; + reg = <0x0 0x0c280000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTC>; @@ -1639,7 +1627,7 @@ uartg: serial@c290000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; - reg = <0x0c290000 0x40>; + reg = <0x0 0x0c290000 0x0 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_UARTG>; @@ -1651,7 +1639,7 @@ rtc: rtc@c2a0000 { compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; - reg = <0x0c2a0000 0x10000>; + reg = <0x0 0x0c2a0000 0x0 0x10000>; interrupt-parent = <&pmc>; interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_CLK_32K>; @@ -1662,8 +1650,8 @@ gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra194-gpio-aon"; reg-names = "security", "gpio"; - reg = <0xc2f0000 0x1000>, - <0xc2f1000 0x1000>; + reg = <0x0 0xc2f0000 0x0 0x1000>, + <0x0 0xc2f1000 0x0 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, @@ -1672,12 +1660,12 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-range = <&pinmux_aon 0 0 30>; + gpio-ranges = <&pinmux_aon 0 0 30>; }; pinmux_aon: pinmux@c300000 { compatible = "nvidia,tegra194-pinmux-aon"; - reg = <0xc300000 0x4000>; + reg = <0x0 0xc300000 0x0 0x4000>; status = "okay"; }; @@ -1685,7 +1673,7 @@ pwm4: pwm@c340000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; - reg = <0xc340000 0x10000>; + reg = <0x0 0xc340000 0x0 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM4>; resets = <&bpmp TEGRA194_RESET_PWM4>; reset-names = "pwm"; @@ -1695,26 +1683,23 @@ pmc: pmc@c360000 { compatible = "nvidia,tegra194-pmc"; - reg = <0x0c360000 0x10000>, - <0x0c370000 0x10000>, - <0x0c380000 0x10000>, - <0x0c390000 0x10000>, - <0x0c3a0000 0x10000>; + reg = <0x0 0x0c360000 0x0 0x10000>, + <0x0 0x0c370000 0x0 0x10000>, + <0x0 0x0c380000 0x0 0x10000>, + <0x0 0x0c390000 0x0 0x10000>, + <0x0 0x0c3a0000 0x0 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch", "misc"; #interrupt-cells = <2>; interrupt-controller; - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; sdmmc1_1v8: sdmmc1-1v8 { pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; @@ -1723,11 +1708,15 @@ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; }; aon-noc@c600000 { compatible = "nvidia,tegra194-aon-noc"; - reg = <0xc600000 0x1000>; + reg = <0x0 0xc600000 0x0 0x1000>; interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; nvidia,apbmisc = <&apbmisc>; @@ -1736,7 +1725,7 @@ bpmp-noc@d600000 { compatible = "nvidia,tegra194-bpmp-noc"; - reg = <0xd600000 0x1000>; + reg = <0x0 0xd600000 0x0 0x1000>; interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; nvidia,axi2apb = <&axi2apb>; @@ -1746,7 +1735,7 @@ iommu@10000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; - reg = <0x10000000 0x800000>; + reg = <0x0 0x10000000 0x0 0x800000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, @@ -1822,8 +1811,8 @@ smmu: iommu@12000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; - reg = <0x12000000 0x800000>, - <0x11000000 0x800000>; + reg = <0x0 0x12000000 0x0 0x800000>, + <0x0 0x11000000 0x0 0x800000>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, @@ -1900,8 +1889,8 @@ host1x@13e00000 { compatible = "nvidia,tegra194-host1x"; - reg = <0x13e00000 0x10000>, - <0x13e10000 0x10000>; + reg = <0x0 0x13e00000 0x0 0x10000>, + <0x0 0x13e10000 0x0 0x10000>; reg-names = "hypervisor", "vm"; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; @@ -1911,13 +1900,14 @@ resets = <&bpmp TEGRA194_RESET_HOST1X>; reset-names = "host1x"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; - ranges = <0x14800000 0x14800000 0x02800000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnect-names = "dma-mem"; iommus = <&smmu TEGRA194_SID_HOST1X>; + dma-coherent; /* Context isolation domains */ iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, @@ -1931,7 +1921,7 @@ nvdec@15140000 { compatible = "nvidia,tegra194-nvdec"; - reg = <0x15140000 0x00040000>; + reg = <0x0 0x15140000 0x0 0x00040000>; clocks = <&bpmp TEGRA194_CLK_NVDEC1>; clock-names = "nvdec"; resets = <&bpmp TEGRA194_RESET_NVDEC1>; @@ -1950,7 +1940,7 @@ display-hub@15200000 { compatible = "nvidia,tegra194-display"; - reg = <0x15200000 0x00040000>; + reg = <0x0 0x15200000 0x0 0x00040000>; resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, @@ -1967,14 +1957,13 @@ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x15200000 0x15200000 0x40000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; display@15200000 { compatible = "nvidia,tegra194-dc"; - reg = <0x15200000 0x10000>; + reg = <0x0 0x15200000 0x0 0x10000>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; clock-names = "dc"; @@ -1992,7 +1981,7 @@ display@15210000 { compatible = "nvidia,tegra194-dc"; - reg = <0x15210000 0x10000>; + reg = <0x0 0x15210000 0x0 0x10000>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; clock-names = "dc"; @@ -2010,7 +1999,7 @@ display@15220000 { compatible = "nvidia,tegra194-dc"; - reg = <0x15220000 0x10000>; + reg = <0x0 0x15220000 0x0 0x10000>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; clock-names = "dc"; @@ -2028,7 +2017,7 @@ display@15230000 { compatible = "nvidia,tegra194-dc"; - reg = <0x15230000 0x10000>; + reg = <0x0 0x15230000 0x0 0x10000>; interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; clock-names = "dc"; @@ -2047,7 +2036,7 @@ vic@15340000 { compatible = "nvidia,tegra194-vic"; - reg = <0x15340000 0x00040000>; + reg = <0x0 0x15340000 0x0 0x00040000>; interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_VIC>; clock-names = "vic"; @@ -2064,7 +2053,7 @@ nvjpg@15380000 { compatible = "nvidia,tegra194-nvjpg"; - reg = <0x15380000 0x40000>; + reg = <0x0 0x15380000 0x0 0x40000>; clocks = <&bpmp TEGRA194_CLK_NVJPG>; clock-names = "nvjpg"; resets = <&bpmp TEGRA194_RESET_NVJPG>; @@ -2080,7 +2069,7 @@ nvdec@15480000 { compatible = "nvidia,tegra194-nvdec"; - reg = <0x15480000 0x00040000>; + reg = <0x0 0x15480000 0x0 0x00040000>; clocks = <&bpmp TEGRA194_CLK_NVDEC>; clock-names = "nvdec"; resets = <&bpmp TEGRA194_RESET_NVDEC>; @@ -2099,7 +2088,7 @@ nvenc@154c0000 { compatible = "nvidia,tegra194-nvenc"; - reg = <0x154c0000 0x40000>; + reg = <0x0 0x154c0000 0x0 0x40000>; clocks = <&bpmp TEGRA194_CLK_NVENC>; clock-names = "nvenc"; resets = <&bpmp TEGRA194_RESET_NVENC>; @@ -2118,7 +2107,7 @@ dpaux0: dpaux@155c0000 { compatible = "nvidia,tegra194-dpaux"; - reg = <0x155c0000 0x10000>; + reg = <0x0 0x155c0000 0x0 0x10000>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_DPAUX>, <&bpmp TEGRA194_CLK_PLLDP>; @@ -2152,7 +2141,7 @@ dpaux1: dpaux@155d0000 { compatible = "nvidia,tegra194-dpaux"; - reg = <0x155d0000 0x10000>; + reg = <0x0 0x155d0000 0x0 0x10000>; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_DPAUX1>, <&bpmp TEGRA194_CLK_PLLDP>; @@ -2186,7 +2175,7 @@ dpaux2: dpaux@155e0000 { compatible = "nvidia,tegra194-dpaux"; - reg = <0x155e0000 0x10000>; + reg = <0x0 0x155e0000 0x0 0x10000>; interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_DPAUX2>, <&bpmp TEGRA194_CLK_PLLDP>; @@ -2220,7 +2209,7 @@ dpaux3: dpaux@155f0000 { compatible = "nvidia,tegra194-dpaux"; - reg = <0x155f0000 0x10000>; + reg = <0x0 0x155f0000 0x0 0x10000>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_DPAUX3>, <&bpmp TEGRA194_CLK_PLLDP>; @@ -2254,7 +2243,7 @@ nvenc@15a80000 { compatible = "nvidia,tegra194-nvenc"; - reg = <0x15a80000 0x00040000>; + reg = <0x0 0x15a80000 0x0 0x00040000>; clocks = <&bpmp TEGRA194_CLK_NVENC1>; clock-names = "nvenc"; resets = <&bpmp TEGRA194_RESET_NVENC1>; @@ -2273,7 +2262,7 @@ sor0: sor@15b00000 { compatible = "nvidia,tegra194-sor"; - reg = <0x15b00000 0x40000>; + reg = <0x0 0x15b00000 0x0 0x40000>; interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, <&bpmp TEGRA194_CLK_SOR0_OUT>, @@ -2297,7 +2286,7 @@ sor1: sor@15b40000 { compatible = "nvidia,tegra194-sor"; - reg = <0x15b40000 0x40000>; + reg = <0x0 0x15b40000 0x0 0x40000>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, <&bpmp TEGRA194_CLK_SOR1_OUT>, @@ -2321,7 +2310,7 @@ sor2: sor@15b80000 { compatible = "nvidia,tegra194-sor"; - reg = <0x15b80000 0x40000>; + reg = <0x0 0x15b80000 0x0 0x40000>; interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, <&bpmp TEGRA194_CLK_SOR2_OUT>, @@ -2345,7 +2334,7 @@ sor3: sor@15bc0000 { compatible = "nvidia,tegra194-sor"; - reg = <0x15bc0000 0x40000>; + reg = <0x0 0x15bc0000 0x0 0x40000>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, <&bpmp TEGRA194_CLK_SOR3_OUT>, @@ -2368,482 +2357,484 @@ }; }; - gpu@17000000 { - compatible = "nvidia,gv11b"; - reg = <0x17000000 0x1000000>, - <0x18000000 0x1000000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "stall", "nonstall"; - clocks = <&bpmp TEGRA194_CLK_GPCCLK>, - <&bpmp TEGRA194_CLK_GPU_PWR>, - <&bpmp TEGRA194_CLK_FUSE>; - clock-names = "gpu", "pwr", "fuse"; - resets = <&bpmp TEGRA194_RESET_GPU>; - reset-names = "gpu"; - dma-coherent; + pcie@14100000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, - <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; - interconnect-names = "dma-mem", "read-0-hp", "write-0", - "read-1", "read-1-hp", "write-1", - "read-2", "read-2-hp", "write-2", - "read-3", "read-3-hp", "write-3"; - }; - }; + status = "disabled"; - pcie@14100000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + linux,pci-domain = <1>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - linux,pci-domain = <1>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_1>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; - clock-names = "core"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_1>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 1>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ + <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + pcie@14120000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie@14120000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + linux,pci-domain = <2>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - linux,pci-domain = <2>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_2>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; - clock-names = "core"; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_2>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 2>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ + <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + pcie@14140000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie@14140000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + linux,pci-domain = <3>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - linux,pci-domain = <3>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_3>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; - clock-names = "core"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_3>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 3>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ + <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ + <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ - <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ - <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + pcie@14160000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie@14160000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + linux,pci-domain = <4>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - linux,pci-domain = <4>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; - clock-names = "core"; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 4>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 4>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ + <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + pcie-ep@14160000 { + compatible = "nvidia,tegra194-pcie-ep"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie@14180000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + num-lanes = <4>; + num-ib-windows = <2>; + num-ob-windows = <8>; - status = "disabled"; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; + clock-names = "core"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - linux,pci-domain = <0>; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; - clock-names = "core"; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; + nvidia,bpmp = <&bpmp 4>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - nvidia,bpmp = <&bpmp 0>; + pcie@14180000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + status = "disabled"; - bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + linux,pci-domain = <0>; - ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; + clock-names = "core"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_0>; + reset-names = "apb", "core"; - pcie@141a0000 { - compatible = "nvidia,tegra194-pcie"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - linux,pci-domain = <5>; + nvidia,bpmp = <&bpmp 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; - clock-names = "core"; + bus-range = <0x0 0xff>; - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA194_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; + ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ + <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - nvidia,bpmp = <&bpmp 5>; + pcie-ep@14180000 { + compatible = "nvidia,tegra194-pcie-ep"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + num-lanes = <8>; + num-ib-windows = <2>; + num-ob-windows = <8>; - bus-range = <0x0 0xff>; + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; + clock-names = "core"; - ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ - <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ - <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA194_RESET_PEX0_CORE_0>; + reset-names = "apb", "core"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - pcie-ep@14160000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + nvidia,bpmp = <&bpmp 0>; - status = "disabled"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - num-lanes = <4>; - num-ib-windows = <2>; - num-ob-windows = <8>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; - clock-names = "core"; + pcie@141a0000 { + compatible = "nvidia,tegra194-pcie"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ + reg-names = "appl", "config", "atu_dma", "dbi"; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; + status = "disabled"; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + linux,pci-domain = <5>; - nvidia,bpmp = <&bpmp 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA194_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; - pcie-ep@14180000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - status = "disabled"; + nvidia,bpmp = <&bpmp 5>; - num-lanes = <8>; - num-ib-windows = <2>; - num-ob-windows = <8>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; - clock-names = "core"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA194_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; + bus-range = <0x0 0xff>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ + <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ + <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ - nvidia,bpmp = <&bpmp 0>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + pcie-ep@141a0000 { + compatible = "nvidia,tegra194-pcie-ep"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; - }; + status = "disabled"; - pcie-ep@141a0000 { - compatible = "nvidia,tegra194-pcie-ep"; - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + num-lanes = <8>; + num-ib-windows = <2>; + num-ob-windows = <8>; - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; - num-lanes = <8>; - num-ib-windows = <2>; - num-ob-windows = <8>; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; + clock-names = "core"; - pinctrl-names = "default"; - pinctrl-0 = <&clkreq_c5_bi_dir_state>; + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA194_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; - clock-names = "core"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA194_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; + nvidia,bpmp = <&bpmp 5>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 5>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + }; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + gpu@17000000 { + compatible = "nvidia,gv11b"; + reg = <0x0 0x17000000 0x0 0x1000000>, + <0x0 0x18000000 0x0 0x1000000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "stall", "nonstall"; + clocks = <&bpmp TEGRA194_CLK_GPCCLK>, + <&bpmp TEGRA194_CLK_GPU_PWR>, + <&bpmp TEGRA194_CLK_FUSE>; + clock-names = "gpu", "pwr", "fuse"; + resets = <&bpmp TEGRA194_RESET_GPU>; + reset-names = "gpu"; + dma-coherent; - interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, + <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; + interconnect-names = "dma-mem", "read-0-hp", "write-0", + "read-1", "read-1-hp", "write-1", + "read-2", "read-2-hp", "write-2", + "read-3", "read-3-hp", "write-3"; + }; }; sram@40000000 { compatible = "nvidia,tegra194-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x50000>; + #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x50000>; + no-memory-wc; cpu_bpmp_tx: sram@4e000 { @@ -3117,6 +3108,13 @@ method = "smc"; }; + tcu: serial { + compatible = "nvidia,tegra194-tcu"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, + <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; + mbox-names = "rx", "tx"; + }; + sound { status = "disabled"; @@ -3137,13 +3135,6 @@ assigned-clock-rates = <258000000>; }; - tcu: serial { - compatible = "nvidia,tegra194-tcu"; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, - <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; - mbox-names = "rx", "tx"; - }; - thermal-zones { cpu-thermal { thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; diff --git a/dts/src/arm64/nvidia/tegra210-p2180.dtsi b/dts/src/arm64/nvidia/tegra210-p2180.dtsi index 75eb743a72..92163b6809 100644 --- a/dts/src/arm64/nvidia/tegra210-p2180.dtsi +++ b/dts/src/arm64/nvidia/tegra210-p2180.dtsi @@ -31,6 +31,23 @@ status = "okay"; }; + i2c@7000c500 { + status = "okay"; + + /* module ID EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + label = "module"; + vcc-supply = <&vdd_1v8>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -50,6 +67,22 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,suspend-fps-time-period-us = <1280>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,suspend-fps-time-period-us = <1280>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -84,22 +117,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,suspend-fps-time-period-us = <1280>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,suspend-fps-time-period-us = <1280>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - }; - regulators { in-ldo0-1-supply = <&vdd_pre>; in-ldo7-8-supply = <&vdd_pre>; @@ -265,23 +282,6 @@ }; }; - i2c@7000c500 { - status = "okay"; - - /* module ID EEPROM */ - eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - - label = "module"; - vcc-supply = <&vdd_1v8>; - address-width = <8>; - pagesize = <8>; - size = <256>; - read-only; - }; - }; - pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; diff --git a/dts/src/arm64/nvidia/tegra210-p2371-2180.dts b/dts/src/arm64/nvidia/tegra210-p2371-2180.dts index 1e26ca91a9..38f4ff229b 100644 --- a/dts/src/arm64/nvidia/tegra210-p2371-2180.dts +++ b/dts/src/arm64/nvidia/tegra210-p2371-2180.dts @@ -63,17 +63,17 @@ pwms = <&pwm 0 29334>; pwm-names = "lp8557"; - /* 3 LED string */ - rom_14h { - rom-addr = /bits/ 8 <0x14>; - rom-val = /bits/ 8 <0x87>; - }; - /* boost frequency 1 MHz */ rom_13h { rom-addr = /bits/ 8 <0x13>; rom-val = /bits/ 8 <0x01>; }; + + /* 3 LED string */ + rom_14h { + rom-addr = /bits/ 8 <0x14>; + rom-val = /bits/ 8 <0x87>; + }; }; }; @@ -116,14 +116,6 @@ aconnect@702c0000 { status = "okay"; - dma-controller@702e2000 { - status = "okay"; - }; - - interrupt-controller@702f9000 { - status = "okay"; - }; - ahub@702d0800 { status = "okay"; @@ -261,81 +253,6 @@ }; }; - dmic@702d4000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - - dmic@702d4100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - - dmic@702d4200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic3_ep>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - sfc@702d2000 { status = "okay"; @@ -436,56 +353,6 @@ }; }; - mvc@702da000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@702da200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - amx@702d3000 { status = "okay"; @@ -682,6 +549,81 @@ }; }; + dmic@702d4000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@702d4100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@702d4200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic3_ep>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + processing-engine@702d8000 { status = "okay"; @@ -732,6 +674,56 @@ }; }; + mvc@702da000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@702da200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + amixer@702dbb00 { status = "okay"; @@ -1335,6 +1327,14 @@ }; }; }; + + dma-controller@702e2000 { + status = "okay"; + }; + + interrupt-controller@702f9000 { + status = "okay"; + }; }; sound { diff --git a/dts/src/arm64/nvidia/tegra210-p2595.dtsi b/dts/src/arm64/nvidia/tegra210-p2595.dtsi index 6ae292da72..65181da730 100644 --- a/dts/src/arm64/nvidia/tegra210-p2595.dtsi +++ b/dts/src/arm64/nvidia/tegra210-p2595.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/pinctrl/pinctrl-tegra.h> + / { model = "NVIDIA Tegra210 P2595 I/O board"; compatible = "nvidia,p2595", "nvidia,tegra210"; diff --git a/dts/src/arm64/nvidia/tegra210-p2597.dtsi b/dts/src/arm64/nvidia/tegra210-p2597.dtsi index dd9a17922f..b4a1108c2d 100644 --- a/dts/src/arm64/nvidia/tegra210-p2597.dtsi +++ b/dts/src/arm64/nvidia/tegra210-p2597.dtsi @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/gpio/tegra-gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/pinctrl-tegra.h> / { model = "NVIDIA Tegra210 P2597 I/O board"; @@ -1667,7 +1670,7 @@ vin-supply = <&vdd_5v0_sys>; }; - vdd_cam_1v2: regulator-vdd-cam-1v8 { + vdd_cam_1v2: regulator-vdd-cam-1v2 { compatible = "regulator-fixed"; regulator-name = "vdd-cam-1v2"; regulator-min-microvolt = <1200000>; diff --git a/dts/src/arm64/nvidia/tegra210-p2894.dtsi b/dts/src/arm64/nvidia/tegra210-p2894.dtsi index 8e657b1056..1f263fd32a 100644 --- a/dts/src/arm64/nvidia/tegra210-p2894.dtsi +++ b/dts/src/arm64/nvidia/tegra210-p2894.dtsi @@ -1342,7 +1342,35 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; - max77620_default: pinmux@0 { + fps { + #address-cells = <1>; + #size-cells = <0>; + + fps0 { + reg = <0>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + + fps1 { + reg = <1>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + reg = <2>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + + hog-0 { + gpio-hog; + output-high; + gpios = <2 GPIO_ACTIVE_HIGH>, + <7 GPIO_ACTIVE_HIGH>; + }; + + max77620_default: pinmux { gpio0 { pins = "gpio0"; function = "gpio"; @@ -1383,34 +1411,6 @@ }; }; - hog-0 { - gpio-hog; - output-high; - gpios = <2 GPIO_ACTIVE_HIGH>, - <7 GPIO_ACTIVE_HIGH>; - }; - - fps { - #address-cells = <1>; - #size-cells = <0>; - - fps0 { - reg = <0>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - - fps1 { - reg = <1>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - - fps2 { - reg = <2>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - }; - regulators { in-ldo0-1-supply = <&max77620_sd2>; in-ldo7-8-supply = <&max77620_sd2>; @@ -1592,20 +1592,6 @@ #clock-cells = <0>; }; - gpio-keys { - compatible = "gpio-keys"; - status = "okay"; - - key-power { - debounce-interval = <30>; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - label = "Power"; - linux,code = <KEY_POWER>; - wakeup-event-action = <EV_ACT_ASSERTED>; - wakeup-source; - }; - }; - cpus { cpu@0 { enable-method = "psci"; @@ -1630,6 +1616,20 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + status = "okay"; + + key-power { + debounce-interval = <30>; + gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + label = "Power"; + linux,code = <KEY_POWER>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/dts/src/arm64/nvidia/tegra210-p3450-0000.dts b/dts/src/arm64/nvidia/tegra210-p3450-0000.dts index 2041371ea7..c9f488e14f 100644 --- a/dts/src/arm64/nvidia/tegra210-p3450-0000.dts +++ b/dts/src/arm64/nvidia/tegra210-p3450-0000.dts @@ -186,6 +186,22 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + maxim,suspend-fps-time-period-us = <5120>; + }; + + fps1 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,suspend-fps-time-period-us = <5120>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + max77620_default: pinmux { gpio0 { pins = "gpio0"; @@ -231,22 +247,6 @@ }; }; - fps { - fps0 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - maxim,suspend-fps-time-period-us = <5120>; - }; - - fps1 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,suspend-fps-time-period-us = <5120>; - }; - - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - }; - regulators { in-ldo0-1-supply = <&vdd_pre>; in-ldo2-supply = <&vdd_3v3_sys>; @@ -611,14 +611,6 @@ aconnect@702c0000 { status = "okay"; - dma-controller@702e2000 { - status = "okay"; - }; - - interrupt-controller@702f9000 { - status = "okay"; - }; - ahub@702d0800 { status = "okay"; @@ -678,56 +670,6 @@ }; }; - dmic@702d4000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic1_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic1_ep>; - }; - }; - - dmic1_port: port@1 { - reg = <1>; - - dmic1_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - - dmic@702d4100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic2_cif_ep: endpoint { - remote-endpoint = <&xbar_dmic2_ep>; - }; - }; - - dmic2_port: port@1 { - reg = <1>; - - dmic2_dap_ep: endpoint { - /* Placeholder for external Codec */ - }; - }; - }; - }; - sfc@702d2000 { status = "okay"; @@ -828,56 +770,6 @@ }; }; - mvc@702da000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc1_in_ep>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc1_out_ep>; - }; - }; - }; - }; - - mvc@702da200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in_ep: endpoint { - remote-endpoint = <&xbar_mvc2_in_ep>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out_ep: endpoint { - remote-endpoint = <&xbar_mvc2_out_ep>; - }; - }; - }; - }; - amx@702d3000 { status = "okay"; @@ -1074,6 +966,56 @@ }; }; + dmic@702d4000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic1_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic1_ep>; + }; + }; + + dmic1_port: port@1 { + reg = <1>; + + dmic1_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + + dmic@702d4100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic2_cif_ep: endpoint { + remote-endpoint = <&xbar_dmic2_ep>; + }; + }; + + dmic2_port: port@1 { + reg = <1>; + + dmic2_dap_ep: endpoint { + /* Placeholder for external Codec */ + }; + }; + }; + }; + processing-engine@702d8000 { status = "okay"; @@ -1124,6 +1066,56 @@ }; }; + mvc@702da000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc1_in_ep>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc1_out_ep>; + }; + }; + }; + }; + + mvc@702da200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in_ep: endpoint { + remote-endpoint = <&xbar_mvc2_in_ep>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out_ep: endpoint { + remote-endpoint = <&xbar_mvc2_out_ep>; + }; + }; + }; + }; + amixer@702dbb00 { status = "okay"; @@ -1695,6 +1687,14 @@ }; }; }; + + dma-controller@702e2000 { + status = "okay"; + }; + + interrupt-controller@702f9000 { + status = "okay"; + }; }; spi@70410000 { @@ -1739,69 +1739,17 @@ }; }; - fan: pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm 3 45334>; - - cooling-levels = <0 64 128 255>; - #cooling-cells = <2>; - }; - - thermal-zones { - cpu-thermal { - trips { - cpu_trip_critical: critical { - temperature = <96500>; - hysteresis = <0>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <70000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active: active { - temperature = <50000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_passive: passive { - temperature = <30000>; - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - cpu-critical { - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_critical>; - }; - - cpu-hot { - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_hot>; - }; - - cpu-active { - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active>; - }; - - cpu-passive { - cooling-device = <&fan 0 0>; - trip = <&cpu_trip_passive>; - }; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; + key-force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <BTN_1>; + debounce-interval = <30>; + }; + key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; @@ -1811,14 +1759,6 @@ wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; }; - - key-force-recovery { - label = "Force Recovery"; - gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <BTN_1>; - debounce-interval = <30>; - }; }; psci { @@ -1826,6 +1766,14 @@ method = "smc"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 3 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + vdd_5v0_sys: regulator-vdd-5v0-sys { compatible = "regulator-fixed"; @@ -1986,4 +1934,56 @@ label = "NVIDIA Jetson Nano APE"; }; + + thermal-zones { + cpu-thermal { + trips { + cpu_trip_critical: critical { + temperature = <96500>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <70000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active: active { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <30000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-critical { + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_critical>; + }; + + cpu-hot { + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_hot>; + }; + + cpu-active { + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active>; + }; + + cpu-passive { + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + }; + }; }; diff --git a/dts/src/arm64/nvidia/tegra210-smaug.dts b/dts/src/arm64/nvidia/tegra210-smaug.dts index 7c569695b7..d7d7c63e62 100644 --- a/dts/src/arm64/nvidia/tegra210-smaug.dts +++ b/dts/src/arm64/nvidia/tegra210-smaug.dts @@ -1389,6 +1389,23 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; + fps { + fps0 { + maxim,shutdown-fps-time-period-us = <5120>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + + fps1 { + maxim,shutdown-fps-time-period-us = <5120>; + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; + maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; + }; + + fps2 { + maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + }; + }; + max77620_default: pinmux { gpio0_1_2_7 { pins = "gpio0", "gpio1", "gpio2", "gpio7"; @@ -1409,32 +1426,15 @@ maxim,active-fps-power-down-slot = <2>; }; - gpio5_6 { - pins = "gpio5", "gpio6"; - function = "gpio"; - drive-push-pull = <1>; - }; - gpio4 { pins = "gpio4"; function = "32k-out1"; }; - }; - - fps { - fps0 { - maxim,shutdown-fps-time-period-us = <5120>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; - }; - - fps1 { - maxim,shutdown-fps-time-period-us = <5120>; - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; - maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; - }; - fps2 { - maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; + gpio5_6 { + pins = "gpio5", "gpio6"; + function = "gpio"; + drive-push-pull = <1>; }; }; @@ -1800,6 +1800,18 @@ wakeup-source; }; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>; @@ -1815,18 +1827,6 @@ linux,code = <SW_TABLET_MODE>; wakeup-source; }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEDOWN>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - }; }; max98357a { diff --git a/dts/src/arm64/nvidia/tegra210.dtsi b/dts/src/arm64/nvidia/tegra210.dtsi index bc0cacb20d..980565bf02 100644 --- a/dts/src/arm64/nvidia/tegra210.dtsi +++ b/dts/src/arm64/nvidia/tegra210.dtsi @@ -555,19 +555,19 @@ reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ <0x0 0x70003000 0x0 0x294>; /* Mux registers */ - sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { + sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { sdmmc1 { nvidia,pins = "drive_sdmmc1"; - nvidia,pull-down-strength = <0x8>; - nvidia,pull-up-strength = <0x8>; + nvidia,pull-down-strength = <0x4>; + nvidia,pull-up-strength = <0x3>; }; }; - sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { + sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { sdmmc1 { nvidia,pins = "drive_sdmmc1"; - nvidia,pull-down-strength = <0x4>; - nvidia,pull-up-strength = <0x3>; + nvidia,pull-down-strength = <0x8>; + nvidia,pull-up-strength = <0x8>; }; }; @@ -579,19 +579,19 @@ }; }; - sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { + sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { sdmmc3 { nvidia,pins = "drive_sdmmc3"; - nvidia,pull-down-strength = <0x8>; - nvidia,pull-up-strength = <0x8>; + nvidia,pull-down-strength = <0x4>; + nvidia,pull-up-strength = <0x3>; }; }; - sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { + sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { sdmmc3 { nvidia,pins = "drive_sdmmc3"; - nvidia,pull-down-strength = <0x4>; - nvidia,pull-up-strength = <0x3>; + nvidia,pull-down-strength = <0x8>; + nvidia,pull-up-strength = <0x8>; }; }; @@ -852,6 +852,38 @@ #interrupt-cells = <2>; interrupt-controller; + pinmux { + pex_dpd_disable: pex-dpd-disable { + pins = "pex-bias", "pex-clk1", "pex-clk2"; + low-power-disable; + }; + + pex_dpd_enable: pex-dpd-enable { + pins = "pex-bias", "pex-clk1", "pex-clk2"; + low-power-enable; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; + }; + powergates { pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, @@ -881,21 +913,12 @@ #power-domain-cells = <0>; }; - pd_xusbss: xusba { - clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; - resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; - #power-domain-cells = <0>; - }; - - pd_xusbdev: xusbb { - clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; - resets = <&tegra_car 95>; - #power-domain-cells = <0>; - }; - - pd_xusbhost: xusbc { - clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; - resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car 20>, + <&tegra_car 52>; #power-domain-cells = <0>; }; @@ -907,45 +930,22 @@ #power-domain-cells = <0>; }; - pd_venc: venc { - clocks = <&tegra_car TEGRA210_CLK_VI>, - <&tegra_car TEGRA210_CLK_CSI>; - resets = <&mc TEGRA210_MC_RESET_VI>, - <&tegra_car 20>, - <&tegra_car 52>; + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; #power-domain-cells = <0>; }; - }; - - pinmux { - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - - sdmmc3_1v8: sdmmc3-1v8 { - pins = "sdmmc3"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; - - pex_dpd_disable: pex-dpd-disable { - pins = "pex-bias", "pex-clk1", "pex-clk2"; - low-power-disable; + pd_xusbdev: xusbb { + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; + resets = <&tegra_car 95>; + #power-domain-cells = <0>; }; - pex_dpd_enable: pex-dpd-enable { - pins = "pex-bias", "pex-clk1", "pex-clk2"; - low-power-enable; + pd_xusbhost: xusbc { + clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; + #power-domain-cells = <0>; }; }; }; @@ -1388,50 +1388,6 @@ ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; status = "disabled"; - adma: dma-controller@702e2000 { - compatible = "nvidia,tegra210-adma"; - reg = <0x702e2000 0x2000>; - interrupt-parent = <&agic>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - clock-names = "d_audio"; - status = "disabled"; - }; - - agic: interrupt-controller@702f9000 { - compatible = "nvidia,tegra210-agic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x702f9000 0x1000>, - <0x702fa000 0x2000>; - interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&tegra_car TEGRA210_CLK_APE>; - clock-names = "clk"; - status = "disabled"; - }; - tegra_ahub: ahub@702d0800 { compatible = "nvidia,tegra210-ahub"; reg = <0x702d0800 0x800>; @@ -1620,42 +1576,6 @@ status = "disabled"; }; - tegra_dmic1: dmic@702d4000 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4000 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC1>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC1"; - status = "disabled"; - }; - - tegra_dmic2: dmic@702d4100 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4100 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC2>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC2"; - status = "disabled"; - }; - - tegra_dmic3: dmic@702d4200 { - compatible = "nvidia,tegra210-dmic"; - reg = <0x702d4200 0x100>; - clocks = <&tegra_car TEGRA210_CLK_DMIC3>; - clock-names = "dmic"; - assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; - assigned-clock-rates = <3072000>; - sound-name-prefix = "DMIC3"; - status = "disabled"; - }; - tegra_sfc1: sfc@702d2000 { compatible = "nvidia,tegra210-sfc"; reg = <0x702d2000 0x200>; @@ -1684,20 +1604,6 @@ status = "disabled"; }; - tegra_mvc1: mvc@702da000 { - compatible = "nvidia,tegra210-mvc"; - reg = <0x702da000 0x200>; - sound-name-prefix = "MVC1"; - status = "disabled"; - }; - - tegra_mvc2: mvc@702da200 { - compatible = "nvidia,tegra210-mvc"; - reg = <0x702da200 0x200>; - sound-name-prefix = "MVC2"; - status = "disabled"; - }; - tegra_amx1: amx@702d3000 { compatible = "nvidia,tegra210-amx"; reg = <0x702d3000 0x100>; @@ -1726,6 +1632,42 @@ status = "disabled"; }; + tegra_dmic1: dmic@702d4000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4000 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@702d4100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4100 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@702d4200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4200 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + tegra_ope1: processing-engine@702d8000 { compatible = "nvidia,tegra210-ope"; reg = <0x702d8000 0x100>; @@ -1766,6 +1708,20 @@ }; }; + tegra_mvc1: mvc@702da000 { + compatible = "nvidia,tegra210-mvc"; + reg = <0x702da000 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@702da200 { + compatible = "nvidia,tegra210-mvc"; + reg = <0x702da200 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + tegra_amixer: amixer@702dbb00 { compatible = "nvidia,tegra210-amixer"; reg = <0x702dbb00 0x800>; @@ -1856,6 +1812,50 @@ }; }; }; + + adma: dma-controller@702e2000 { + compatible = "nvidia,tegra210-adma"; + reg = <0x702e2000 0x2000>; + interrupt-parent = <&agic>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@702f9000 { + compatible = "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x702f9000 0x1000>, + <0x702fa000 0x2000>; + interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&tegra_car TEGRA210_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; }; spi@70410000 { diff --git a/dts/src/arm64/nvidia/tegra234-p3701-0000.dtsi b/dts/src/arm64/nvidia/tegra234-p3701-0000.dtsi index 8b86ea9cb5..2378da3242 100644 --- a/dts/src/arm64/nvidia/tegra234-p3701-0000.dtsi +++ b/dts/src/arm64/nvidia/tegra234-p3701-0000.dtsi @@ -6,42 +6,23 @@ model = "NVIDIA Jetson AGX Orin"; compatible = "nvidia,p3701-0000", "nvidia,tegra234"; - vdd_1v8_ls: regulator-vdd-1v8-ls { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8_LS"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_1v8_ao: regulator-vdd-1v8-ao { - compatible = "regulator-fixed"; - regulator-name = "VDD_1V8_AO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + bus@0 { + i2c@3160000 { + status = "okay"; - vdd_3v3_pcie: regulator-vdd-3v3-pcie { - compatible = "regulator-fixed"; - regulator-name = "VDD_3V3_PCIE"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; - regulator-boot-on; - enable-active-high; - }; + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; - vdd_12v_pcie: regulator-vdd-12v-pcie { - compatible = "regulator-fixed"; - regulator-name = "VDD_12V_PCIE"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; + label = "module"; + vcc-supply = <&vdd_1v8_hs>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; - bus@0 { spi@3270000 { status = "okay"; @@ -67,6 +48,29 @@ non-removable; }; + padctl@3520000 { + vclamp-usb-supply = <&vdd_1v8_ao>; + avdd-usb-supply = <&vdd_3v3_ao>; + + ports { + usb2-0 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-1 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-2 { + vbus-supply = <&vdd_5v0_sys>; + }; + + usb2-3 { + vbus-supply = <&vdd_5v0_sys>; + }; + }; + }; + rtc@c2a0000 { status = "okay"; }; @@ -75,4 +79,64 @@ nvidia,invert-interrupt; }; }; + + vdd_5v0_sys: regulator-vdd-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_ls: regulator-vdd-1v8-ls { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_LS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_hs: regulator-vdd-1v8-hs { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_HS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_ao: regulator-vdd-1v8-ao { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_AO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_3v3_ao: regulator-vdd-3v3-ao { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_AO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_3v3_pcie: regulator-vdd-3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_PCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; + + vdd_12v_pcie: regulator-vdd-12v-pcie { + compatible = "regulator-fixed"; + regulator-name = "VDD_12V_PCIE"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; }; diff --git a/dts/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts b/dts/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts index 96aa2267b0..8a9747855d 100644 --- a/dts/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/dts/src/arm64/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -17,6 +17,11 @@ serial1 = &uarta; }; + chosen { + bootargs = "console=ttyTCU0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + bus@0 { aconnect@2900000 { status = "okay"; @@ -24,867 +29,6 @@ ahub@2900800 { status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0: endpoint { - remote-endpoint = <&admaif0>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1: endpoint { - remote-endpoint = <&admaif1>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2: endpoint { - remote-endpoint = <&admaif2>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3: endpoint { - remote-endpoint = <&admaif3>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4: endpoint { - remote-endpoint = <&admaif4>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5: endpoint { - remote-endpoint = <&admaif5>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6: endpoint { - remote-endpoint = <&admaif6>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7: endpoint { - remote-endpoint = <&admaif7>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8: endpoint { - remote-endpoint = <&admaif8>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9: endpoint { - remote-endpoint = <&admaif9>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10: endpoint { - remote-endpoint = <&admaif10>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11: endpoint { - remote-endpoint = <&admaif11>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12: endpoint { - remote-endpoint = <&admaif12>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13: endpoint { - remote-endpoint = <&admaif13>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14: endpoint { - remote-endpoint = <&admaif14>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15: endpoint { - remote-endpoint = <&admaif15>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16: endpoint { - remote-endpoint = <&admaif16>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17: endpoint { - remote-endpoint = <&admaif17>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18: endpoint { - remote-endpoint = <&admaif18>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19: endpoint { - remote-endpoint = <&admaif19>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1: endpoint { - remote-endpoint = <&i2s1_cif>; - }; - }; - - xbar_i2s2_port: port@15 { - reg = <0x15>; - - xbar_i2s2: endpoint { - remote-endpoint = <&i2s2_cif>; - }; - }; - - xbar_i2s4_port: port@17 { - reg = <0x17>; - - xbar_i2s4: endpoint { - remote-endpoint = <&i2s4_cif>; - }; - }; - - xbar_i2s6_port: port@19 { - reg = <0x19>; - - xbar_i2s6: endpoint { - remote-endpoint = <&i2s6_cif>; - }; - }; - - xbar_dmic3_port: port@1c { - reg = <0x1c>; - - xbar_dmic3: endpoint { - remote-endpoint = <&dmic3_cif>; - }; - }; - - xbar_sfc1_in_port: port@20 { - reg = <0x20>; - - xbar_sfc1_in: endpoint { - remote-endpoint = <&sfc1_cif_in>; - }; - }; - - port@21 { - reg = <0x21>; - - xbar_sfc1_out: endpoint { - remote-endpoint = <&sfc1_cif_out>; - }; - }; - - xbar_sfc2_in_port: port@22 { - reg = <0x22>; - - xbar_sfc2_in: endpoint { - remote-endpoint = <&sfc2_cif_in>; - }; - }; - - port@23 { - reg = <0x23>; - - xbar_sfc2_out: endpoint { - remote-endpoint = <&sfc2_cif_out>; - }; - }; - - xbar_sfc3_in_port: port@24 { - reg = <0x24>; - - xbar_sfc3_in: endpoint { - remote-endpoint = <&sfc3_cif_in>; - }; - }; - - port@25 { - reg = <0x25>; - - xbar_sfc3_out: endpoint { - remote-endpoint = <&sfc3_cif_out>; - }; - }; - - xbar_sfc4_in_port: port@26 { - reg = <0x26>; - - xbar_sfc4_in: endpoint { - remote-endpoint = <&sfc4_cif_in>; - }; - }; - - port@27 { - reg = <0x27>; - - xbar_sfc4_out: endpoint { - remote-endpoint = <&sfc4_cif_out>; - }; - }; - - xbar_mvc1_in_port: port@28 { - reg = <0x28>; - - xbar_mvc1_in: endpoint { - remote-endpoint = <&mvc1_cif_in>; - }; - }; - - port@29 { - reg = <0x29>; - - xbar_mvc1_out: endpoint { - remote-endpoint = <&mvc1_cif_out>; - }; - }; - - xbar_mvc2_in_port: port@2a { - reg = <0x2a>; - - xbar_mvc2_in: endpoint { - remote-endpoint = <&mvc2_cif_in>; - }; - }; - - port@2b { - reg = <0x2b>; - - xbar_mvc2_out: endpoint { - remote-endpoint = <&mvc2_cif_out>; - }; - }; - - xbar_amx1_in1_port: port@2c { - reg = <0x2c>; - - xbar_amx1_in1: endpoint { - remote-endpoint = <&amx1_in1>; - }; - }; - - xbar_amx1_in2_port: port@2d { - reg = <0x2d>; - - xbar_amx1_in2: endpoint { - remote-endpoint = <&amx1_in2>; - }; - }; - - xbar_amx1_in3_port: port@2e { - reg = <0x2e>; - - xbar_amx1_in3: endpoint { - remote-endpoint = <&amx1_in3>; - }; - }; - - xbar_amx1_in4_port: port@2f { - reg = <0x2f>; - - xbar_amx1_in4: endpoint { - remote-endpoint = <&amx1_in4>; - }; - }; - - port@30 { - reg = <0x30>; - - xbar_amx1_out: endpoint { - remote-endpoint = <&amx1_out>; - }; - }; - - xbar_amx2_in1_port: port@31 { - reg = <0x31>; - - xbar_amx2_in1: endpoint { - remote-endpoint = <&amx2_in1>; - }; - }; - - xbar_amx2_in2_port: port@32 { - reg = <0x32>; - - xbar_amx2_in2: endpoint { - remote-endpoint = <&amx2_in2>; - }; - }; - - xbar_amx2_in3_port: port@33 { - reg = <0x33>; - - xbar_amx2_in3: endpoint { - remote-endpoint = <&amx2_in3>; - }; - }; - - xbar_amx2_in4_port: port@34 { - reg = <0x34>; - - xbar_amx2_in4: endpoint { - remote-endpoint = <&amx2_in4>; - }; - }; - - port@35 { - reg = <0x35>; - - xbar_amx2_out: endpoint { - remote-endpoint = <&amx2_out>; - }; - }; - - xbar_amx3_in1_port: port@36 { - reg = <0x36>; - - xbar_amx3_in1: endpoint { - remote-endpoint = <&amx3_in1>; - }; - }; - - xbar_amx3_in2_port: port@37 { - reg = <0x37>; - - xbar_amx3_in2: endpoint { - remote-endpoint = <&amx3_in2>; - }; - }; - - xbar_amx3_in3_port: port@38 { - reg = <0x38>; - - xbar_amx3_in3: endpoint { - remote-endpoint = <&amx3_in3>; - }; - }; - - xbar_amx3_in4_port: port@39 { - reg = <0x39>; - - xbar_amx3_in4: endpoint { - remote-endpoint = <&amx3_in4>; - }; - }; - - port@3a { - reg = <0x3a>; - - xbar_amx3_out: endpoint { - remote-endpoint = <&amx3_out>; - }; - }; - - xbar_amx4_in1_port: port@3b { - reg = <0x3b>; - - xbar_amx4_in1: endpoint { - remote-endpoint = <&amx4_in1>; - }; - }; - - xbar_amx4_in2_port: port@3c { - reg = <0x3c>; - - xbar_amx4_in2: endpoint { - remote-endpoint = <&amx4_in2>; - }; - }; - - xbar_amx4_in3_port: port@3d { - reg = <0x3d>; - - xbar_amx4_in3: endpoint { - remote-endpoint = <&amx4_in3>; - }; - }; - - xbar_amx4_in4_port: port@3e { - reg = <0x3e>; - - xbar_amx4_in4: endpoint { - remote-endpoint = <&amx4_in4>; - }; - }; - - port@3f { - reg = <0x3f>; - - xbar_amx4_out: endpoint { - remote-endpoint = <&amx4_out>; - }; - }; - - xbar_adx1_in_port: port@40 { - reg = <0x40>; - - xbar_adx1_in: endpoint { - remote-endpoint = <&adx1_in>; - }; - }; - - port@41 { - reg = <0x41>; - - xbar_adx1_out1: endpoint { - remote-endpoint = <&adx1_out1>; - }; - }; - - port@42 { - reg = <0x42>; - - xbar_adx1_out2: endpoint { - remote-endpoint = <&adx1_out2>; - }; - }; - - port@43 { - reg = <0x43>; - - xbar_adx1_out3: endpoint { - remote-endpoint = <&adx1_out3>; - }; - }; - - port@44 { - reg = <0x44>; - - xbar_adx1_out4: endpoint { - remote-endpoint = <&adx1_out4>; - }; - }; - - xbar_adx2_in_port: port@45 { - reg = <0x45>; - - xbar_adx2_in: endpoint { - remote-endpoint = <&adx2_in>; - }; - }; - - port@46 { - reg = <0x46>; - - xbar_adx2_out1: endpoint { - remote-endpoint = <&adx2_out1>; - }; - }; - - port@47 { - reg = <0x47>; - - xbar_adx2_out2: endpoint { - remote-endpoint = <&adx2_out2>; - }; - }; - - port@48 { - reg = <0x48>; - - xbar_adx2_out3: endpoint { - remote-endpoint = <&adx2_out3>; - }; - }; - - port@49 { - reg = <0x49>; - - xbar_adx2_out4: endpoint { - remote-endpoint = <&adx2_out4>; - }; - }; - - xbar_adx3_in_port: port@4a { - reg = <0x4a>; - - xbar_adx3_in: endpoint { - remote-endpoint = <&adx3_in>; - }; - }; - - port@4b { - reg = <0x4b>; - - xbar_adx3_out1: endpoint { - remote-endpoint = <&adx3_out1>; - }; - }; - - port@4c { - reg = <0x4c>; - - xbar_adx3_out2: endpoint { - remote-endpoint = <&adx3_out2>; - }; - }; - - port@4d { - reg = <0x4d>; - - xbar_adx3_out3: endpoint { - remote-endpoint = <&adx3_out3>; - }; - }; - - port@4e { - reg = <0x4e>; - - xbar_adx3_out4: endpoint { - remote-endpoint = <&adx3_out4>; - }; - }; - - xbar_adx4_in_port: port@4f { - reg = <0x4f>; - - xbar_adx4_in: endpoint { - remote-endpoint = <&adx4_in>; - }; - }; - - port@50 { - reg = <0x50>; - - xbar_adx4_out1: endpoint { - remote-endpoint = <&adx4_out1>; - }; - }; - - port@51 { - reg = <0x51>; - - xbar_adx4_out2: endpoint { - remote-endpoint = <&adx4_out2>; - }; - }; - - port@52 { - reg = <0x52>; - - xbar_adx4_out3: endpoint { - remote-endpoint = <&adx4_out3>; - }; - }; - - port@53 { - reg = <0x53>; - - xbar_adx4_out4: endpoint { - remote-endpoint = <&adx4_out4>; - }; - }; - - xbar_mix_in1_port: port@54 { - reg = <0x54>; - - xbar_mix_in1: endpoint { - remote-endpoint = <&mix_in1>; - }; - }; - - xbar_mix_in2_port: port@55 { - reg = <0x55>; - - xbar_mix_in2: endpoint { - remote-endpoint = <&mix_in2>; - }; - }; - - xbar_mix_in3_port: port@56 { - reg = <0x56>; - - xbar_mix_in3: endpoint { - remote-endpoint = <&mix_in3>; - }; - }; - - xbar_mix_in4_port: port@57 { - reg = <0x57>; - - xbar_mix_in4: endpoint { - remote-endpoint = <&mix_in4>; - }; - }; - - xbar_mix_in5_port: port@58 { - reg = <0x58>; - - xbar_mix_in5: endpoint { - remote-endpoint = <&mix_in5>; - }; - }; - - xbar_mix_in6_port: port@59 { - reg = <0x59>; - - xbar_mix_in6: endpoint { - remote-endpoint = <&mix_in6>; - }; - }; - - xbar_mix_in7_port: port@5a { - reg = <0x5a>; - - xbar_mix_in7: endpoint { - remote-endpoint = <&mix_in7>; - }; - }; - - xbar_mix_in8_port: port@5b { - reg = <0x5b>; - - xbar_mix_in8: endpoint { - remote-endpoint = <&mix_in8>; - }; - }; - - xbar_mix_in9_port: port@5c { - reg = <0x5c>; - - xbar_mix_in9: endpoint { - remote-endpoint = <&mix_in9>; - }; - }; - - xbar_mix_in10_port: port@5d { - reg = <0x5d>; - - xbar_mix_in10: endpoint { - remote-endpoint = <&mix_in10>; - }; - }; - - port@5e { - reg = <0x5e>; - - xbar_mix_out1: endpoint { - remote-endpoint = <&mix_out1>; - }; - }; - - port@5f { - reg = <0x5f>; - - xbar_mix_out2: endpoint { - remote-endpoint = <&mix_out2>; - }; - }; - - port@60 { - reg = <0x60>; - - xbar_mix_out3: endpoint { - remote-endpoint = <&mix_out3>; - }; - }; - - port@61 { - reg = <0x61>; - - xbar_mix_out4: endpoint { - remote-endpoint = <&mix_out4>; - }; - }; - - port@62 { - reg = <0x62>; - - xbar_mix_out5: endpoint { - remote-endpoint = <&mix_out5>; - }; - }; - - xbar_asrc_in1_port: port@63 { - reg = <0x63>; - - xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; - }; - }; - - port@64 { - reg = <0x64>; - - xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; - }; - }; - - xbar_asrc_in2_port: port@65 { - reg = <0x65>; - - xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; - }; - }; - - port@66 { - reg = <0x66>; - - xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; - }; - }; - - xbar_asrc_in3_port: port@67 { - reg = <0x67>; - - xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; - }; - }; - - port@68 { - reg = <0x68>; - - xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; - }; - }; - - xbar_asrc_in4_port: port@69 { - reg = <0x69>; - - xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; - }; - }; - - port@6a { - reg = <0x6a>; - - xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; - }; - }; - - xbar_asrc_in5_port: port@6b { - reg = <0x6b>; - - xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; - }; - }; - - port@6c { - reg = <0x6c>; - - xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; - }; - }; - - xbar_asrc_in6_port: port@6d { - reg = <0x6d>; - - xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; - }; - }; - - port@6e { - reg = <0x6e>; - - xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; - }; - }; - - xbar_asrc_in7_port: port@6f { - reg = <0x6f>; - - xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; - }; - }; - - xbar_ope1_in_port: port@70 { - reg = <0x70>; - - xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; - }; - }; - - port@71 { - reg = <0x71>; - - xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; - }; - }; - }; - i2s@2901000 { status = "okay"; @@ -1991,6 +1135,867 @@ }; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3: endpoint { + remote-endpoint = <&dmic3_cif>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_mix_in1_port: port@54 { + reg = <0x54>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@55 { + reg = <0x55>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@56 { + reg = <0x56>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@57 { + reg = <0x57>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@58 { + reg = <0x58>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@59 { + reg = <0x59>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@5a { + reg = <0x5a>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@5b { + reg = <0x5b>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@5c { + reg = <0x5c>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@5d { + reg = <0x5d>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + }; }; dma-controller@2930000 { @@ -2022,14 +2027,100 @@ nvidia,model = "NVIDIA Jetson AGX Orin HDA"; status = "okay"; }; - }; - chosen { - bootargs = "console=ttyTCU0,115200n8"; - stdout-path = "serial0:115200n8"; - }; + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + status = "okay"; + }; + + usb2-1 { + status = "okay"; + }; + + usb2-2 { + status = "okay"; + }; + + usb2-3 { + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + status = "okay"; + }; + + usb3-1 { + status = "okay"; + }; + + usb3-2 { + status = "okay"; + }; + }; + }; + }; + + ports { + usb2-0 { + mode = "host"; + status = "okay"; + }; + + usb2-1 { + mode = "host"; + status = "okay"; + }; + + usb2-2 { + mode = "host"; + status = "okay"; + }; + + usb2-3 { + mode = "host"; + status = "okay"; + }; + + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + + usb3-2 { + nvidia,usb2-companion = <3>; + status = "okay"; + }; + }; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", + "usb3-0", "usb3-1", "usb3-2"; + }; - bus@0 { ethernet@6800000 { status = "okay"; @@ -2048,6 +2139,57 @@ }; }; }; + + pcie@14100000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + pcie@14160000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, + <&p2u_hsio_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + pcie@141a0000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + vpcie12v-supply = <&vdd_12v_pcie>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; + + pcie-ep@141a0000 { + status = "disabled"; + + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + + reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; + + nvidia,refclk-select-gpios = <&gpio_aon + TEGRA234_AON_GPIO(AA, 4) + GPIO_ACTIVE_HIGH>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; }; gpio-keys { @@ -2078,6 +2220,14 @@ }; }; + pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + + cooling-levels = <0 95 178 255>; + #cooling-cells = <2>; + }; + serial { status = "okay"; }; @@ -2144,63 +2294,4 @@ label = "NVIDIA Jetson AGX Orin APE"; }; - - pcie@14100000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_3>; - phy-names = "p2u-0"; - }; - - pcie@14160000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, - <&p2u_hsio_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; - - pcie@141a0000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - vpcie12v-supply = <&vdd_12v_pcie>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - pcie-ep@141a0000 { - status = "disabled"; - - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - - reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; - - nvidia,refclk-select-gpios = <&gpio_aon - TEGRA234_AON_GPIO(AA, 4) - GPIO_ACTIVE_HIGH>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - pwm-fan { - compatible = "pwm-fan"; - pwms = <&pwm3 0 45334>; - - cooling-levels = <0 95 178 255>; - #cooling-cells = <2>; - }; }; diff --git a/dts/src/arm64/nvidia/tegra234-p3737-0000.dtsi b/dts/src/arm64/nvidia/tegra234-p3737-0000.dtsi index e76894574d..022a5408d8 100644 --- a/dts/src/arm64/nvidia/tegra234-p3737-0000.dtsi +++ b/dts/src/arm64/nvidia/tegra234-p3737-0000.dtsi @@ -4,6 +4,22 @@ compatible = "nvidia,p3737-0000"; bus@0 { + i2c@3160000 { + status = "okay"; + + eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + + label = "system"; + vcc-supply = <&vdd_1v8_sys>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + pwm@3280000 { status = "okay"; }; @@ -16,4 +32,12 @@ status = "okay"; }; }; + + vdd_1v8_sys: regulator-vdd-1v8-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_SYS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; }; diff --git a/dts/src/arm64/nvidia/tegra234.dtsi b/dts/src/arm64/nvidia/tegra234.dtsi index eaf05ee9ac..8fe8eda765 100644 --- a/dts/src/arm64/nvidia/tegra234.dtsi +++ b/dts/src/arm64/nvidia/tegra234.dtsi @@ -5,9 +5,9 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/tegra186-hsp.h> #include <dt-bindings/memory/tegra234-mc.h> +#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> #include <dt-bindings/power/tegra234-powergate.h> #include <dt-bindings/reset/tegra234-reset.h> -#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> / { compatible = "nvidia,tegra234"; @@ -17,15 +17,103 @@ bus@0 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; + + misc@100000 { + compatible = "nvidia,tegra234-misc"; + reg = <0x0 0x00100000 0x0 0xf000>, + <0x0 0x0010f000 0x0 0x1000>; + status = "okay"; + }; + + timer@2080000 { + compatible = "nvidia,tegra234-timer"; + reg = <0x0 0x02080000 0x0 0x00121000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + }; + + gpio: gpio@2200000 { + compatible = "nvidia,tegra234-gpio"; + reg-names = "security", "gpio"; + reg = <0x0 0x02200000 0x0 0x10000>, + <0x0 0x02210000 0x0 0x10000>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; gpcdma: dma-controller@2600000 { compatible = "nvidia,tegra234-gpcdma", "nvidia,tegra186-gpcdma"; - reg = <0x2600000 0x210000>; + reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma"; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, @@ -73,27 +161,29 @@ <&bpmp TEGRA234_CLK_APB2APE>; clock-names = "ape", "apb2ape"; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900000 0x02900000 0x200000>; status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; + tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra234-ahub"; - reg = <0x02900800 0x800>; + reg = <0x0 0x02900800 0x0 0x800>; clocks = <&bpmp TEGRA234_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x02900800 0x02900800 0x11800>; status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; + tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901000 0x100>; + reg = <0x0 0x2901000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S1>, <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -107,7 +197,7 @@ tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901100 0x100>; + reg = <0x0 0x2901100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S2>, <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -121,7 +211,7 @@ tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901200 0x100>; + reg = <0x0 0x2901200 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S3>, <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -135,7 +225,7 @@ tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901300 0x100>; + reg = <0x0 0x2901300 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S4>, <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -149,7 +239,7 @@ tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901400 0x100>; + reg = <0x0 0x2901400 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S5>, <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -163,7 +253,7 @@ tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x2901500 0x100>; + reg = <0x0 0x2901500 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S6>, <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -177,7 +267,7 @@ tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902000 0x200>; + reg = <0x0 0x2902000 0x0 0x200>; sound-name-prefix = "SFC1"; status = "disabled"; }; @@ -185,7 +275,7 @@ tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902200 0x200>; + reg = <0x0 0x2902200 0x0 0x200>; sound-name-prefix = "SFC2"; status = "disabled"; }; @@ -193,7 +283,7 @@ tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902400 0x200>; + reg = <0x0 0x2902400 0x0 0x200>; sound-name-prefix = "SFC3"; status = "disabled"; }; @@ -201,7 +291,7 @@ tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x2902600 0x200>; + reg = <0x0 0x2902600 0x0 0x200>; sound-name-prefix = "SFC4"; status = "disabled"; }; @@ -209,7 +299,7 @@ tegra_amx1: amx@2903000 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x2903000 0x100>; + reg = <0x0 0x2903000 0x0 0x100>; sound-name-prefix = "AMX1"; status = "disabled"; }; @@ -217,7 +307,7 @@ tegra_amx2: amx@2903100 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x2903100 0x100>; + reg = <0x0 0x2903100 0x0 0x100>; sound-name-prefix = "AMX2"; status = "disabled"; }; @@ -225,7 +315,7 @@ tegra_amx3: amx@2903200 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x2903200 0x100>; + reg = <0x0 0x2903200 0x0 0x100>; sound-name-prefix = "AMX3"; status = "disabled"; }; @@ -233,7 +323,7 @@ tegra_amx4: amx@2903300 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x2903300 0x100>; + reg = <0x0 0x2903300 0x0 0x100>; sound-name-prefix = "AMX4"; status = "disabled"; }; @@ -241,7 +331,7 @@ tegra_adx1: adx@2903800 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x2903800 0x100>; + reg = <0x0 0x2903800 0x0 0x100>; sound-name-prefix = "ADX1"; status = "disabled"; }; @@ -249,7 +339,7 @@ tegra_adx2: adx@2903900 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x2903900 0x100>; + reg = <0x0 0x2903900 0x0 0x100>; sound-name-prefix = "ADX2"; status = "disabled"; }; @@ -257,7 +347,7 @@ tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x2903a00 0x100>; + reg = <0x0 0x2903a00 0x0 0x100>; sound-name-prefix = "ADX3"; status = "disabled"; }; @@ -265,7 +355,7 @@ tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x2903b00 0x100>; + reg = <0x0 0x2903b00 0x0 0x100>; sound-name-prefix = "ADX4"; status = "disabled"; }; @@ -274,7 +364,7 @@ tegra_dmic1: dmic@2904000 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x2904000 0x100>; + reg = <0x0 0x2904000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC1>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; @@ -287,7 +377,7 @@ tegra_dmic2: dmic@2904100 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x2904100 0x100>; + reg = <0x0 0x2904100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC2>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; @@ -300,7 +390,7 @@ tegra_dmic3: dmic@2904200 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x2904200 0x100>; + reg = <0x0 0x2904200 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC3>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; @@ -313,7 +403,7 @@ tegra_dmic4: dmic@2904300 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x2904300 0x100>; + reg = <0x0 0x2904300 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC4>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; @@ -326,7 +416,7 @@ tegra_dspk1: dspk@2905000 { compatible = "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; - reg = <0x2905000 0x100>; + reg = <0x0 0x2905000 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DSPK1>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; @@ -339,7 +429,7 @@ tegra_dspk2: dspk@2905100 { compatible = "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; - reg = <0x2905100 0x100>; + reg = <0x0 0x2905100 0x0 0x100>; clocks = <&bpmp TEGRA234_CLK_DSPK2>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; @@ -352,30 +442,31 @@ tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra234-ope", "nvidia,tegra210-ope"; - reg = <0x2908000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x0 0x2908000 0x0 0x100>; sound-name-prefix = "OPE1"; status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + equalizer@2908100 { compatible = "nvidia,tegra234-peq", "nvidia,tegra210-peq"; - reg = <0x2908100 0x100>; + reg = <0x0 0x2908100 0x0 0x100>; }; dynamic-range-compressor@2908200 { compatible = "nvidia,tegra234-mbdrc", "nvidia,tegra210-mbdrc"; - reg = <0x2908200 0x200>; + reg = <0x0 0x2908200 0x0 0x200>; }; }; tegra_mvc1: mvc@290a000 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; - reg = <0x290a000 0x200>; + reg = <0x0 0x290a000 0x0 0x200>; sound-name-prefix = "MVC1"; status = "disabled"; }; @@ -383,7 +474,7 @@ tegra_mvc2: mvc@290a200 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; - reg = <0x290a200 0x200>; + reg = <0x0 0x290a200 0x0 0x200>; sound-name-prefix = "MVC2"; status = "disabled"; }; @@ -391,7 +482,7 @@ tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra234-amixer", "nvidia,tegra210-amixer"; - reg = <0x290bb00 0x800>; + reg = <0x0 0x290bb00 0x0 0x800>; sound-name-prefix = "MIXER1"; status = "disabled"; }; @@ -399,7 +490,7 @@ tegra_admaif: admaif@290f000 { compatible = "nvidia,tegra234-admaif", "nvidia,tegra186-admaif"; - reg = <0x0290f000 0x1000>; + reg = <0x0 0x0290f000 0x0 0x1000>; dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, @@ -450,7 +541,7 @@ tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra234-asrc", "nvidia,tegra186-asrc"; - reg = <0x2910000 0x2000>; + reg = <0x0 0x2910000 0x0 0x2000>; sound-name-prefix = "ASRC1"; status = "disabled"; }; @@ -459,7 +550,7 @@ adma: dma-controller@2930000 { compatible = "nvidia,tegra234-adma", "nvidia,tegra186-adma"; - reg = <0x02930000 0x20000>; + reg = <0x0 0x02930000 0x0 0x20000>; interrupt-parent = <&agic>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, @@ -504,8 +595,8 @@ "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x02a41000 0x1000>, - <0x02a42000 0x2000>; + reg = <0x0 0x02a41000 0x0 0x1000>, + <0x0 0x02a42000 0x0 0x2000>; interrupts = <GIC_SPI 145 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -515,214 +606,26 @@ }; }; - misc@100000 { - compatible = "nvidia,tegra234-misc"; - reg = <0x00100000 0xf000>, - <0x0010f000 0x1000>; - status = "okay"; - }; - - timer@2080000 { - compatible = "nvidia,tegra234-timer"; - reg = <0x02080000 0x00121000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; - }; - - host1x@13e00000 { - compatible = "nvidia,tegra234-host1x"; - reg = <0x13e00000 0x10000>, - <0x13e10000 0x10000>, - <0x13e40000 0x10000>; - reg-names = "common", "hypervisor", "vm"; - interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", - "syncpt5", "syncpt6", "syncpt7", "host1x"; - clocks = <&bpmp TEGRA234_CLK_HOST1X>; - clock-names = "host1x"; - - #address-cells = <1>; - #size-cells = <1>; - - ranges = <0x14800000 0x14800000 0x02000000>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; - interconnect-names = "dma-mem"; - iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; - - /* Context isolation domains */ - iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, - <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, - <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, - <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, - <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, - <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, - <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, - <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, - <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, - <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, - <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, - <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, - <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, - <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, - <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, - <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; - - vic@15340000 { - compatible = "nvidia,tegra234-vic"; - reg = <0x15340000 0x00040000>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA234_CLK_VIC>; - clock-names = "vic"; - resets = <&bpmp TEGRA234_RESET_VIC>; - reset-names = "vic"; - - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, - <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu_niso1 TEGRA234_SID_VIC>; - dma-coherent; - }; - - nvdec@15480000 { - compatible = "nvidia,tegra234-nvdec"; - reg = <0x15480000 0x00040000>; - clocks = <&bpmp TEGRA234_CLK_NVDEC>, - <&bpmp TEGRA234_CLK_FUSE>, - <&bpmp TEGRA234_CLK_TSEC_PKA>; - clock-names = "nvdec", "fuse", "tsec_pka"; - resets = <&bpmp TEGRA234_RESET_NVDEC>; - reset-names = "nvdec"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, - <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; - dma-coherent; - - nvidia,memory-controller = <&mc>; - - /* - * Placeholder values that firmware needs to update with the real - * offsets parsed from the microcode headers. - */ - nvidia,bl-manifest-offset = <0>; - nvidia,bl-data-offset = <0>; - nvidia,bl-code-offset = <0>; - nvidia,os-manifest-offset = <0>; - nvidia,os-data-offset = <0>; - nvidia,os-code-offset = <0>; - - /* - * Firmware needs to set this to "okay" once the above values have - * been updated. - */ - status = "disabled"; - }; - }; - - gpio: gpio@2200000 { - compatible = "nvidia,tegra234-gpio"; - reg-names = "security", "gpio"; - reg = <0x02200000 0x10000>, - <0x02210000 0x10000>; - interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <2>; - interrupt-controller; - #gpio-cells = <2>; - gpio-controller; - }; - mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x10000>, /* MC-SID */ - <0x02c10000 0x10000>, /* MC Broadcast*/ - <0x02c20000 0x10000>, /* MC0 */ - <0x02c30000 0x10000>, /* MC1 */ - <0x02c40000 0x10000>, /* MC2 */ - <0x02c50000 0x10000>, /* MC3 */ - <0x02b80000 0x10000>, /* MC4 */ - <0x02b90000 0x10000>, /* MC5 */ - <0x02ba0000 0x10000>, /* MC6 */ - <0x02bb0000 0x10000>, /* MC7 */ - <0x01700000 0x10000>, /* MC8 */ - <0x01710000 0x10000>, /* MC9 */ - <0x01720000 0x10000>, /* MC10 */ - <0x01730000 0x10000>, /* MC11 */ - <0x01740000 0x10000>, /* MC12 */ - <0x01750000 0x10000>, /* MC13 */ - <0x01760000 0x10000>, /* MC14 */ - <0x01770000 0x10000>; /* MC15 */ + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ + <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ + <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ + <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ + <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ + <0x0 0x01700000 0x0 0x10000>, /* MC8 */ + <0x0 0x01710000 0x0 0x10000>, /* MC9 */ + <0x0 0x01720000 0x0 0x10000>, /* MC10 */ + <0x0 0x01730000 0x0 0x10000>, /* MC11 */ + <0x0 0x01740000 0x0 0x10000>, /* MC12 */ + <0x0 0x01750000 0x0 0x10000>, /* MC13 */ + <0x0 0x01760000 0x0 0x10000>, /* MC14 */ + <0x0 0x01770000 0x0 0x10000>; /* MC15 */ reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; @@ -732,10 +635,9 @@ #address-cells = <2>; #size-cells = <2>; - - ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, - <0x02b80000 0x0 0x02b80000 0x0 0x040000>, - <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; /* * Bit 39 of addresses passing through the memory @@ -752,7 +654,7 @@ * * Limit the DMA range for memory clients to [38:0]. */ - dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; emc: external-memory-controller@2c60000 { compatible = "nvidia,tegra234-emc"; @@ -771,7 +673,7 @@ uarta: serial@3100000 { compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; - reg = <0x03100000 0x10000>; + reg = <0x0 0x03100000 0x0 0x10000>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_UARTA>; clock-names = "serial"; @@ -782,9 +684,11 @@ gen1_i2c: i2c@3160000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x3160000 0x100>; + reg = <0x0 0x3160000 0x0 0x100>; status = "disabled"; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA234_CLK_I2C1 &bpmp TEGRA234_CLK_PLLP_OUT0>; @@ -793,16 +697,16 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C1>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; }; cam_i2c: i2c@3180000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x3180000 0x100>; + reg = <0x0 0x3180000 0x0 0x100>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <400000>; clocks = <&bpmp TEGRA234_CLK_I2C3 @@ -812,16 +716,16 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C3>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; }; dp_aux_ch1_i2c: i2c@3190000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x3190000 0x100>; + reg = <0x0 0x3190000 0x0 0x100>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C4 @@ -831,16 +735,16 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C4>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; }; dp_aux_ch0_i2c: i2c@31b0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x31b0000 0x100>; + reg = <0x0 0x31b0000 0x0 0x100>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C6 @@ -850,16 +754,16 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C6>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; }; dp_aux_ch2_i2c: i2c@31c0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x31c0000 0x100>; + reg = <0x0 0x31c0000 0x0 0x100>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C7 @@ -869,23 +773,23 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C7>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; }; uarti: serial@31d0000 { compatible = "arm,sbsa-uart"; - reg = <0x31d0000 0x10000>; + reg = <0x0 0x31d0000 0x0 0x10000>; interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; - reg = <0x31e0000 0x100>; + reg = <0x0 0x31e0000 0x0 0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C9 @@ -895,15 +799,13 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C9>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; }; spi@3270000 { compatible = "nvidia,tegra234-qspi"; - reg = <0x3270000 0x1000>; + reg = <0x0 0x3270000 0x0 0x1000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -916,7 +818,7 @@ pwm1: pwm@3280000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x3280000 0x10000>; + reg = <0x0 0x3280000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM1>; resets = <&bpmp TEGRA234_RESET_PWM1>; reset-names = "pwm"; @@ -926,7 +828,7 @@ pwm2: pwm@3290000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x3290000 0x10000>; + reg = <0x0 0x3290000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM2>; resets = <&bpmp TEGRA234_RESET_PWM2>; reset-names = "pwm"; @@ -936,7 +838,7 @@ pwm3: pwm@32a0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32a0000 0x10000>; + reg = <0x0 0x32a0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM3>; resets = <&bpmp TEGRA234_RESET_PWM3>; reset-names = "pwm"; @@ -946,7 +848,7 @@ pwm5: pwm@32c0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32c0000 0x10000>; + reg = <0x0 0x32c0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM5>; resets = <&bpmp TEGRA234_RESET_PWM5>; reset-names = "pwm"; @@ -956,7 +858,7 @@ pwm6: pwm@32d0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32d0000 0x10000>; + reg = <0x0 0x32d0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM6>; resets = <&bpmp TEGRA234_RESET_PWM6>; reset-names = "pwm"; @@ -966,7 +868,7 @@ pwm7: pwm@32e0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32e0000 0x10000>; + reg = <0x0 0x32e0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM7>; resets = <&bpmp TEGRA234_RESET_PWM7>; reset-names = "pwm"; @@ -976,7 +878,7 @@ pwm8: pwm@32f0000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0x32f0000 0x10000>; + reg = <0x0 0x32f0000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM8>; resets = <&bpmp TEGRA234_RESET_PWM8>; reset-names = "pwm"; @@ -986,7 +888,7 @@ spi@3300000 { compatible = "nvidia,tegra234-qspi"; - reg = <0x3300000 0x1000>; + reg = <0x0 0x3300000 0x0 0x1000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -999,7 +901,7 @@ mmc@3400000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03400000 0x20000>; + reg = <0x0 0x03400000 0x0 0x20000>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_SDMMC1>, <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; @@ -1034,7 +936,7 @@ mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; - reg = <0x03460000 0x20000>; + reg = <0x0 0x03460000 0x0 0x20000>; interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_SDMMC4>, <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; @@ -1063,7 +965,7 @@ hda@3510000 { compatible = "nvidia,tegra234-hda"; - reg = <0x3510000 0x10000>; + reg = <0x0 0x3510000 0x0 0x10000>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, <&bpmp TEGRA234_CLK_AZA_2XBIT>; @@ -1079,16 +981,184 @@ status = "disabled"; }; + xusb_padctl: padctl@3520000 { + compatible = "nvidia,tegra234-xusb-padctl"; + reg = <0x0 0x03520000 0x0 0x20000>, + <0x0 0x03540000 0x0 0x10000>; + reg-names = "padctl", "ao"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + + resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; + reset-names = "padctl"; + + status = "disabled"; + + pads { + usb2 { + clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; + clock-names = "trk"; + + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb2-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-2 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb3-3 { + nvidia,function = "xusb"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + }; + }; + + ports { + usb2-0 { + status = "disabled"; + }; + + usb2-1 { + status = "disabled"; + }; + + usb2-2 { + status = "disabled"; + }; + + usb2-3 { + status = "disabled"; + }; + + usb3-0 { + status = "disabled"; + }; + + usb3-1 { + status = "disabled"; + }; + + usb3-2 { + status = "disabled"; + }; + + usb3-3 { + status = "disabled"; + }; + }; + }; + + usb@3550000 { + compatible = "nvidia,tegra234-xudc"; + reg = <0x0 0x03550000 0x0 0x8000>, + <0x0 0x03558000 0x0 0x8000>; + reg-names = "base", "fpci"; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x0 0x03610000 0x0 0x40000>, + <0x0 0x03600000 0x0 0x10000>, + <0x0 0x03650000 0x0 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + dma-coherent; + status = "disabled"; + }; + fuse@3810000 { compatible = "nvidia,tegra234-efuse"; - reg = <0x03810000 0x10000>; + reg = <0x0 0x03810000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_FUSE>; clock-names = "fuse"; }; hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; - reg = <0x03c00000 0xa0000>; + reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, @@ -1106,7 +1176,7 @@ p2u_hsio_0: phy@3e00000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e00000 0x10000>; + reg = <0x0 0x03e00000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1114,7 +1184,7 @@ p2u_hsio_1: phy@3e10000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e10000 0x10000>; + reg = <0x0 0x03e10000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1122,7 +1192,7 @@ p2u_hsio_2: phy@3e20000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e20000 0x10000>; + reg = <0x0 0x03e20000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1130,7 +1200,7 @@ p2u_hsio_3: phy@3e30000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e30000 0x10000>; + reg = <0x0 0x03e30000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1138,7 +1208,7 @@ p2u_hsio_4: phy@3e40000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e40000 0x10000>; + reg = <0x0 0x03e40000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1146,7 +1216,7 @@ p2u_hsio_5: phy@3e50000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e50000 0x10000>; + reg = <0x0 0x03e50000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1154,7 +1224,7 @@ p2u_hsio_6: phy@3e60000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e60000 0x10000>; + reg = <0x0 0x03e60000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1162,7 +1232,7 @@ p2u_hsio_7: phy@3e70000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e70000 0x10000>; + reg = <0x0 0x03e70000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1170,7 +1240,7 @@ p2u_nvhs_0: phy@3e90000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03e90000 0x10000>; + reg = <0x0 0x03e90000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1178,7 +1248,7 @@ p2u_nvhs_1: phy@3ea0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ea0000 0x10000>; + reg = <0x0 0x03ea0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1186,7 +1256,7 @@ p2u_nvhs_2: phy@3eb0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03eb0000 0x10000>; + reg = <0x0 0x03eb0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1194,7 +1264,7 @@ p2u_nvhs_3: phy@3ec0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ec0000 0x10000>; + reg = <0x0 0x03ec0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1202,7 +1272,7 @@ p2u_nvhs_4: phy@3ed0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ed0000 0x10000>; + reg = <0x0 0x03ed0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1210,7 +1280,7 @@ p2u_nvhs_5: phy@3ee0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ee0000 0x10000>; + reg = <0x0 0x03ee0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1218,7 +1288,7 @@ p2u_nvhs_6: phy@3ef0000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03ef0000 0x10000>; + reg = <0x0 0x03ef0000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1226,7 +1296,7 @@ p2u_nvhs_7: phy@3f00000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f00000 0x10000>; + reg = <0x0 0x03f00000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1234,7 +1304,7 @@ p2u_gbe_0: phy@3f20000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f20000 0x10000>; + reg = <0x0 0x03f20000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1242,7 +1312,7 @@ p2u_gbe_1: phy@3f30000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f30000 0x10000>; + reg = <0x0 0x03f30000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1250,7 +1320,7 @@ p2u_gbe_2: phy@3f40000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f40000 0x10000>; + reg = <0x0 0x03f40000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1258,7 +1328,7 @@ p2u_gbe_3: phy@3f50000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f50000 0x10000>; + reg = <0x0 0x03f50000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1266,7 +1336,7 @@ p2u_gbe_4: phy@3f60000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f60000 0x10000>; + reg = <0x0 0x03f60000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1274,7 +1344,7 @@ p2u_gbe_5: phy@3f70000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f70000 0x10000>; + reg = <0x0 0x03f70000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1282,7 +1352,7 @@ p2u_gbe_6: phy@3f80000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f80000 0x10000>; + reg = <0x0 0x03f80000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1290,7 +1360,7 @@ p2u_gbe_7: phy@3f90000 { compatible = "nvidia,tegra234-p2u"; - reg = <0x03f90000 0x10000>; + reg = <0x0 0x03f90000 0x0 0x10000>; reg-names = "ctl"; #phy-cells = <0>; @@ -1298,9 +1368,9 @@ ethernet@6800000 { compatible = "nvidia,tegra234-mgbe"; - reg = <0x06800000 0x10000>, - <0x06810000 0x10000>, - <0x068a0000 0x10000>; + reg = <0x0 0x06800000 0x0 0x10000>, + <0x0 0x06810000 0x0 0x10000>, + <0x0 0x068a0000 0x0 0x10000>; reg-names = "hypervisor", "mac", "xpcs"; interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; @@ -1332,9 +1402,9 @@ ethernet@6900000 { compatible = "nvidia,tegra234-mgbe"; - reg = <0x06900000 0x10000>, - <0x06910000 0x10000>, - <0x069a0000 0x10000>; + reg = <0x0 0x06900000 0x0 0x10000>, + <0x0 0x06910000 0x0 0x10000>, + <0x0 0x069a0000 0x0 0x10000>; reg-names = "hypervisor", "mac", "xpcs"; interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; @@ -1366,9 +1436,9 @@ ethernet@6a00000 { compatible = "nvidia,tegra234-mgbe"; - reg = <0x06a00000 0x10000>, - <0x06a10000 0x10000>, - <0x06aa0000 0x10000>; + reg = <0x0 0x06a00000 0x0 0x10000>, + <0x0 0x06a10000 0x0 0x10000>, + <0x0 0x06aa0000 0x0 0x10000>; reg-names = "hypervisor", "mac", "xpcs"; interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; @@ -1400,9 +1470,9 @@ ethernet@6b00000 { compatible = "nvidia,tegra234-mgbe"; - reg = <0x06b00000 0x10000>, - <0x06b10000 0x10000>, - <0x06ba0000 0x10000>; + reg = <0x0 0x06b00000 0x0 0x10000>, + <0x0 0x06b10000 0x0 0x10000>, + <0x0 0x06ba0000 0x0 0x10000>; reg-names = "hypervisor", "mac", "xpcs"; interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "common"; @@ -1434,8 +1504,8 @@ smmu_niso1: iommu@8000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; - reg = <0x8000000 0x1000000>, - <0x7000000 0x1000000>; + reg = <0x0 0x8000000 0x0 0x1000000>, + <0x0 0x7000000 0x0 0x1000000>; interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, @@ -1576,21 +1646,21 @@ sce-fabric@b600000 { compatible = "nvidia,tegra234-sce-fabric"; - reg = <0xb600000 0x40000>; + reg = <0x0 0xb600000 0x0 0x40000>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; rce-fabric@be00000 { compatible = "nvidia,tegra234-rce-fabric"; - reg = <0xbe00000 0x40000>; + reg = <0x0 0xbe00000 0x0 0x40000>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; - reg = <0x0c150000 0x90000>; + reg = <0x0 0x0c150000 0x0 0x90000>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, @@ -1605,8 +1675,10 @@ gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; - reg = <0xc240000 0x100>; + reg = <0x0 0xc240000 0x0 0x100>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <100000>; clocks = <&bpmp TEGRA234_CLK_I2C2 @@ -1616,16 +1688,16 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C2>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 22>, <&gpcdma 22>; dma-names = "rx", "tx"; }; gen8_i2c: i2c@c250000 { compatible = "nvidia,tegra194-i2c"; - reg = <0xc250000 0x100>; + reg = <0x0 0xc250000 0x0 0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; clock-frequency = <400000>; clocks = <&bpmp TEGRA234_CLK_I2C8 @@ -1635,15 +1707,13 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C8>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 0>, <&gpcdma 0>; dma-names = "rx", "tx"; }; rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; - reg = <0x0c2a0000 0x10000>; + reg = <0x0 0x0c2a0000 0x0 0x10000>; interrupt-parent = <&pmc>; interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_CLK_32K>; @@ -1654,8 +1724,8 @@ gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra234-gpio-aon"; reg-names = "security", "gpio"; - reg = <0x0c2f0000 0x1000>, - <0x0c2f1000 0x1000>; + reg = <0x0 0x0c2f0000 0x0 0x1000>, + <0x0 0x0c2f1000 0x0 0x1000>; interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, @@ -1668,7 +1738,7 @@ pwm4: pwm@c340000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; - reg = <0xc340000 0x10000>; + reg = <0x0 0xc340000 0x0 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM4>; resets = <&bpmp TEGRA234_RESET_PWM4>; reset-names = "pwm"; @@ -1678,28 +1748,23 @@ pmc: pmc@c360000 { compatible = "nvidia,tegra234-pmc"; - reg = <0x0c360000 0x10000>, - <0x0c370000 0x10000>, - <0x0c380000 0x10000>, - <0x0c390000 0x10000>, - <0x0c3a0000 0x10000>; + reg = <0x0 0x0c360000 0x0 0x10000>, + <0x0 0x0c370000 0x0 0x10000>, + <0x0 0x0c380000 0x0 0x10000>, + <0x0 0x0c390000 0x0 0x10000>, + <0x0 0x0c3a0000 0x0 0x10000>; reg-names = "pmc", "wake", "aotag", "scratch", "misc"; #interrupt-cells = <2>; interrupt-controller; - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1-hv"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; - sdmmc1_1v8: sdmmc1-1v8 { pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3-hv"; + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; }; @@ -1707,33 +1772,45 @@ pins = "sdmmc3-hv"; power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; }; aon-fabric@c600000 { compatible = "nvidia,tegra234-aon-fabric"; - reg = <0xc600000 0x40000>; + reg = <0x0 0xc600000 0x0 0x40000>; interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; bpmp-fabric@d600000 { compatible = "nvidia,tegra234-bpmp-fabric"; - reg = <0xd600000 0x40000>; + reg = <0x0 0xd600000 0x0 0x40000>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; dce-fabric@de00000 { compatible = "nvidia,tegra234-sce-fabric"; - reg = <0xde00000 0x40000>; + reg = <0x0 0xde00000 0x0 0x40000>; interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; + gic: interrupt-controller@f400000 { compatible = "arm,gic-v3"; - reg = <0x0f400000 0x010000>, /* GICD */ - <0x0f440000 0x200000>; /* GICR */ + reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ + <0x0 0x0f440000 0x0 0x200000>; /* GICR */ interrupt-parent = <&gic>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; @@ -1744,7 +1821,7 @@ smmu_iso: iommu@10000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; - reg = <0x10000000 0x1000000>; + reg = <0x0 0x10000000 0x0 0x1000000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, @@ -1884,8 +1961,8 @@ smmu_niso0: iommu@12000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; - reg = <0x12000000 0x1000000>, - <0x11000000 0x1000000>; + reg = <0x0 0x12000000 0x0 0x1000000>, + <0x0 0x11000000 0x0 0x1000000>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, @@ -2026,771 +2103,867 @@ cbb-fabric@13a00000 { compatible = "nvidia,tegra234-cbb-fabric"; - reg = <0x13a00000 0x400000>; + reg = <0x0 0x13a00000 0x0 0x400000>; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; status = "okay"; }; - }; - ccplex@e000000 { - compatible = "nvidia,tegra234-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x5ffff>; - nvidia,bpmp = <&bpmp>; - status = "okay"; - }; + host1x@13e00000 { + compatible = "nvidia,tegra234-host1x"; + reg = <0x0 0x13e00000 0x0 0x10000>, + <0x0 0x13e10000 0x0 0x10000>, + <0x0 0x13e40000 0x0 0x10000>; + reg-names = "common", "hypervisor", "vm"; + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", + "syncpt5", "syncpt6", "syncpt7", "host1x"; + clocks = <&bpmp TEGRA234_CLK_HOST1X>; + clock-names = "host1x"; - pcie@140a0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; - reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <8>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; + interconnect-names = "dma-mem"; + iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; + dma-coherent; + + /* Context isolation domains */ + iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, + <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, + <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, + <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, + <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, + <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, + <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, + <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, + <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, + <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, + <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, + <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, + <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, + <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, + <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, + <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; + + vic@15340000 { + compatible = "nvidia,tegra234-vic"; + reg = <0x0 0x15340000 0x0 0x00040000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_VIC>; + clock-names = "vic"; + resets = <&bpmp TEGRA234_RESET_VIC>; + reset-names = "vic"; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_VIC>; + dma-coherent; + }; + + nvdec@15480000 { + compatible = "nvidia,tegra234-nvdec"; + reg = <0x0 0x15480000 0x0 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_NVDEC>, + <&bpmp TEGRA234_CLK_FUSE>, + <&bpmp TEGRA234_CLK_TSEC_PKA>; + clock-names = "nvdec", "fuse", "tsec_pka"; + resets = <&bpmp TEGRA234_RESET_NVDEC>; + reset-names = "nvdec"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; + dma-coherent; - clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; - clock-names = "core"; + nvidia,memory-controller = <&mc>; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_8>; - reset-names = "apb", "core"; + /* + * Placeholder values that firmware needs to update with the real + * offsets parsed from the microcode headers. + */ + nvidia,bl-manifest-offset = <0>; + nvidia,bl-data-offset = <0>; + nvidia,bl-code-offset = <0>; + nvidia,os-manifest-offset = <0>; + nvidia,os-data-offset = <0>; + nvidia,os-code-offset = <0>; - interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + /* + * Firmware needs to set this to "okay" once the above values have + * been updated. + */ + status = "disabled"; + }; + }; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + pcie@140a0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; + reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - nvidia,bpmp = <&bpmp 8>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <8>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; + clock-names = "core"; - bus-range = <0x0 0xff>; + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_8>; + reset-names = "apb", "core"; - ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + nvidia,bpmp = <&bpmp 8>; - pcie@140c0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; - reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <9>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; - clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; - clock-names = "core"; + ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_9>; - reset-names = "apb", "core"; + status = "disabled"; + }; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + pcie@140c0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; + reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <9>; - nvidia,bpmp = <&bpmp 9>; + clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; + clock-names = "core"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_9>; + reset-names = "apb", "core"; - bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ - <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + nvidia,bpmp = <&bpmp 9>; - status = "disabled"; - }; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - pcie@140e0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; - reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <10>; + bus-range = <0x0 0xff>; - clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; - clock-names = "core"; + ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ + <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_10>; - reset-names = "apb", "core"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + status = "disabled"; + }; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + pcie@140e0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; + reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - nvidia,bpmp = <&bpmp 10>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <10>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; + clock-names = "core"; - bus-range = <0x0 0xff>; + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_10>; + reset-names = "apb", "core"; - ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + nvidia,bpmp = <&bpmp 10>; - pcie@14100000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <1>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; - clock-names = "core"; + bus-range = <0x0 0xff>; - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_1>; - reset-names = "apb", "core"; + ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; - nvidia,bpmp = <&bpmp 1>; + pcie-ep@140e0000 { + compatible = "nvidia,tegra234-pcie-ep"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; + reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ + <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + num-lanes = <4>; - bus-range = <0x0 0xff>; + clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; + clock-names = "core"; - ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_10>; + reset-names = "apb", "core"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - status = "disabled"; - }; + nvidia,bpmp = <&bpmp 10>; - pcie@14120000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <2>; + nvidia,enable-ext-refclk; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; - clock-names = "core"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_2>; - reset-names = "apb", "core"; + status = "disabled"; + }; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + pcie@14100000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <1>; - nvidia,bpmp = <&bpmp 2>; + clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; + clock-names = "core"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_1>; + reset-names = "apb", "core"; - bus-range = <0x0 0xff>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + nvidia,bpmp = <&bpmp 1>; - status = "disabled"; - }; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - pcie@14140000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; - reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <1>; - num-viewport = <8>; - linux,pci-domain = <3>; + bus-range = <0x0 0xff>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; - clock-names = "core"; + ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_3>; - reset-names = "apb", "core"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + status = "disabled"; + }; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + pcie@14120000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - nvidia,bpmp = <&bpmp 3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <2>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; + clock-names = "core"; - bus-range = <0x0 0xff>; + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_2>; + reset-names = "apb", "core"; - ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + nvidia,bpmp = <&bpmp 2>; - pcie@14160000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; - reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <4>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; - clock-names = "core"; + bus-range = <0x0 0xff>; - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_4>; - reset-names = "apb", "core"; + ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; - nvidia,bpmp = <&bpmp 4>; + pcie@14140000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; + reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <1>; + num-viewport = <8>; + linux,pci-domain = <3>; - bus-range = <0x0 0xff>; + clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; + clock-names = "core"; - ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_3>; + reset-names = "apb", "core"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - status = "disabled"; - }; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - pcie@14180000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; - reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <0>; + nvidia,bpmp = <&bpmp 3>; - clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; - clock-names = "core"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, - <&bpmp TEGRA234_RESET_PEX0_CORE_0>; - reset-names = "apb", "core"; + bus-range = <0x0 0xff>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - nvidia,bpmp = <&bpmp 0>; + status = "disabled"; + }; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + pcie@14160000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <4>; - ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; + clock-names = "core"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_4>; + reset-names = "apb", "core"; - status = "disabled"; - }; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - pcie@141a0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - num-viewport = <8>; - linux,pci-domain = <5>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; - clock-names = "core"; + nvidia,bpmp = <&bpmp 4>; - resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA234_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + bus-range = <0x0 0xff>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - nvidia,bpmp = <&bpmp 5>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + status = "disabled"; + }; - bus-range = <0x0 0xff>; + pcie@14180000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; + reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ - <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <0>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; + clock-names = "core"; - status = "disabled"; - }; + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, + <&bpmp TEGRA234_RESET_PEX0_CORE_0>; + reset-names = "apb", "core"; - pcie@141c0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - num-viewport = <8>; - linux,pci-domain = <6>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; - clock-names = "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, - <&bpmp TEGRA234_RESET_PEX1_CORE_6>; - reset-names = "apb", "core"; + nvidia,bpmp = <&bpmp 0>; - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x0 0xff>; - nvidia,bpmp = <&bpmp 6>; + ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - bus-range = <0x0 0xff>; + status = "disabled"; + }; - ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ - <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + pcie@141a0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + num-viewport = <8>; + linux,pci-domain = <5>; - status = "disabled"; - }; + clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; + clock-names = "core"; - pcie@141e0000 { - compatible = "nvidia,tegra234-pcie"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ - <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ - reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <8>; - num-viewport = <8>; - linux,pci-domain = <7>; + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; - clock-names = "core"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_7>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ - <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ - interrupt-names = "intr", "msi"; + nvidia,bpmp = <&bpmp 5>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 7>; + bus-range = <0x0 0xff>; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ + <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - bus-range = <0x0 0xff>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ - <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ - <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + status = "disabled"; + }; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + pcie-ep@141a0000 { + compatible = "nvidia,tegra234-pcie-ep"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - status = "disabled"; - }; + num-lanes = <8>; - pcie-ep@141a0000 { - compatible = "nvidia,tegra234-pcie-ep"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; - reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ - <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; + clock-names = "core"; - num-lanes = <8>; + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_5>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; - clock-names = "core"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, - <&bpmp TEGRA234_RESET_PEX1_CORE_5>; - reset-names = "apb", "core"; + nvidia,bpmp = <&bpmp 5>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + nvidia,enable-ext-refclk; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,bpmp = <&bpmp 5>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - nvidia,enable-ext-refclk; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + status = "disabled"; + }; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + pcie@141c0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - status = "disabled"; - }; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + num-viewport = <8>; + linux,pci-domain = <6>; - pcie-ep@141c0000{ - compatible = "nvidia,tegra234-pcie-ep"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; - reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ - <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; + clock-names = "core"; - num-lanes = <4>; + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_6>; + reset-names = "apb", "core"; - clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; - clock-names = "core"; + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, - <&bpmp TEGRA234_RESET_PEX1_CORE_6>; - reset-names = "apb", "core"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; - interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + nvidia,bpmp = <&bpmp 6>; - nvidia,bpmp = <&bpmp 6>; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - nvidia,enable-ext-refclk; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + bus-range = <0x0 0xff>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ - status = "disabled"; - }; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - pcie-ep@141e0000{ - compatible = "nvidia,tegra234-pcie-ep"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; - reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ - <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + status = "disabled"; + }; - num-lanes = <8>; + pcie-ep@141c0000 { + compatible = "nvidia,tegra234-pcie-ep"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; + reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ + <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; - clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; - clock-names = "core"; + num-lanes = <4>; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_7>; - reset-names = "apb", "core"; + clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; + clock-names = "core"; - interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, + <&bpmp TEGRA234_RESET_PEX1_CORE_6>; + reset-names = "apb", "core"; - nvidia,bpmp = <&bpmp 7>; + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; - nvidia,enable-ext-refclk; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + nvidia,bpmp = <&bpmp 6>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + nvidia,enable-ext-refclk; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; - status = "disabled"; - }; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; - pcie-ep@140e0000{ - compatible = "nvidia,tegra234-pcie-ep"; - power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; - reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ - <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ - <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ - reg-names = "appl", "atu_dma", "dbi", "addr_space"; + status = "disabled"; + }; - num-lanes = <4>; + pcie@141e0000 { + compatible = "nvidia,tegra234-pcie"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ + <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; - clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; - clock-names = "core"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <8>; + num-viewport = <8>; + linux,pci-domain = <7>; - resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, - <&bpmp TEGRA234_RESET_PEX2_CORE_10>; - reset-names = "apb", "core"; + clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; + clock-names = "core"; - interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_7>; + reset-names = "apb", "core"; - nvidia,bpmp = <&bpmp 10>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; - nvidia,enable-ext-refclk; - nvidia,aspm-cmrt-us = <60>; - nvidia,aspm-pwr-on-t-us = <20>; - nvidia,aspm-l0s-entrance-latency-us = <3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, - <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; - interconnect-names = "dma-mem", "write"; - iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; - iommu-map-mask = <0x0>; - dma-coherent; + nvidia,bpmp = <&bpmp 7>; - status = "disabled"; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; + + ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ + <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + + status = "disabled"; + }; + + pcie-ep@141e0000 { + compatible = "nvidia,tegra234-pcie-ep"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; + reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ + <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ + <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ + <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ + reg-names = "appl", "atu_dma", "dbi", "addr_space"; + + num-lanes = <8>; + + clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; + clock-names = "core"; + + resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, + <&bpmp TEGRA234_RESET_PEX2_CORE_7>; + reset-names = "apb", "core"; + + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "intr"; + + nvidia,bpmp = <&bpmp 7>; + + nvidia,enable-ext-refclk; + nvidia,aspm-cmrt-us = <60>; + nvidia,aspm-pwr-on-t-us = <20>; + nvidia,aspm-l0s-entrance-latency-us = <3>; + + interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; + interconnect-names = "dma-mem", "write"; + iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; + iommu-map-mask = <0x0>; + dma-coherent; + + status = "disabled"; + }; }; sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x80000>; + #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x40000000 0x80000>; + no-memory-wc; cpu_bpmp_tx: sram@70000 { |