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authorSascha Hauer <s.hauer@pengutronix.de>2023-06-13 11:20:28 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2023-06-13 11:20:28 +0200
commit6b268debbf6f3ecc0432dd9ae57f428816d7ee85 (patch)
tree615c1ae7cf693470bc0953aa72da1305bd4f328c /dts/src/arm64/qcom/sm8450.dtsi
parent3fe16708d72bc4971709b9b284529c50c17654cd (diff)
downloadbarebox-6b268debbf6f3ecc0432dd9ae57f428816d7ee85.tar.gz
barebox-6b268debbf6f3ecc0432dd9ae57f428816d7ee85.tar.xz
dts: update to v6.4-rc6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'dts/src/arm64/qcom/sm8450.dtsi')
-rw-r--r--dts/src/arm64/qcom/sm8450.dtsi61
1 files changed, 35 insertions, 26 deletions
diff --git a/dts/src/arm64/qcom/sm8450.dtsi b/dts/src/arm64/qcom/sm8450.dtsi
index 595533aeaf..d59ea8ee71 100644
--- a/dts/src/arm64/qcom/sm8450.dtsi
+++ b/dts/src/arm64/qcom/sm8450.dtsi
@@ -57,12 +57,14 @@
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- next-level-cache = <&L3_0>;
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
L3_0: l3-cache {
- compatible = "cache";
- cache-level = <3>;
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
};
};
};
@@ -79,9 +81,10 @@
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- next-level-cache = <&L3_0>;
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
};
};
@@ -97,9 +100,10 @@
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- next-level-cache = <&L3_0>;
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
};
};
@@ -115,9 +119,10 @@
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- next-level-cache = <&L3_0>;
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
};
};
@@ -133,9 +138,10 @@
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- next-level-cache = <&L3_0>;
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
};
};
@@ -151,9 +157,10 @@
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- next-level-cache = <&L3_0>;
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
};
};
@@ -169,9 +176,10 @@
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- next-level-cache = <&L3_0>;
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
};
};
@@ -187,9 +195,10 @@
#cooling-cells = <2>;
clocks = <&cpufreq_hw 2>;
L2_700: l2-cache {
- compatible = "cache";
- cache-level = <2>;
- next-level-cache = <&L3_0>;
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ next-level-cache = <&L3_0>;
};
};