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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2022-11-14 16:54:36 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-11-14 16:54:36 +0100 |
| commit | ab1e21447d0b45d6689a7ddee51a5eadff1ebeeb (patch) | |
| tree | 2f303011dfe883f8b003fc88eed91568d3fbab88 /dts/src/riscv/microchip/mpfs-icicle-kit.dts | |
| parent | 082680652836cd17f2e0bb3da5bec35789e93483 (diff) | |
| parent | 6f98e5463b673e6dcf9a54c1571f95a567b65296 (diff) | |
| download | barebox-ab1e21447d0b45d6689a7ddee51a5eadff1ebeeb.tar.gz barebox-ab1e21447d0b45d6689a7ddee51a5eadff1ebeeb.tar.xz | |
Merge branch 'for-next/dts'
Diffstat (limited to 'dts/src/riscv/microchip/mpfs-icicle-kit.dts')
| -rw-r--r-- | dts/src/riscv/microchip/mpfs-icicle-kit.dts | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/dts/src/riscv/microchip/mpfs-icicle-kit.dts b/dts/src/riscv/microchip/mpfs-icicle-kit.dts index f3f87ed200..ec7b7c2a3c 100644 --- a/dts/src/riscv/microchip/mpfs-icicle-kit.dts +++ b/dts/src/riscv/microchip/mpfs-icicle-kit.dts @@ -11,7 +11,8 @@ / { model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; aliases { ethernet0 = &mac1; @@ -32,15 +33,26 @@ ddrc_cache_lo: memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x2e000000>; + reg = <0x0 0x80000000 0x0 0x40000000>; status = "okay"; }; ddrc_cache_hi: memory@1000000000 { device_type = "memory"; - reg = <0x10 0x0 0x0 0x40000000>; + reg = <0x10 0x40000000 0x0 0x40000000>; status = "okay"; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss_payload: region@BFC00000 { + reg = <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; }; &core_pwm0 { |