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| author | Christian Hemp <c.hemp@phytec.de> | 2013-08-08 14:45:43 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-03-26 21:07:53 +0100 |
| commit | 4c65c20f107113b82bf0aae6072fbb2affb6d1f7 (patch) | |
| tree | ba6807412903f90b2f3a6bd4486fac9c9930a077 /images | |
| parent | 286314915a777159aa9dc8820e0a1cd0e397616c (diff) | |
| download | barebox-4c65c20f107113b82bf0aae6072fbb2affb6d1f7.tar.gz barebox-4c65c20f107113b82bf0aae6072fbb2affb6d1f7.tar.xz | |
ARM: pfla02: Set new ethernet phy tx timings
TX_CLK line is approx. 54mm longer than other TX lines which adds
a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add
a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by
setting GTX pad skew value to 11100
Also add a delay for the RX delay lines, needed for the Duallite variant.
=> Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Diffstat (limited to 'images')
0 files changed, 0 insertions, 0 deletions