diff options
| author | Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com> | 2021-05-31 21:40:19 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-06-02 08:43:05 +0200 |
| commit | ac0d216bd657d044ea7aa22b7f2138752f3c6629 (patch) | |
| tree | 574dde2000712b46be5c254014561ebc7aa47af6 /images | |
| parent | 5b4dcc6fdeadf4844852efd7c950614de8525a83 (diff) | |
| download | barebox-ac0d216bd657d044ea7aa22b7f2138752f3c6629.tar.gz barebox-ac0d216bd657d044ea7aa22b7f2138752f3c6629.tar.xz | |
ARM: SoCFPGA: add Terasic DE10-Nano board support
The Terasic DE10-Nano board is based on CycloneV SoCFPGA (5CSEBA6) with
What has been tested to work:
- SD card
- Gigabit network
- FPGA (FPPx16 & FPPx32)
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
Link: https://lore.barebox.org/20210531194019.951-1-gwenj@trabucayre.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'images')
| -rw-r--r-- | images/Makefile.socfpga | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga index b36e2a5033..26220178af 100644 --- a/images/Makefile.socfpga +++ b/images/Makefile.socfpga @@ -30,6 +30,14 @@ pblb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += start_socfpga_de0_nano_soc FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblb socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img +pblb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += start_socfpga_de10_nano_xload +FILE_barebox-socfpga-de10_nano-xload.img = start_socfpga_de10_nano_xload.pblb.socfpgaimg +socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += barebox-socfpga-de10_nano-xload.img + +pblb-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += start_socfpga_de10_nano +FILE_barebox-socfpga-de10_nano.img = start_socfpga_de10_nano.pblb +socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE10_NANO) += barebox-socfpga-de10_nano.img + pblb-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles_xload FILE_barebox-socfpga-achilles-xload.img = start_socfpga_achilles_xload.pblb.socfpgaimg socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles-xload.img |