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authorSascha Hauer <s.hauer@pengutronix.de>2011-07-29 11:20:11 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2011-08-03 09:11:10 +0200
commit3100ea14668853aeedae85ec83e3536b59ba7728 (patch)
tree0fa218f88a470a9948eec79aa9aa0d65017d5c16 /include/common.h
parentf9f35ee93821048bbace895c5c688bafbda2c3f3 (diff)
downloadbarebox-3100ea14668853aeedae85ec83e3536b59ba7728.tar.gz
barebox-3100ea14668853aeedae85ec83e3536b59ba7728.tar.xz
ARM: rework MMU support
In barebox we used 1MiB sections to map our SDRAM cachable. This has the drawback that we have to map our sdram twice: cached for normal sdram and uncached for DMA operations. As address space gets sparse on newer systems we are sometines unable to find a suitably big enough area for the dma coherent space. This patch changes the MMU code to use second level page tables. With it we can implement dma_alloc_coherent as normal malloc, we just have to remap the allocated area uncached afterwards and map it cached again after free(). This makes arm_create_section(), setup_dma_coherent() and mmu_enable() noops. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include/common.h')
-rw-r--r--include/common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/common.h b/include/common.h
index f3353c8643..0ce4a70b56 100644
--- a/include/common.h
+++ b/include/common.h
@@ -221,6 +221,7 @@ int run_shell(void);
#define ULLONG_MAX (~0ULL)
#define PAGE_SIZE 4096
+#define PAGE_SHIFT 12
int memory_display(char *addr, ulong offs, ulong nbytes, int size);