clk: add STM32MP13 clock and reset drivers

The reset and clock control peripheral of the STM32MP13 is with
publicly available firmware exclusively handled by the secure world and
normal world needs to employ SCMI to interact with OP-TEE to toggle clocks
for it. Import the Linux driver to facilitate this.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20231127064947.2207726-10-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

2 files changed, 31 insertions, 0 deletions

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6d781fbfcc..eab8305821 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -29,6 +29,32 @@ static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
 					    val);
 }
 
+/**
+ * struct clk_rate_request - Structure encoding the clk constraints that
+ * a clock user might require.
+ *
+ * Should be initialized by calling clk_hw_init_rate_request().
+ *
+ * @core: 		Pointer to the struct clk_core affected by this request
+ * @rate:		Requested clock rate. This field will be adjusted by
+ *			clock drivers according to hardware capabilities.
+ * @min_rate:		Minimum rate imposed by clk users.
+ * @max_rate:		Maximum rate imposed by clk users.
+ * @best_parent_rate:	The best parent rate a parent can provide to fulfill the
+ *			requested constraints.
+ * @best_parent_hw:	The most appropriate parent clock that fulfills the
+ *			requested constraints.
+ *
+ */
+struct clk_rate_request {
+	struct clk_core *core;
+	unsigned long rate;
+	unsigned long min_rate;
+	unsigned long max_rate;
+	unsigned long best_parent_rate;
+	struct clk_hw *best_parent_hw;
+};
+
 #define CLK_HW_INIT(_name, _parent, _ops, _flags)		\
 	(&(struct clk_init_data) {				\
 		.flags		= _flags,			\
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 18fda074fd..7657ab6fc2 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -436,6 +436,11 @@ static inline void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
 	/* clk_get_parent always reads from HW, so nothing to update here */
 }
 
+static inline int __clk_get_enable_count(struct clk *clk)
+{
+	return !clk ? 0 : clk->enable_count;
+}
+
 unsigned long divider_recalc_rate(struct clk *clk, unsigned long parent_rate,
 		unsigned int val,
 		const struct clk_div_table *table,