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authorSascha Hauer <s.hauer@pengutronix.de>2019-08-14 09:32:55 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2019-08-14 09:56:19 +0200
commitb76d5bee8b1c034fb321540a782a176843531f77 (patch)
tree541d48ddee9d00b319e6815d556d1608ee510761 /include/serial
parent5b8ccd6752650d98b05c236ec9dbb21c3c69fb68 (diff)
downloadbarebox-b76d5bee8b1c034fb321540a782a176843531f77.tar.gz
barebox-b76d5bee8b1c034fb321540a782a176843531f77.tar.xz
serial: i.MX: Add i.MX1 lowlevel init function
The i.MX1 uart must be initialized slightly differently than on other SoCs. Add an i.MX1 specific init function. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include/serial')
-rw-r--r--include/serial/imx-uart.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h
index c23606569d..23cee26fcf 100644
--- a/include/serial/imx-uart.h
+++ b/include/serial/imx-uart.h
@@ -155,6 +155,27 @@ static inline void imx_uart_set_dte(void __iomem *uartbase)
writel(ufcr, uartbase + UFCR);
}
+static inline void imx1_uart_setup(void __iomem *uartbase)
+{
+ unsigned int refclock = 16000000;
+
+ writel(UCR1_UARTCLKEN, uartbase + UCR1);
+
+ writel(UCR2_IRTS | UCR2_WS | UCR2_TXEN | UCR2_RXEN | UCR2_SRST,
+ uartbase + UCR2);
+ writel(0, uartbase + UCR3);
+
+ writel((0b10 << UFCR_TXTL_SHF) | UFCR_RFDIV1 | (1 << UFCR_RXTL_SHF),
+ uartbase + UFCR);
+
+ writel(baudrate_to_ubir(CONFIG_BAUDRATE),
+ uartbase + UBIR);
+ writel(refclock_to_ubmr(refclock),
+ uartbase + UBMR);
+
+ writel(UCR1_UARTCLKEN | UCR1_UARTEN, uartbase + UCR1);
+}
+
static inline void imx50_uart_setup(void __iomem *uartbase)
{
imx_uart_setup(uartbase, 66666666);