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authorSascha Hauer <s.hauer@pengutronix.de>2014-03-07 09:25:02 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2014-03-07 09:25:02 +0100
commit2331b1d8e8d7aabe52b4fd65ca200cf8288aec88 (patch)
treeb72e8f7f08c76f91575a4a652655923821b9904b /include
parent9c2aa617030a44f3d336b5fef3861eac142290d2 (diff)
parentb3cd25785571160bd0f18e3da8d2101fcf415481 (diff)
downloadbarebox-2331b1d8e8d7aabe52b4fd65ca200cf8288aec88.tar.gz
barebox-2331b1d8e8d7aabe52b4fd65ca200cf8288aec88.tar.xz
Merge branch 'for-next/marvell'
Conflicts: arch/arm/dts/Makefile
Diffstat (limited to 'include')
-rw-r--r--include/linux/mbus.h61
-rw-r--r--include/linux/phy.h14
2 files changed, 75 insertions, 0 deletions
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
new file mode 100644
index 0000000000..578ff33146
--- /dev/null
+++ b/include/linux/mbus.h
@@ -0,0 +1,61 @@
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+
+struct resource;
+
+struct mbus_dram_target_info {
+ /*
+ * The 4-bit MBUS target ID of the DRAM controller.
+ */
+ u8 mbus_dram_target_id;
+
+ /*
+ * The base address, size, and MBUS attribute ID for each
+ * of the possible DRAM chip selects. Peripherals are
+ * required to support at least 4 decode windows.
+ */
+ int num_cs;
+ struct mbus_dram_window {
+ u8 cs_index;
+ u8 mbus_attr;
+ u32 base;
+ u32 size;
+ } cs[4];
+};
+
+/* Flags for PCI/PCIe address decoding regions */
+#define MVEBU_MBUS_PCI_IO 0x1
+#define MVEBU_MBUS_PCI_MEM 0x2
+#define MVEBU_MBUS_PCI_WA 0x3
+
+/*
+ * Magic value that explicits that we don't need a remapping-capable
+ * address decoding window.
+ */
+#define MVEBU_MBUS_NO_REMAP (0xffffffff)
+
+/* Maximum size of a mbus window name */
+#define MVEBU_MBUS_MAX_WINNAME_SZ 32
+
+const struct mbus_dram_target_info *mvebu_mbus_dram_info(void);
+void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
+void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+ unsigned int attribute,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap);
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+ phys_addr_t base, size_t size);
+int mvebu_mbus_del_window(phys_addr_t base, size_t size);
+
+#endif /* __LINUX_MBUS_H */
diff --git a/include/linux/phy.h b/include/linux/phy.h
index c8980b0191..9567c43e38 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -280,6 +280,20 @@ int phy_device_connect(struct eth_device *dev, struct mii_bus *bus, int addr,
void (*adjust_link) (struct eth_device *edev),
u32 flags, phy_interface_t interface);
+#if defined(CONFIG_OFTREE)
+int of_phy_device_connect(struct eth_device *edev, struct device_node *phy_np,
+ void (*adjust_link) (struct eth_device *edev),
+ u32 flags, phy_interface_t interface);
+#else
+static inline int of_phy_device_connect(struct eth_device *edev,
+ struct device_node *phy_np,
+ void (*adjust_link) (struct eth_device *edev),
+ u32 flags, phy_interface_t interface)
+{
+ return -ENOSYS;
+}
+#endif
+
int phy_update_status(struct phy_device *phydev);
int phy_wait_aneg_done(struct phy_device *phydev);