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| author | Rafal Jaworowski <raj@semihalf.com> | 2006-08-11 12:35:52 +0200 |
|---|---|---|
| committer | Rafal Jaworowski <raj@pollux.denx.de> | 2006-08-11 12:35:52 +0200 |
| commit | 36b904a7fdc170a69eb94975b0e506dc2a73fa82 (patch) | |
| tree | f457aa5402f910ecb32fc8e10228a45a025e947c /include | |
| parent | 692519b1edfd5803cd2a841921492889f46f0ce3 (diff) | |
| download | barebox-36b904a7fdc170a69eb94975b0e506dc2a73fa82.tar.gz barebox-36b904a7fdc170a69eb94975b0e506dc2a73fa82.tar.xz | |
Fix PCI-Express on PPC440SPe rev. A.
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/yucca.h | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 9dd9e5eae4..26a330eea7 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -67,8 +67,9 @@ #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE -#define CFG_PCIE_MEMBASE 0xB0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ #define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 #define CFG_PCIE0_XCFGBASE 0xc0000400 @@ -77,13 +78,6 @@ #define CFG_PCIE2_CFGBASE 0xc0002000 #define CFG_PCIE2_XCFGBASE 0xc0002400 -#define CFG_PCIE0_REGBASE 0xc0003000 -#define CFG_PCIE1_REGBASE 0xc0003400 -#define CFG_PCIE2_REGBASE 0xc0004000 -#define CFG_PCIE3_REGBASE 0xc0004400 -#define CFG_PCIE4_REGBASE 0xc0005000 -#define CFG_PCIE5_REGBASE 0xc0005400 - /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE |