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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2020-12-11 13:31:13 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-12-11 13:31:13 +0100 |
| commit | 5530a4248036e3d873aee816e4ce596aa2aff600 (patch) | |
| tree | 6df29a44a3c84a81dc6d5f30d57c586c8140810e /include | |
| parent | 5264daae51117bce522333b3b9a797bbac29edc9 (diff) | |
| parent | eca2a6194514a6decd798c9a235fbb2f3f5258ab (diff) | |
| download | barebox-5530a4248036e3d873aee816e4ce596aa2aff600.tar.gz barebox-5530a4248036e3d873aee816e4ce596aa2aff600.tar.xz | |
Merge branch 'for-next/imx'
Diffstat (limited to 'include')
| -rw-r--r-- | include/mfd/imx6q-iomuxc-gpr.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/mfd/imx6q-iomuxc-gpr.h b/include/mfd/imx6q-iomuxc-gpr.h index b2c9da6579..2e7aa6dc7a 100644 --- a/include/mfd/imx6q-iomuxc-gpr.h +++ b/include/mfd/imx6q-iomuxc-gpr.h @@ -344,4 +344,22 @@ #define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0) #define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0) +/* For imx6ul iomux gpr register field define */ +/* IMX6UL_GPR1_ENET*_CLK_DIR: + * 0 - ENET1_TX_CLK output driver is disabled when configured for ALT1 + * 1 - ENET1_TX_CLK output driver is enabled when configured for ALT1 + */ +#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) +#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) + +/* IMX6UL_GPR1_ENET*_CLK_SEL: + * 0 - ENET TX reference clock driven by ref_enetpll. This clock is also + * output to pins via the IOMUX. ENET_REF_CLK2 function. + * 1 - Gets ENET2 TX reference clk from the ENET2_TX_CLK pin. In this use case, + * an external OSC provides the clock for both the external PHY and the + * internal controller. + */ +#define IMX6UL_GPR1_ENET2_CLK_SEL (0x1 << 14) +#define IMX6UL_GPR1_ENET1_CLK_SEL (0x1 << 13) + #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ |