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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-19 05:41:43 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-01-19 05:41:43 +0100 |
| commit | 83ec121f239b6af42a408ea75930e3733c27c79a (patch) | |
| tree | 9f0de8269e0c450fbac70bf9f0c17aa3ff9ed0ce /include | |
| parent | a0633c4cbc3c06c4e6de0505e02a9585020b3497 (diff) | |
| parent | 94c080861cbaa705646d6dd002da00d945a3b309 (diff) | |
| download | barebox-83ec121f239b6af42a408ea75930e3733c27c79a.tar.gz barebox-83ec121f239b6af42a408ea75930e3733c27c79a.tar.xz | |
Merge branch 'for-next/imx'
Diffstat (limited to 'include')
| -rw-r--r-- | include/soc/imx8m/ddr.h | 4 | ||||
| -rw-r--r-- | include/soc/imx8m/lpddr4_define.h | 7 |
2 files changed, 2 insertions, 9 deletions
diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index a5a6109092..78b15f1d46 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -372,14 +372,14 @@ enum ddrc_type { int imx8mm_ddr_init(struct dram_timing_info *timing_info); int imx8mq_ddr_init(struct dram_timing_info *timing_info); int imx8mp_ddr_init(struct dram_timing_info *timing_info); -int ddr_cfg_phy(struct dram_timing_info *timing_info); +int ddr_cfg_phy(struct dram_timing_info *timing_info, enum ddrc_type type); void load_lpddr4_phy_pie(void); void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); void dram_config_save(struct dram_timing_info *info, unsigned long base); /* utils function for ddr phy training */ int wait_ddrphy_training_complete(void); -void ddrphy_init_set_dfi_clk(unsigned int drate); +void ddrphy_init_set_dfi_clk(unsigned int drate, enum ddrc_type type); void ddrphy_init_read_msg_block(enum fw_type type); void update_umctl2_rank_space_setting(unsigned int pstat_num, diff --git a/include/soc/imx8m/lpddr4_define.h b/include/soc/imx8m/lpddr4_define.h index caf5bafb6d..8053579593 100644 --- a/include/soc/imx8m/lpddr4_define.h +++ b/include/soc/imx8m/lpddr4_define.h @@ -6,13 +6,6 @@ #ifndef __LPDDR4_DEFINE_H_ #define __LPDDR4_DEFINE_H_ -#define LPDDR4_DVFS_DBI -#define DDR_ONE_RANK -/* #define LPDDR4_DBI_ON */ -#define DFI_BUG_WR -#define M845S_4GBx2 -#define PRETRAIN - /* DRAM MR setting */ #ifdef LPDDR4_DBI_ON #define LPDDR4_MR3 0xf1 |