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author | Sascha Hauer <s.hauer@pengutronix.de> | 2021-06-02 11:54:55 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-06-07 12:46:13 +0200 |
commit | 951e8e9cf592db968198957562324c49ab3e0670 (patch) | |
tree | a25bff3444c1b814ae40a8d509c8a30c4546c3cf /include | |
parent | 12fb68e22ee1c13db0c0956db5c606844e1bea7a (diff) | |
download | barebox-951e8e9cf592db968198957562324c49ab3e0670.tar.gz barebox-951e8e9cf592db968198957562324c49ab3e0670.tar.xz |
clk: Update fractional divider from Linux
This updates the fractional divider implementation from Linux-5.12.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.barebox.org/20210602095507.24609-13-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/clk.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/include/linux/clk.h b/include/linux/clk.h index 7140aa9509..39288f5025 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -498,6 +498,46 @@ extern struct clk_ops clk_fixed_factor_ops; struct clk *clk_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div, unsigned flags); + +/** + * struct clk_fractional_divider - adjustable fractional divider clock + * + * @hw: handle between common and hardware-specific interfaces + * @reg: register containing the divider + * @mshift: shift to the numerator bit field + * @mwidth: width of the numerator bit field + * @nshift: shift to the denominator bit field + * @nwidth: width of the denominator bit field + * + * Clock with adjustable fractional divider affecting its output frequency. + * + * Flags: + * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator + * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED + * is set then the numerator and denominator are both the value read + * plus one. + * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are + * used for the divider register. Setting this flag makes the register + * accesses big endian. + */ +struct clk_fractional_divider { + struct clk_hw hw; + void __iomem *reg; + u8 mshift; + u8 mwidth; + u32 mmask; + u8 nshift; + u8 nwidth; + u32 nmask; + u8 flags; + void (*approximation)(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate, + unsigned long *m, unsigned long *n); +}; + +#define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0) +#define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1) + struct clk *clk_fractional_divider_alloc( const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, @@ -508,6 +548,10 @@ struct clk *clk_fractional_divider( u8 clk_divider_flags); void clk_fractional_divider_free(struct clk *clk_fd); +#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) + +extern const struct clk_ops clk_fractional_divider_ops; + struct clk_mux { struct clk_hw hw; void __iomem *reg; |