diff options
| author | Johannes Zink <j.zink@pengutronix.de> | 2022-09-30 14:15:49 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-10-05 09:26:47 +0200 |
| commit | 9d5c18259a3f98ff0dd222e9541db4374451390d (patch) | |
| tree | b13412fcf7f352e96a4a4793024162cdfffd2318 /include | |
| parent | ec87d73af6ee3c3ce515ee5ce02a55b4264b372e (diff) | |
| download | barebox-9d5c18259a3f98ff0dd222e9541db4374451390d.tar.gz barebox-9d5c18259a3f98ff0dd222e9541db4374451390d.tar.xz | |
mtd: nand-mxs: add i.MX7 FCB write support
The FCB on the i.MX7 is written in BCH62 mode and with randomizer
enabled. This needs special FCB read/write functions. Add them to the
driver.
Signed-off-by: Johannes Zink <j.zink@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Johannes Zink <j.zink@pengutronix.de> # innocomm S810
Link: https://lore.barebox.org/20220930121553.335796-4-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mtd/nand_mxs.h | 4 | ||||
| -rw-r--r-- | include/soc/imx/imx-nand-bcb.h | 11 |
2 files changed, 15 insertions, 0 deletions
diff --git a/include/linux/mtd/nand_mxs.h b/include/linux/mtd/nand_mxs.h index 7eda0b8e63..4c1e90d6f0 100644 --- a/include/linux/mtd/nand_mxs.h +++ b/include/linux/mtd/nand_mxs.h @@ -28,5 +28,9 @@ */ int mxs_nand_get_geo(int *ecc_strength, int *bb_mark_bit_offset); +int mxs_nand_read_fcb_bch62(unsigned int block, void *buf, size_t size); +int mxs_nand_write_fcb_bch62(unsigned int block, void *buf, size_t size); + +struct mtd_info; #endif /* __NAND_MXS_H */ diff --git a/include/soc/imx/imx-nand-bcb.h b/include/soc/imx/imx-nand-bcb.h index 6c42d80428..c5481e602e 100644 --- a/include/soc/imx/imx-nand-bcb.h +++ b/include/soc/imx/imx-nand-bcb.h @@ -77,6 +77,17 @@ struct fcb_block { uint32_t DISBBM; /* the flag to enable (1)/disable(0) bi swap */ uint32_t BBMarkerPhysicalOffsetInSpareData; /* The swap position of main area in spare area */ + + /* iMX7 only */ + uint32_t onfi_sync_enable; /* enable Onfi nand sync support */ + uint32_t onfi_sync_speed; /* Speed for Onfi nand sync mode */ + uint32_t onfi_sync_nand_data; /* parameters for Onfi nand sync mode timing */ + uint32_t reserved[6]; + uint32_t disbbm_search; /* disable bad block search function when reading the firmware, only using DBBT */ + uint32_t disbbm_search_limit; /* ???randomizer type 2 enable ???*/ + uint32_t reserved1[15]; /* reserved for future use */ + uint32_t read_retry_enable; /* enable read retry for DBBT and firmware */ + uint32_t reserved2[1]; /*reserved, keep at 0 */ }; #endif /* __MACH_IMX_NAND_BCB_H */ |