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author | Sascha Hauer <s.hauer@pengutronix.de> | 2015-08-06 12:33:06 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2015-08-06 12:33:06 +0200 |
commit | a8525f691dd74f9aa50ecd359408486217e956ba (patch) | |
tree | 13f7fe523b5280803e9eaa5a87cc5e8da425946f /include | |
parent | 3c92473a9e24a55c9e253027178492a788ea7611 (diff) | |
parent | 60427aac464696ebf2125e4eef22f54d960d9bc0 (diff) | |
download | barebox-a8525f691dd74f9aa50ecd359408486217e956ba.tar.gz barebox-a8525f691dd74f9aa50ecd359408486217e956ba.tar.xz |
Merge branch 'for-next/imx'
Diffstat (limited to 'include')
-rw-r--r-- | include/console.h | 6 | ||||
-rw-r--r-- | include/serial/imx-uart.h | 40 | ||||
-rw-r--r-- | include/spi/imx-spi.h | 83 |
3 files changed, 129 insertions, 0 deletions
diff --git a/include/console.h b/include/console.h index 839ec17e50..a6737c8581 100644 --- a/include/console.h +++ b/include/console.h @@ -83,4 +83,10 @@ unsigned console_get_active(struct console_device *cdev); int console_set_baudrate(struct console_device *cdev, unsigned baudrate); unsigned console_get_baudrate(struct console_device *cdev); +#ifdef CONFIG_PBL_CONSOLE +void pbl_set_putc(void (*putcf)(void *ctx, int c), void *ctx); +#else +static inline void pbl_set_putc(void (*putcf)(void *ctx, int c), void *ctx) {} +#endif + #endif diff --git a/include/serial/imx-uart.h b/include/serial/imx-uart.h index 7275e6ac38..d0e5bcc2b8 100644 --- a/include/serial/imx-uart.h +++ b/include/serial/imx-uart.h @@ -125,4 +125,44 @@ static inline int refclock_to_ubmr(int clock_hz) return clock_hz / 1600 - 1; } +static inline void imx_uart_setup(void __iomem *uartbase, + unsigned int refclock) +{ + writel(0x00000000, uartbase + UCR1); + + writel(UCR2_IRTS | UCR2_WS | UCR2_TXEN | UCR2_RXEN | UCR2_SRST, + uartbase + UCR2); + writel(UCR3_DSR | UCR3_DCD | UCR3_RI | UCR3_ADNIMP | UCR3_RXDMUXSEL, + uartbase + UCR3); + writel((0b10 << UFCR_TXTL_SHF) | UFCR_RFDIV1 | (1 << UFCR_RXTL_SHF), + uartbase + UFCR); + + writel(baudrate_to_ubir(CONFIG_BAUDRATE), + uartbase + UBIR); + writel(refclock_to_ubmr(refclock), + uartbase + UBMR); + + writel(UCR1_UARTEN, uartbase + UCR1); +} + +static inline void imx51_uart_setup(void __iomem *uartbase) +{ + imx_uart_setup(uartbase, 54000000); +} + +static inline void imx6_uart_setup(void __iomem *uartbase) +{ + imx_uart_setup(uartbase, 80000000); +} + +static inline void imx_uart_putc(void *base, int c) +{ + if (!(readl(base + UCR1) & UCR1_UARTEN)) + return; + + while (!(readl(base + USR2) & USR2_TXDC)); + + writel(c, base + URTX0); +} + #endif /* __IMX_UART_H__ */ diff --git a/include/spi/imx-spi.h b/include/spi/imx-spi.h new file mode 100644 index 0000000000..560b092bd2 --- /dev/null +++ b/include/spi/imx-spi.h @@ -0,0 +1,83 @@ +#ifndef __SPI_IMX_SPI_H +#define __SPI_IMX_SPI_H + +#define CSPI_0_0_RXDATA 0x00 +#define CSPI_0_0_TXDATA 0x04 +#define CSPI_0_0_CTRL 0x08 +#define CSPI_0_0_INT 0x0C +#define CSPI_0_0_DMA 0x18 +#define CSPI_0_0_STAT 0x0C +#define CSPI_0_0_PERIOD 0x14 +#define CSPI_0_0_TEST 0x10 +#define CSPI_0_0_RESET 0x1C + +#define CSPI_0_0_CTRL_ENABLE (1 << 10) +#define CSPI_0_0_CTRL_MASTER (1 << 11) +#define CSPI_0_0_CTRL_XCH (1 << 9) +#define CSPI_0_0_CTRL_LOWPOL (1 << 5) +#define CSPI_0_0_CTRL_PHA (1 << 6) +#define CSPI_0_0_CTRL_SSCTL (1 << 7) +#define CSPI_0_0_CTRL_HIGHSSPOL (1 << 8) +#define CSPI_0_0_CTRL_CS(x) (((x) & 0x3) << 19) +#define CSPI_0_0_CTRL_BITCOUNT(x) (((x) & 0x1f) << 0) +#define CSPI_0_0_CTRL_DATARATE(x) (((x) & 0x7) << 14) + +#define CSPI_0_0_CTRL_MAXDATRATE 0x10 +#define CSPI_0_0_CTRL_DATAMASK 0x1F +#define CSPI_0_0_CTRL_DATASHIFT 14 + +#define CSPI_0_0_STAT_TE (1 << 0) +#define CSPI_0_0_STAT_TH (1 << 1) +#define CSPI_0_0_STAT_TF (1 << 2) +#define CSPI_0_0_STAT_RR (1 << 4) +#define CSPI_0_0_STAT_RH (1 << 5) +#define CSPI_0_0_STAT_RF (1 << 6) +#define CSPI_0_0_STAT_RO (1 << 7) + +#define CSPI_0_0_PERIOD_32KHZ (1 << 15) + +#define CSPI_0_0_TEST_LBC (1 << 14) + +#define CSPI_0_0_RESET_START (1 << 0) + +#define CSPI_0_7_RXDATA 0x00 +#define CSPI_0_7_TXDATA 0x04 +#define CSPI_0_7_CTRL 0x08 +#define CSPI_0_7_CTRL_ENABLE (1 << 0) +#define CSPI_0_7_CTRL_MASTER (1 << 1) +#define CSPI_0_7_CTRL_XCH (1 << 2) +#define CSPI_0_7_CTRL_POL (1 << 4) +#define CSPI_0_7_CTRL_PHA (1 << 5) +#define CSPI_0_7_CTRL_SSCTL (1 << 6) +#define CSPI_0_7_CTRL_SSPOL (1 << 7) +#define CSPI_0_7_CTRL_CS_SHIFT 12 +#define CSPI_0_7_CTRL_DR_SHIFT 16 +#define CSPI_0_7_CTRL_BL_SHIFT 20 +#define CSPI_0_7_STAT 0x14 +#define CSPI_0_7_STAT_RR (1 << 3) + +#define CSPI_2_3_RXDATA 0x00 +#define CSPI_2_3_TXDATA 0x04 +#define CSPI_2_3_CTRL 0x08 +#define CSPI_2_3_CTRL_ENABLE (1 << 0) +#define CSPI_2_3_CTRL_XCH (1 << 2) +#define CSPI_2_3_CTRL_MODE(cs) (1 << ((cs) + 4)) +#define CSPI_2_3_CTRL_POSTDIV_OFFSET 8 +#define CSPI_2_3_CTRL_PREDIV_OFFSET 12 +#define CSPI_2_3_CTRL_CS(cs) ((cs) << 18) +#define CSPI_2_3_CTRL_BL_OFFSET 20 + +#define CSPI_2_3_CONFIG 0x0c +#define CSPI_2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) +#define CSPI_2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) +#define CSPI_2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) +#define CSPI_2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) + +#define CSPI_2_3_INT 0x10 +#define CSPI_2_3_INT_TEEN (1 << 0) +#define CSPI_2_3_INT_RREN (1 << 3) + +#define CSPI_2_3_STAT 0x18 +#define CSPI_2_3_STAT_RR (1 << 3) + +#endif /* __SPI_IMX_SPI_H */ |