summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/arm/mach-stm32mp/include/mach/bsec.h6
-rw-r--r--arch/arm/mach-stm32mp/include/mach/revision.h18
-rw-r--r--arch/arm/mach-stm32mp/init.c123
-rw-r--r--drivers/mci/stm32_sdmmc2.c18
-rw-r--r--drivers/mfd/stpmic1.c2
-rw-r--r--drivers/nvmem/bsec.c44
-rw-r--r--drivers/regulator/stpmic1_regulator.c2
-rw-r--r--images/.gitignore1
-rw-r--r--include/i2c/i2c.h2
-rw-r--r--scripts/.gitignore1
10 files changed, 184 insertions, 33 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h
index 559faaa..d3cb91b 100644
--- a/arch/arm/mach-stm32mp/include/mach/bsec.h
+++ b/arch/arm/mach-stm32mp/include/mach/bsec.h
@@ -17,7 +17,7 @@ enum bsec_smc {
};
/* Service for BSEC */
-enum bsec_field {
+enum bsec_op {
BSEC_SMC_READ_SHADOW = 1,
BSEC_SMC_PROG_OTP = 2,
BSEC_SMC_WRITE_SHADOW = 3,
@@ -26,13 +26,13 @@ enum bsec_field {
BSEC_SMC_WRITE_ALL = 6,
};
-static inline enum bsec_smc bsec_read_field(enum bsec_field field, unsigned *val)
+static inline enum bsec_smc bsec_read_field(unsigned field, unsigned *val)
{
return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_READ_SHADOW,
field, 0, val);
}
-static inline enum bsec_smc bsec_write_field(enum bsec_field field, unsigned val)
+static inline enum bsec_smc bsec_write_field(unsigned field, unsigned val)
{
return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_WRITE_SHADOW,
field, val, NULL);
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h
index 3872014..2eb4d44 100644
--- a/arch/arm/mach-stm32mp/include/mach/revision.h
+++ b/arch/arm/mach-stm32mp/include/mach/revision.h
@@ -6,17 +6,33 @@
#ifndef __MACH_CPUTYPE_H__
#define __MACH_CPUTYPE_H__
-/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/
+
+/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0)
+ * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI
+ * 153X: 2x Cortex-A7, Cortex-M4, CAN FD
+ * 151X: 1x Cortex-A7, Cortex-M4
+ * XXXA: Cortex-A7 @ 650 MHz
+ * XXXC: Cortex-A7 @ 650 MHz + Secure Boot + HW Crypto
+ * XXXD: Cortex-A7 @ 800 MHz
+ * XXXF: Cortex-A7 @ 800 MHz + Secure Boot + HW Crypto
+ */
#define CPU_STM32MP157Cxx 0x05000000
#define CPU_STM32MP157Axx 0x05000001
#define CPU_STM32MP153Cxx 0x05000024
#define CPU_STM32MP153Axx 0x05000025
#define CPU_STM32MP151Cxx 0x0500002E
#define CPU_STM32MP151Axx 0x0500002F
+#define CPU_STM32MP157Fxx 0x05000080
+#define CPU_STM32MP157Dxx 0x05000081
+#define CPU_STM32MP153Fxx 0x050000A4
+#define CPU_STM32MP153Dxx 0x050000A5
+#define CPU_STM32MP151Fxx 0x050000AE
+#define CPU_STM32MP151Dxx 0x050000AF
/* silicon revisions */
#define CPU_REV_A 0x1000
#define CPU_REV_B 0x2000
+#define CPU_REV_Z 0x2001
int stm32mp_silicon_revision(void);
int stm32mp_cputype(void);
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index 7bad989..7f687fa 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -13,6 +13,7 @@
#include <mach/revision.h>
#include <mach/bootsource.h>
#include <bootsource.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
/* DBGMCU register */
#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
@@ -75,6 +76,9 @@
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
#define TAMP_BOOT_DEBUG_ON BIT(16)
+#define FIXUP_CPU_MASK(num, mhz) (((num) << 16) | (mhz))
+#define FIXUP_CPU_NUM(mask) ((mask) >> 16)
+#define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL)
static enum stm32mp_forced_boot_mode __stm32mp_forced_boot_mode;
enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void)
@@ -155,7 +159,7 @@ static inline u32 read_idc(void)
}
/* Get Device Part Number (RPN) from OTP */
-static u32 get_cpu_rpn(u32 *rpn)
+static int get_cpu_rpn(u32 *rpn)
{
int ret = bsec_read_field(BSEC_OTP_RPN, rpn);
if (ret)
@@ -170,7 +174,7 @@ static u32 get_cpu_revision(void)
return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
}
-static u32 get_cpu_type(u32 *type)
+static int get_cpu_type(u32 *type)
{
u32 id;
int ret = get_cpu_rpn(type);
@@ -192,30 +196,109 @@ static int get_cpu_package(u32 *pkg)
return 0;
}
+static int stm32mp15_fixup_cpus(struct device_node *root, void *_ctx)
+{
+ unsigned long ctx = (unsigned long)_ctx;
+ struct device_node *cpus_node, *np, *tmp;
+
+ cpus_node = of_find_node_by_name(root, "cpus");
+ if (!cpus_node)
+ return 0;
+
+ for_each_child_of_node_safe(cpus_node, tmp, np) {
+ u32 cpu_index;
+
+ if (of_property_read_u32(np, "reg", &cpu_index))
+ continue;
+
+ if (cpu_index >= FIXUP_CPU_NUM(ctx)) {
+ of_delete_node(np);
+ continue;
+ }
+
+ of_property_write_u32(np, "clock-frequency", FIXUP_CPU_HZ(ctx));
+ }
+
+ return 0;
+}
+
+static int fixup_pinctrl(struct device_node *root, const char *compat, u32 pkg)
+{
+ struct device_node *np = of_find_compatible_node(root, NULL, compat);
+ if (!np)
+ return -ENODEV;
+
+ return of_property_write_u32(np, "st,package", pkg);
+}
+
+static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg)
+{
+ unsigned long pkg = (unsigned long)_pkg;
+ int ret;
+
+ ret = fixup_pinctrl(root, "st,stm32mp157-pinctrl", pkg);
+ if (ret)
+ return ret;
+
+ return fixup_pinctrl(root, "st,stm32mp157-z-pinctrl", pkg);
+}
+
static int setup_cpu_type(void)
{
- const char *cputypestr;
- const char *cpupkgstr;
+ const char *cputypestr, *cpupkgstr, *cpurevstr;
+ unsigned long cpufixupctx = 0, pkgfixupctx = 0;
+ u32 pkg;
+ int ret;
get_cpu_type(&__stm32mp_cputype);
switch (__stm32mp_cputype) {
+ case CPU_STM32MP157Fxx:
+ cputypestr = "157F";
+ cpufixupctx = FIXUP_CPU_MASK(2, 800);
+ break;
+ case CPU_STM32MP157Dxx:
+ cputypestr = "157D";
+ cpufixupctx = FIXUP_CPU_MASK(2, 800);
+ break;
case CPU_STM32MP157Cxx:
cputypestr = "157C";
+ cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP157Axx:
cputypestr = "157A";
+ cpufixupctx = FIXUP_CPU_MASK(2, 650);
+ break;
+ case CPU_STM32MP153Fxx:
+ cputypestr = "153F";
+ cpufixupctx = FIXUP_CPU_MASK(2, 800);
+ break;
+ case CPU_STM32MP153Dxx:
+ cputypestr = "153D";
+ cpufixupctx = FIXUP_CPU_MASK(2, 800);
break;
case CPU_STM32MP153Cxx:
cputypestr = "153C";
+ cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP153Axx:
cputypestr = "153A";
+ cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP151Cxx:
cputypestr = "151C";
+ cpufixupctx = FIXUP_CPU_MASK(1, 650);
break;
case CPU_STM32MP151Axx:
cputypestr = "151A";
+ cpufixupctx = FIXUP_CPU_MASK(1, 650);
+ break;
+ case CPU_STM32MP151Fxx:
+ cputypestr = "151F";
+ cpufixupctx = FIXUP_CPU_MASK(1, 800);
+ break;
+ case CPU_STM32MP151Dxx:
+ cputypestr = "151D";
+ cpufixupctx = FIXUP_CPU_MASK(1, 800);
break;
default:
cputypestr = "????";
@@ -226,15 +309,19 @@ static int setup_cpu_type(void)
switch (__stm32mp_package) {
case PKG_AA_LBGA448:
cpupkgstr = "AA";
+ pkgfixupctx = STM32MP_PKG_AA;
break;
case PKG_AB_LBGA354:
cpupkgstr = "AB";
+ pkgfixupctx = STM32MP_PKG_AB;
break;
case PKG_AC_TFBGA361:
cpupkgstr = "AC";
+ pkgfixupctx = STM32MP_PKG_AC;
break;
case PKG_AD_TFBGA257:
cpupkgstr = "AD";
+ pkgfixupctx = STM32MP_PKG_AD;
break;
default:
cpupkgstr = "??";
@@ -242,11 +329,33 @@ static int setup_cpu_type(void)
}
__stm32mp_silicon_revision = get_cpu_revision();
+ switch (__stm32mp_silicon_revision) {
+ case CPU_REV_A:
+ cpurevstr = "A";
+ break;
+ case CPU_REV_B:
+ cpurevstr = "B";
+ break;
+ case CPU_REV_Z:
+ cpurevstr = "Z";
+ break;
+ default:
+ cpurevstr = "?";
+ }
pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n",
- __stm32mp_cputype, __stm32mp_package, __stm32mp_silicon_revision);
- pr_info("detected STM32MP%s%s Rev.%c\n", cputypestr, cpupkgstr,
- (__stm32mp_silicon_revision >> 12) + 'A' - 1);
+ __stm32mp_cputype, pkg, __stm32mp_silicon_revision);
+ pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr);
+
+ if (cpufixupctx) {
+ ret = of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
+ if (ret)
+ return ret;
+ }
+
+ if (pkgfixupctx)
+ return of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx);
+
return 0;
}
diff --git a/drivers/mci/stm32_sdmmc2.c b/drivers/mci/stm32_sdmmc2.c
index 0c26869..3ce3bb0 100644
--- a/drivers/mci/stm32_sdmmc2.c
+++ b/drivers/mci/stm32_sdmmc2.c
@@ -367,7 +367,7 @@ static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
/* Check status */
if (status & SDMMC_STA_CTIMEOUT) {
- dev_err(priv->dev, "%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
+ dev_dbg(priv->dev, "%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
__func__, status, cmd->cmdidx);
return -ETIMEDOUT;
}
@@ -481,11 +481,8 @@ static int stm32_sdmmc2_send_cmd(struct mci_host *mci, struct mci_cmd *cmd,
{
struct stm32_sdmmc2_priv *priv = to_mci_host(mci);
u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
- u32 data_length;
- int ret, retry = 3;
-
-retry_cmd:
- data_length = 0;
+ u32 data_length = 0;
+ int ret;
if (data) {
data_length = data->blocks * data->blocksize;
@@ -530,15 +527,6 @@ retry_cmd:
writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
}
- if (ret && retry) {
- dev_warn(priv->dev, "%s: cmd %d failed, retrying ...\n",
- __func__, cmd->cmdidx);
-
- retry--;
-
- goto retry_cmd;
- }
-
dev_dbg(priv->dev, "%s: end for CMD %d, ret = %d\n", __func__,
cmd->cmdidx, ret);
diff --git a/drivers/mfd/stpmic1.c b/drivers/mfd/stpmic1.c
index ab13ded..d22758b 100644
--- a/drivers/mfd/stpmic1.c
+++ b/drivers/mfd/stpmic1.c
@@ -94,4 +94,4 @@ static struct driver_d stpmic1_i2c_driver = {
.of_compatible = DRV_OF_COMPAT(stpmic1_dt_ids),
};
-device_i2c_driver(stpmic1_i2c_driver);
+coredevice_i2c_driver(stpmic1_i2c_driver);
diff --git a/drivers/nvmem/bsec.c b/drivers/nvmem/bsec.c
index d772d0b..836e62e 100644
--- a/drivers/nvmem/bsec.c
+++ b/drivers/nvmem/bsec.c
@@ -33,7 +33,7 @@ struct stm32_bsec_data {
int num_regs;
};
-static int bsec_smc(struct bsec_priv *priv, u8 op, enum bsec_field field,
+static int bsec_smc(struct bsec_priv *priv, enum bsec_op op, u32 field,
unsigned data2, unsigned *val)
{
enum bsec_smc ret = stm32mp_smc(priv->svc_id, op, field / 4, data2, val);
@@ -77,15 +77,49 @@ static int stm32_bsec_write(struct device_d *dev, int offset,
{
struct bsec_priv *priv = dev->parent->priv;
+ /* Allow only writing complete 32-bits aligned words */
+ if ((bytes % 4) || (offset % 4))
+ return -EINVAL;
+
return regmap_bulk_write(priv->map, offset, val, bytes);
}
static int stm32_bsec_read(struct device_d *dev, int offset,
- void *val, int bytes)
+ void *buf, int bytes)
{
struct bsec_priv *priv = dev->parent->priv;
+ u32 roffset, rbytes, val;
+ u8 *buf8 = buf, *val8 = (u8 *)&val;
+ int i, j = 0, ret, skip_bytes, size;
+
+ /* Round unaligned access to 32-bits */
+ roffset = rounddown(offset, 4);
+ skip_bytes = offset & 0x3;
+ rbytes = roundup(bytes + skip_bytes, 4);
+
+ if (roffset + rbytes > priv->config.size)
+ return -EINVAL;
+
+ for (i = roffset; i < roffset + rbytes; i += 4) {
+ ret = regmap_bulk_read(priv->map, i, &val, 4);
+ if (ret) {
+ dev_err(dev, "Can't read data%d (%d)\n", i, ret);
+ return ret;
+ }
+
+ /* skip first bytes in case of unaligned read */
+ if (skip_bytes)
+ size = min(bytes, 4 - skip_bytes);
+ else
+ size = min(bytes, 4);
+
+ memcpy(&buf8[j], &val8[skip_bytes], size);
+ bytes -= size;
+ j += size;
+ skip_bytes = 0;
+ }
- return regmap_bulk_read(priv->map, offset, val, bytes);
+ return 0;
}
static const struct nvmem_bus stm32_bsec_nvmem_bus = {
@@ -185,8 +219,8 @@ static int stm32_bsec_probe(struct device_d *dev)
priv->config.name = "stm32-bsec";
priv->config.dev = dev;
- priv->config.stride = 4;
- priv->config.word_size = 4;
+ priv->config.stride = 1;
+ priv->config.word_size = 1;
priv->config.size = data->num_regs;
priv->config.bus = &stm32_bsec_nvmem_bus;
dev->priv = priv;
diff --git a/drivers/regulator/stpmic1_regulator.c b/drivers/regulator/stpmic1_regulator.c
index aaaba09..71a4ae8 100644
--- a/drivers/regulator/stpmic1_regulator.c
+++ b/drivers/regulator/stpmic1_regulator.c
@@ -433,4 +433,4 @@ static struct driver_d stpmic1_regulator_driver = {
.probe = stpmic1_regulator_probe,
.of_compatible = DRV_OF_COMPAT(stpmic1_regulator_of_match),
};
-device_platform_driver(stpmic1_regulator_driver);
+coredevice_platform_driver(stpmic1_regulator_driver);
diff --git a/images/.gitignore b/images/.gitignore
index 2f8b87d..377c14c 100644
--- a/images/.gitignore
+++ b/images/.gitignore
@@ -30,3 +30,4 @@ barebox.sum
*.zynqimg
*.image
*.mvebu1img
+*.stm32
diff --git a/include/i2c/i2c.h b/include/i2c/i2c.h
index 56a887a..bfc1eab 100644
--- a/include/i2c/i2c.h
+++ b/include/i2c/i2c.h
@@ -319,6 +319,8 @@ static inline int i2c_driver_register(struct driver_d *drv)
return register_driver(drv);
}
+#define coredevice_i2c_driver(drv) \
+ register_driver_macro(coredevice, i2c, drv)
#define device_i2c_driver(drv) \
register_driver_macro(device, i2c, drv)
diff --git a/scripts/.gitignore b/scripts/.gitignore
index 76ea271..c3ac0b5 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -30,3 +30,4 @@ omap4_usbboot
omap3-usb-loader
mips-relocs
rsatoc
+stm32image