diff options
| -rw-r--r-- | arch/arm/mach-imx/Kconfig | 23 | ||||
| -rw-r--r-- | arch/arm/mach-imx/Makefile | 1 | ||||
| -rw-r--r-- | drivers/nvmem/Kconfig | 21 | ||||
| -rw-r--r-- | drivers/nvmem/Makefile | 3 | ||||
| -rw-r--r-- | drivers/nvmem/ocotp.c (renamed from arch/arm/mach-imx/ocotp.c) | 0 |
5 files changed, 26 insertions, 22 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index e6956acbdb..09530e56f5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -179,6 +179,7 @@ config ARCH_VF610 select OFTREE select COMMON_CLK select COMMON_CLK_OF_PROVIDER + select NVMEM select IMX_OCOTP # Needed for clock adjustement config IMX_MULTI_BOARDS @@ -725,33 +726,13 @@ config IMX_IIM_FUSE_BLOW enable it: imx_iim0.permanent_write_enable=1 -config IMX_OCOTP - tristate "i.MX6 On Chip OTP controller" - depends on ARCH_IMX6 || ARCH_VF610 - depends on OFDEVICE - help - This adds support for the i.MX6 On-Chip OTP controller. Currently the - only supported functionality is reading the MAC address and assigning - it to an ethernet device. - -config IMX_OCOTP_WRITE - bool - prompt "Enable write support of i.MX6 CPUs OTP fuses" - depends on IMX_OCOTP - help - This adds write support to IMX6 On-Chip OTP registers. Example of set - MAC to 12:34:56:78:9A:BC (2 words with address 0x22 (OCOTP_MAC0) and - address 0x23 (OCOTP_MAC1)). To calculate the file offset multiply - the value of the address by 4. - mw -l -d /dev/imx-ocotp 0x8C 0x00001234 - mw -l -d /dev/imx-ocotp 0x88 0x56789ABC - config HAB bool config HABV4 tristate "HABv4 support" select HAB + select NVMEM select IMX_OCOTP depends on ARCH_IMX6 depends on OFDEVICE diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 160ed4b084..969f5347bf 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_ARCH_IMX7) += imx7.o obj-$(CONFIG_ARCH_VF610) += vf610.o obj-$(CONFIG_ARCH_IMX_XLOAD) += xload.o obj-$(CONFIG_IMX_IIM) += iim.o -obj-$(CONFIG_IMX_OCOTP) += ocotp.o obj-$(CONFIG_NAND_IMX) += nand.o lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o obj-y += devices.o imx.o diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index d801cc25af..53086d1aac 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -15,4 +15,25 @@ config NVMEM_SNVS_LPGPR help If you say yes here you get NVMEM support for the Freescale SNVS Low Power Generic Purpose Register (LPGPR). + +config IMX_OCOTP + tristate "i.MX6 On Chip OTP controller" + depends on ARCH_IMX6 || ARCH_VF610 + depends on OFDEVICE + help + This adds support for the i.MX6 On-Chip OTP controller. Currently the + only supported functionality is reading the MAC address and assigning + it to an ethernet device. + +config IMX_OCOTP_WRITE + bool + prompt "Enable write support of i.MX6 CPUs OTP fuses" + depends on IMX_OCOTP + help + This adds write support to IMX6 On-Chip OTP registers. Example of set + MAC to 12:34:56:78:9A:BC (2 words with address 0x22 (OCOTP_MAC0) and + address 0x23 (OCOTP_MAC1)). To calculate the file offset multiply + the value of the address by 4. + mw -l -d /dev/imx-ocotp 0x8C 0x00001234 + mw -l -d /dev/imx-ocotp 0x88 0x56789ABC endif diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 32522e9fbf..998a9c4b9a 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -8,3 +8,6 @@ nvmem_core-y := core.o # Devices obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o nvmem_snvs_lpgpr-y := snvs_lpgpr.o + +obj-$(CONFIG_IMX_OCOTP) += nvmem_ocotp.o +nvmem_ocotp-y := ocotp.o
\ No newline at end of file diff --git a/arch/arm/mach-imx/ocotp.c b/drivers/nvmem/ocotp.c index 8c44bbb16e..8c44bbb16e 100644 --- a/arch/arm/mach-imx/ocotp.c +++ b/drivers/nvmem/ocotp.c |