diff options
21 files changed, 1531 insertions, 351 deletions
diff --git a/Documentation/boards/socfpga.rst b/Documentation/boards/socfpga.rst new file mode 100644 index 0000000000..93831c5f29 --- /dev/null +++ b/Documentation/boards/socfpga.rst @@ -0,0 +1,80 @@ +Altera SoCFPGA +============== + +Alteras SoCFPGA SoCs have a two-stage boot process. The first stage is +known as preloader which loads the second stage bootloader. barebox can act +as both the first and the second stage loader. +In barebox the preloader is called xload, so to build as a first stage loader, +build the ``socfpga-xload_defconfig``; for second stage use the normal +``socfpga_defconfig``. + +Bootstrapping +------------- + +The supported bootsource is a SD card. The Boot ROM searches for a partition of +type A2 and loads what it finds there. When barebox is placed in such a partition +it will then itself try and mount the second partition of the SD card, which must +be of type FAT32. On this partition barebox searches for a file called barebox.bin. + +To boot barebox on a Terasic SoCkit, the procedure is as follows (sdb1 is the A2 and +sdb2 the FAT32 partition):: + + mount -t fat /dev/sdb2 /mnt + make socfpga-xload_defconfig + make + make socfpga_defconfig + make + +barebox has now generated multiple files in the images directory. So for the SoCkit +proceed with:: + + cat images/barebox-socfpga-sockit-xload.img > /dev/sdb1 + cp images/barebox-socfpga-sockit.img /mnt/barebox.bin + umount /mnt + +For the EBV Socrates use ``images/barebox-socfpga-socrates(-xload).img`` instead. + +Updating handoff files +---------------------- + +(Tools needed: Quartus II + SoCEDS) + +As barebox uses some of the autogenerated files from Quartus II, every +time Altera makes a new release, there might be some updates to the +handoff files. As these files are split up in the code base and generated +explicitely for some specific U-boot code base, some manual work might be +necessary. + +The following files are generic and belong into the +`arch/arm/mach-socfpga` directory tree: + +* sequencer.c (Not for the faint of heart.) +* sequencer.h +* system.h + +It should normally not be necessary to touch these if barebox is up-to-date. + +The boardspecific files for `arch/arm/boards/<yourboard>` are: + +* iocsr_config_cyclone5.c +* pinmux_config_cyclone5.c -> pinmux_config.c +* pll_config.h +* sdram/sdram_config.h -> sdram_config.h +* sequencer_auto.h +* sequencer_auto_ac_init.c +* sequencer_auto_inst_init.c +* sequencer_defines.h + +To update the handoff files, the following procedure is necessary:: + + 1. Regenerate the project with Qsys + 2. Load up your project in Quartus II and assemble the design + 3. Go to the SoCEDS installation and run + ``./embedded_command_shell.sh`` + 4. Now run ``bsp-editor`` + 5. Create a new BSP + 6. Select the directory `hps_isw_handoff/soc_system_hps_0` under the + preloader settings directory + 7. Click ``Ok`` than ``Generate`` + 8. Copy the files generated in `software/spl_bsp/generated/` to your + board folder diff --git a/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c new file mode 100644 index 0000000000..ab6733f92b --- /dev/null +++ b/arch/arm/boards/ebv-socrates/iocsr_config_cyclone5.c @@ -0,0 +1,675 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <mach/scan-manager.h> + +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { + 0x000C0300, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00001806, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C0300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x18000100, + 0x00018060, + 0x00018060, + 0x00004000, + 0x200700C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x10018060, + 0x06018000, + 0x06000000, + 0x00010038, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { + 0x0CC20D80, + 0x0C3000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x45034030, + 0x12481A01, + 0x80A280D0, + 0x34030C06, + 0x01A01450, + 0x280D0000, + 0x30C0680A, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0x20430000, + 0x0C003001, + 0x00C00481, + 0x00000FF0, + 0x4810C000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x90218000, + 0x86001800, + 0x00600240, + 0x80090218, + 0x24086001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x4810C000, + 0x43000C00, + 0x00300120, + 0xC004810C, + 0x12043000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD00A281A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x18000000, + 0x01800902, + 0x00240860, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF228A3D5, + 0xF6D1451E, + 0x0342E388, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD949247A, + 0x1EF228A3, + 0x88F6D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x86120800, + 0x00600240, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF3CF23D5, + 0xF4D1451E, + 0x034A9248, + 0x821A038E, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF3CF23, + 0x88F4D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x2043090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F36080, + 0x1A041404, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xF228A3D9, + 0xF4D1451E, + 0x034A9248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF228A3, + 0x88F4D145, + 0x000352E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0x7FFFFFFF, + 0x14F16080, + 0x1A041404, + 0x00D00000, + 0x08864000, + 0x49247A02, + 0xF3CF23D9, + 0xF4D1451E, + 0x0342E388, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD949247A, + 0x1EF3CF23, + 0x88F4DE79, + 0x000342A2, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c index 9c11543209..7fc81678ef 100644 --- a/arch/arm/boards/ebv-socrates/lowlevel.c +++ b/arch/arm/boards/ebv-socrates/lowlevel.c @@ -16,6 +16,7 @@ #include <mach/sequencer.c> #include "sequencer_auto_inst_init.c" #include "sequencer_auto_ac_init.c" +#include "iocsr_config_cyclone5.c" static inline void ledon(void) { @@ -58,6 +59,7 @@ ENTRY_FUNCTION(start_socfpga_socrates, r0, r1, r2) static noinline void socrates_entry(void) { + struct socfpga_io_config io_config; int ret; arm_early_mmu_cache_invalidate(); @@ -65,8 +67,14 @@ static noinline void socrates_entry(void) relocate_to_current_adr(); setup_c(); - socfpga_lowlevel_init(&cm_default_cfg, - sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table)); + io_config.pinmux = sys_mgr_init_table; + io_config.num_pin = ARRAY_SIZE(sys_mgr_init_table); + io_config.iocsr_emac_mixed2 = iocsr_scan_chain0_table; + io_config.iocsr_mixed1_flash = iocsr_scan_chain1_table; + io_config.iocsr_general = iocsr_scan_chain2_table; + io_config.iocsr_ddr = iocsr_scan_chain3_table; + + socfpga_lowlevel_init(&cm_default_cfg, &io_config); puts_ll("lowlevel init done\n"); puts_ll("SDRAM setup...\n"); diff --git a/arch/arm/boards/ebv-socrates/pinmux_config.c b/arch/arm/boards/ebv-socrates/pinmux_config.c index e259078410..faa3122466 100644 --- a/arch/arm/boards/ebv-socrates/pinmux_config.c +++ b/arch/arm/boards/ebv-socrates/pinmux_config.c @@ -1,3 +1,34 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <common.h> + /* pin MUX configuration data */ static unsigned long sys_mgr_init_table[] = { 0, /* EMACIO0 */ @@ -207,4 +238,4 @@ static unsigned long sys_mgr_init_table[] = { 0, /* SPIM1USEFPGA */ 0, /* USB0USEFPGA */ 0 /* SPIM0USEFPGA */ -}; +};
\ No newline at end of file diff --git a/arch/arm/boards/ebv-socrates/pll_config.h b/arch/arm/boards/ebv-socrates/pll_config.h index 7682f6302d..083ebd4a87 100644 --- a/arch/arm/boards/ebv-socrates/pll_config.h +++ b/arch/arm/boards/ebv-socrates/pll_config.h @@ -1,97 +1,113 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef _PRELOADER_PLL_CONFIG_H_ #define _PRELOADER_PLL_CONFIG_H_ -/* PLL configuration data */ -/* Main PLL */ -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) -/* - * To tell where is the clock source: - * 0 = MAINPLL - * 1 = PERIPHPLL - */ -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) +#define CONFIG_HPS_DBCTRL_STAYOSC1 (1) -/* Peripheral PLL */ -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) -/* - * To tell where is the VCOs source: - * 0 = EOSC1 - * 1 = EOSC2 - * 2 = F2S - */ -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (19) -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) -/* - * To tell where is the clock source: - * 0 = F2S_PERIPH_REF_CLK - * 1 = MAIN_CLK - * 2 = PERIPH_CLK - */ -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (1) -#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) -/* SDRAM PLL */ -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79) -/* - * To tell where is the VCOs source: - * 0 = EOSC1 - * 1 = EOSC2 - * 2 = F2S - */ -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79) +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666) +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_EMAC0_HZ (1953125) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (400000000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (100000000) +#define CONFIG_HPS_CLK_CAN1_HZ (12500000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) -/* Info for driver */ -#define CONFIG_HPS_CLK_OSC1_HZ (25000000) -#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) -#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) -#define CONFIG_HPS_CLK_SDRVCO_HZ (600000000) -#define CONFIG_HPS_CLK_EMAC0_HZ (50000000) -#define CONFIG_HPS_CLK_EMAC1_HZ (50000000) -#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) -#define CONFIG_HPS_CLK_NAND_HZ (100000000) -#define CONFIG_HPS_CLK_SDMMC_HZ (50000000) -#define CONFIG_HPS_CLK_QSPI_HZ (400000000) -#define CONFIG_HPS_CLK_SPIM_HZ (200000000) -#define CONFIG_HPS_CLK_CAN0_HZ (100000000) -#define CONFIG_HPS_CLK_CAN1_HZ (100000000) -#define CONFIG_HPS_CLK_GPIODB_HZ (32000) -#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) -#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) +#define CONFIG_HPS_ALTERAGRP_MPUCLK (1) +#define CONFIG_HPS_ALTERAGRP_MAINCLK (3) +#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3) #endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/arch/arm/boards/ebv-socrates/sdram_config.h b/arch/arm/boards/ebv-socrates/sdram_config.h index 94d1cbe470..16dd783bf0 100644 --- a/arch/arm/boards/ebv-socrates/sdram_config.h +++ b/arch/arm/boards/ebv-socrates/sdram_config.h @@ -1,3 +1,32 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef __SDRAM_CONFIG_H #define __SDRAM_CONFIG_H @@ -26,9 +55,10 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (17) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4) -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (200) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (512) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3) #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES (8) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3) @@ -36,6 +66,7 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32) #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8) #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK (3) #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2) #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0) #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2) @@ -61,13 +92,17 @@ #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x80808080) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x80808080) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x8080) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ +(0x0101) #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0) -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0x0) +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST (0x0) #endif /*#ifndef__SDRAM_CONFIG_H*/ diff --git a/arch/arm/mach-socfpga/iocsr-config-cyclone5.c b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c index 44238b3b3e..117d7f4ebc 100644 --- a/arch/arm/mach-socfpga/iocsr-config-cyclone5.c +++ b/arch/arm/boards/terasic-sockit/iocsr_config_cyclone5.c @@ -1,9 +1,35 @@ -/* This file is generated by Preloader Generator */ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ -#include <common.h> #include <mach/scan-manager.h> -const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { 0x00000000, 0x00000000, 0x0FF00000, @@ -30,7 +56,7 @@ const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 0x00001000, }; -const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { 0x00100000, 0x300C0000, 0x300000C0, @@ -87,7 +113,7 @@ const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 0x00000080, }; -const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { 0x300C0300, 0x00000000, 0x0FF00000, @@ -120,9 +146,9 @@ const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 0x00000800, }; -const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { +static const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { 0x0C420D80, - 0x882000FF, + 0x082000FF, 0x0A804001, 0x07900000, 0x08020000, diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c index 5b3b89a924..0683435a7b 100644 --- a/arch/arm/boards/terasic-sockit/lowlevel.c +++ b/arch/arm/boards/terasic-sockit/lowlevel.c @@ -16,6 +16,7 @@ #include <mach/sequencer.c> #include "sequencer_auto_inst_init.c" #include "sequencer_auto_ac_init.c" +#include "iocsr_config_cyclone5.c" static inline void ledon(int led) { @@ -58,6 +59,7 @@ ENTRY_FUNCTION(start_socfpga_sockit, r0, r1, r2) static noinline void sockit_entry(void) { + struct socfpga_io_config io_config; int ret; arm_early_mmu_cache_invalidate(); @@ -65,8 +67,14 @@ static noinline void sockit_entry(void) relocate_to_current_adr(); setup_c(); - socfpga_lowlevel_init(&cm_default_cfg, - sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table)); + io_config.pinmux = sys_mgr_init_table; + io_config.num_pin = ARRAY_SIZE(sys_mgr_init_table); + io_config.iocsr_emac_mixed2 = iocsr_scan_chain0_table; + io_config.iocsr_mixed1_flash = iocsr_scan_chain1_table; + io_config.iocsr_general = iocsr_scan_chain2_table; + io_config.iocsr_ddr = iocsr_scan_chain3_table; + + socfpga_lowlevel_init(&cm_default_cfg, &io_config); puts_ll("lowlevel init done\n"); puts_ll("SDRAM setup...\n"); diff --git a/arch/arm/boards/terasic-sockit/pinmux_config.c b/arch/arm/boards/terasic-sockit/pinmux_config.c index 554fbd8fef..3a7cd2bc62 100644 --- a/arch/arm/boards/terasic-sockit/pinmux_config.c +++ b/arch/arm/boards/terasic-sockit/pinmux_config.c @@ -1,3 +1,32 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #include <common.h> unsigned long sys_mgr_init_table[] = { diff --git a/arch/arm/boards/terasic-sockit/pll_config.h b/arch/arm/boards/terasic-sockit/pll_config.h index 672ce41fb7..e064e2b2b2 100644 --- a/arch/arm/boards/terasic-sockit/pll_config.h +++ b/arch/arm/boards/terasic-sockit/pll_config.h @@ -1,98 +1,113 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #ifndef _PRELOADER_PLL_CONFIG_H_ #define _PRELOADER_PLL_CONFIG_H_ -/* PLL configuration data */ -/* Main PLL */ -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) -/* - * To tell where is the clock source: - * 0 = MAINPLL - * 1 = PERIPHPLL - */ -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) +#define CONFIG_HPS_DBCTRL_STAYOSC1 (1) -/* Peripheral PLL */ -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) -/* - * To tell where is the VCOs source: - * 0 = EOSC1 - * 1 = EOSC2 - * 2 = F2S - */ -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (19) -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) -/* - * To tell where is the clock source: - * 0 = F2S_PERIPH_REF_CLK - * 1 = MAIN_CLK - * 2 = PERIPH_CLK - */ -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) -#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) -/* SDRAM PLL */ -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) -/* - * To tell where is the VCOs source: - * 0 = EOSC1 - * 1 = EOSC2 - * 2 = F2S - */ -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39) +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4) +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4) +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) +#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) + +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) +#define CONFIG_HPS_CLK_OSC1_HZ (25000000) +#define CONFIG_HPS_CLK_OSC2_HZ (25000000) +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0) +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0) +#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) +#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) +#define CONFIG_HPS_CLK_EMAC0_HZ (1953125) +#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) +#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) +#define CONFIG_HPS_CLK_NAND_HZ (50000000) +#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) +#define CONFIG_HPS_CLK_QSPI_HZ (400000000) +#define CONFIG_HPS_CLK_SPIM_HZ (200000000) +#define CONFIG_HPS_CLK_CAN0_HZ (12500000) +#define CONFIG_HPS_CLK_CAN1_HZ (12500000) +#define CONFIG_HPS_CLK_GPIODB_HZ (32000) +#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) +#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) -/* Info for driver */ -#define CONFIG_HPS_CLK_OSC1_HZ (25000000) -#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) -#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) -#define CONFIG_HPS_CLK_SDRVCO_HZ (600000000) -#define CONFIG_HPS_CLK_EMAC0_HZ (50000000) -#define CONFIG_HPS_CLK_EMAC1_HZ (50000000) -#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) -#define CONFIG_HPS_CLK_NAND_HZ (100000000) -#define CONFIG_HPS_CLK_SDMMC_HZ (50000000) -#define CONFIG_HPS_CLK_QSPI_HZ (400000000) -#define CONFIG_HPS_CLK_SPIM_HZ (200000000) -#define CONFIG_HPS_CLK_CAN0_HZ (100000000) -#define CONFIG_HPS_CLK_CAN1_HZ (100000000) -#define CONFIG_HPS_CLK_GPIODB_HZ (32000) -#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) -#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) +#define CONFIG_HPS_ALTERAGRP_MPUCLK (1) +#define CONFIG_HPS_ALTERAGRP_MAINCLK (3) +#define CONFIG_HPS_ALTERAGRP_DBGATCLK (3) #endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/arch/arm/boards/terasic-sockit/sdram_config.h b/arch/arm/boards/terasic-sockit/sdram_config.h index 2c04b02599..875d5fe0e7 100644 --- a/arch/arm/boards/terasic-sockit/sdram_config.h +++ b/arch/arm/boards/terasic-sockit/sdram_config.h @@ -1,3 +1,32 @@ +/* GENERATED FILE - DO NOT EDIT */ +/* + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef __SDRAM_CONFIG_H #define __SDRAM_CONFIG_H @@ -26,9 +55,10 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (20) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4) -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (200) +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (512) #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3) #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES (8) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15) #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3) @@ -36,6 +66,7 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32) #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8) #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0) +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK (3) #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2) #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0) #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2) @@ -61,9 +92,12 @@ #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041) #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x01010101) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x01010101) -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x0101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ +(0x01010101) +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ +(0x0101) #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0) #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1) #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0x0) diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto.h b/arch/arm/boards/terasic-sockit/sequencer_auto.h index 492706f7a3..ac6d28297d 100644 --- a/arch/arm/boards/terasic-sockit/sequencer_auto.h +++ b/arch/arm/boards/terasic-sockit/sequencer_auto.h @@ -1,3 +1,31 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ #define __RW_MGR_ac_mrs1 0x04 #define __RW_MGR_ac_mrs3 0x06 #define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C @@ -71,56 +99,83 @@ #define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000 #define __RW_MGR_CONTENT_ac_mrs2 0x100A0218 -#define __RW_MGR_READ_B2B_WAIT2 0x6A -#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31 +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#define __RW_MGR_READ_B2B_WAIT2 0x6B +#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 #define __RW_MGR_REFRESH_ALL 0x14 #define __RW_MGR_ZQCL 0x06 -#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22 -#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23 +#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 #define __RW_MGR_ACTIVATE_0_AND_1 0x0D #define __RW_MGR_MRS2_MIRR 0x0A -#define __RW_MGR_INIT_RESET_0_CKE_0 0x6E -#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45 +#define __RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 #define __RW_MGR_ACTIVATE_1 0x0F #define __RW_MGR_MRS2 0x04 -#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 #define __RW_MGR_MRS1 0x03 -#define __RW_MGR_IDLE_LOOP1 0x7C -#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x18 +#define __RW_MGR_IDLE_LOOP1 0x7B +#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 #define __RW_MGR_MRS3 0x05 -#define __RW_MGR_IDLE_LOOP2 0x7B -#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E -#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24 -#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C -#define __RW_MGR_RDIMM_CMD 0x7A -#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36 -#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A -#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38 -#define __RW_MGR_GUARANTEED_READ_CONT 0x53 +#define __RW_MGR_IDLE_LOOP2 0x7A +#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define __RW_MGR_RDIMM_CMD 0x79 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define __RW_MGR_GUARANTEED_READ_CONT 0x54 +#define __RW_MGR_REFRESH_DELAY 0x15 #define __RW_MGR_MRS3_MIRR 0x0B #define __RW_MGR_IDLE 0x00 -#define __RW_MGR_READ_B2B 0x58 -#define __RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F -#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37 -#define __RW_MGR_GUARANTEED_WRITE 0x17 +#define __RW_MGR_READ_B2B 0x59 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define __RW_MGR_GUARANTEED_WRITE 0x18 #define __RW_MGR_PRECHARGE_ALL 0x12 -#define __RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74 -#define __RW_MGR_SGLE_READ 0x7E +#define __RW_MGR_SGLE_READ 0x7D #define __RW_MGR_MRS0_USER_MIRR 0x0C #define __RW_MGR_RETURN 0x01 -#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35 +#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 #define __RW_MGR_MRS0_USER 0x07 -#define __RW_MGR_GUARANTEED_READ 0x4B +#define __RW_MGR_GUARANTEED_READ 0x4C #define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08 -#define __RW_MGR_INIT_RESET_1_CKE_0 0x73 +#define __RW_MGR_INIT_RESET_1_CKE_0 0x74 #define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 -#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20 +#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 #define __RW_MGR_MRS0_DLL_RESET 0x02 #define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E -#define __RW_MGR_LFSR_WR_RD_BANK_0 0x21 -#define __RW_MGR_CLEAR_DQS_ENABLE 0x48 +#define __RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define __RW_MGR_CLEAR_DQS_ENABLE 0x49 #define __RW_MGR_MRS1_MIRR 0x09 -#define __RW_MGR_READ_B2B_WAIT1 0x60 +#define __RW_MGR_READ_B2B_WAIT1 0x61 #define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 #define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 #define __RW_MGR_CONTENT_REFRESH_ALL 0x000980 @@ -147,14 +202,13 @@ #define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 #define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 #define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 +#define __RW_MGR_CONTENT_REFRESH_DELAY 0x00A680 #define __RW_MGR_CONTENT_MRS3_MIRR 0x008600 #define __RW_MGR_CONTENT_IDLE 0x080000 #define __RW_MGR_CONTENT_READ_B2B 0x040E88 -#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000 #define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 #define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 #define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 -#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080 #define __RW_MGR_CONTENT_SGLE_READ 0x040F08 #define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 #define __RW_MGR_CONTENT_RETURN 0x080680 @@ -171,3 +225,4 @@ #define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 #define __RW_MGR_CONTENT_MRS1_MIRR 0x008500 #define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 + diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c index 5b0c3f351d..fe0764b0ce 100644 --- a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c +++ b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c @@ -1,3 +1,32 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + static const uint32_t ac_rom_init_size = 36; static const uint32_t ac_rom_init[36] = { diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c index 7815faa939..fc83721ea2 100644 --- a/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c +++ b/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c @@ -1,7 +1,35 @@ -#include <common.h> +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ -const uint32_t inst_rom_init_size = 128; -const uint32_t inst_rom_init[128] = +#include <common.h> +const uint32_t inst_rom_init_size = 127; +const uint32_t inst_rom_init[127] = { 0x80000, 0x80680, @@ -24,6 +52,7 @@ const uint32_t inst_rom_init[128] = 0x900, 0x80680, 0x980, + 0xa680, 0x8680, 0x80680, 0xb68, @@ -114,16 +143,14 @@ const uint32_t inst_rom_init[128] = 0xe680, 0x80680, 0x0, - 0x0, - 0xa000, 0x8000, + 0xa000, + 0xc000, 0x80000, 0x80, - 0x80, - 0x80, - 0x80, - 0xa080, 0x8080, + 0xa080, + 0xc080, 0x80080, 0x9180, 0x8680, diff --git a/arch/arm/boards/terasic-sockit/sequencer_defines.h b/arch/arm/boards/terasic-sockit/sequencer_defines.h index a3cd7a87d7..f4d43951c8 100644 --- a/arch/arm/boards/terasic-sockit/sequencer_defines.h +++ b/arch/arm/boards/terasic-sockit/sequencer_defines.h @@ -1,3 +1,31 @@ +/* +Copyright (c) 2012, Altera Corporation +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Altera Corporation nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ #ifndef _SEQUENCER_DEFINES_H_ #define _SEQUENCER_DEFINES_H_ @@ -30,6 +58,7 @@ #define DM_PINS_ENABLED 1 #define ENABLE_ASSERT 0 #define ENABLE_BRINGUP_DEBUGGING 0 +#define ENABLE_DELAY_CHAIN_WRITE 0 #define ENABLE_DQS_IN_CENTERING 1 #define ENABLE_DQS_OUT_CENTERING 0 #define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 @@ -38,6 +67,7 @@ #define ENABLE_NON_DESTRUCTIVE_CALIB 0 #define ENABLE_SUPER_QUICK_CALIBRATION 0 #define ENABLE_TCL_DEBUG 0 +#define FAKE_CAL_FAIL 0 #define FULL_RATE 1 #define GUARANTEED_READ_BRINGUP_TEST 0 #define HALF_RATE 0 @@ -69,9 +99,13 @@ #define LPDDR1 0 #define LPDDR2 0 #define LRDIMM 0 +#define M10_DQ_WIDTH_8 0 +#define M10_DQ_WIDTH_16 0 +#define M10_DQ_WIDTH_24 0 #define MARGIN_VARIATION_TEST 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define MEM_ADDR_WIDTH 13 +#define MRS_MIRROR_PING_PONG_ATSO 0 #define MULTIPLE_AFI_WLAT 0 #define NUM_SHADOW_REGS 1 #define QDRII 0 @@ -79,7 +113,7 @@ #define RDIMM 0 #define READ_AFTER_WRITE_CALIBRATION 1 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c #define RLDRAM3 0 #define RLDRAMII 0 #define RLDRAMX 0 @@ -110,9 +144,17 @@ #define STATIC_SIM_FILESET 0 #define STATIC_SKIP_MEM_INIT 0 #define STRATIXV 0 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TINIT_CNTR0_VAL 99 #define TRACKING_ERROR_TEST 0 #define TRACKING_WATCH_TEST 0 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 +#define TRESET_CNTR0_VAL 99 +#define TW0_CAPTURE_CLOCKS 0 #define USE_DQS_TRACKING 1 #define USE_SHADOW_REGS 0 +#define USE_USER_RDIMM_VALUE 0 #endif /* _SEQUENCER_DEFINES_H_ */ diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 12585c5476..b81d57da26 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -1,5 +1,5 @@ obj-y += generic.o nic301.o bootsource.o reset-manager.o pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o -pbl-y += clock-manager.o iocsr-config-cyclone5.o +pbl-y += clock-manager.o obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o obj-$(CONFIG_ARCH_SOCFPGA_FPGA) += fpga.o diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h index cb7f8e6928..2f5cda0d02 100644 --- a/arch/arm/mach-socfpga/include/mach/generic.h +++ b/arch/arm/mach-socfpga/include/mach/generic.h @@ -3,8 +3,10 @@ struct socfpga_cm_config; +struct socfpga_io_config; + void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config, - unsigned long *pinmux, int num_pinmux); + struct socfpga_io_config *io_config); static inline void __udelay(unsigned us) { diff --git a/arch/arm/mach-socfpga/include/mach/scan-manager.h b/arch/arm/mach-socfpga/include/mach/scan-manager.h index e815e2f33b..568bedfde1 100644 --- a/arch/arm/mach-socfpga/include/mach/scan-manager.h +++ b/arch/arm/mach-socfpga/include/mach/scan-manager.h @@ -119,13 +119,13 @@ int scan_mgr_io_scan_chain_prg(enum io_scan_chain io_scan_chain_id, uint32_t io_scan_chain_len_in_bits, const unsigned long *iocsr_scan_chain); -extern const unsigned long iocsr_scan_chain0_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; -extern const unsigned long iocsr_scan_chain1_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; -extern const unsigned long iocsr_scan_chain2_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; -extern const unsigned long iocsr_scan_chain3_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; +struct socfpga_io_config { + unsigned long *pinmux; + unsigned int num_pin; + const unsigned long *iocsr_emac_mixed2; + const unsigned long *iocsr_mixed1_flash; + const unsigned long *iocsr_general; + const unsigned long *iocsr_ddr; +}; #endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.c b/arch/arm/mach-socfpga/include/mach/sequencer.c index 6e69d1becc..87dc6677ec 100644 --- a/arch/arm/mach-socfpga/include/mach/sequencer.c +++ b/arch/arm/mach-socfpga/include/mach/sequencer.c @@ -1,29 +1,30 @@ /* -Copyright (c) 2012, Altera Corporation -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of Altera Corporation nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #include <common.h> #include <io.h> @@ -1160,32 +1161,29 @@ static void rw_mgr_mem_initialize (void) /* start with memory RESET activated */ - /* tINIT = 200us */ - - /* - * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles - * If a and b are the number of iteration in 2 nested loops - * it takes the following number of cycles to complete the operation: - * number_of_cycles = ((2 + n) * a + 2) * b - * where n is the number of instruction in the inner loop - * One possible solution is n = 0 , a = 256 , b = 106 => a = FF, - * b = 6A + /* tINIT is typically 200us (but can be adjusted in the GUI) + * The total number of cycles required for this nested counter structure to + * complete is defined by: + * num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1 */ /* Load counters */ IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, - SKIP_DELAY_LOOP_VALUE_OR_ZERO(0xFF)); + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL)); IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, - SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x6A)); + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL)); + IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL)); /* Load jump address */ IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_0_CKE_0); IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, - __RW_MGR_INIT_RESET_0_CKE_0_inloop); + __RW_MGR_INIT_RESET_0_CKE_0); + IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, + __RW_MGR_INIT_RESET_0_CKE_0); /* Execute count instruction */ - /* IOWR_32DIRECT(BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0); */ IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_0_CKE_0); /* indicate that memory is stable */ @@ -1194,26 +1192,21 @@ static void rw_mgr_mem_initialize (void) /* transition the RESET to high */ /* Wait for 500us */ - /* - * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles - * If a and b are the number of iteration in 2 nested loops - * it takes the following number of cycles to complete the operation - * number_of_cycles = ((2 + n) * a + 2) * b - * where n is the number of instruction in the inner loop - * One possible solution is n = 2 , a = 131 , b = 256 => a = 83, - * b = FF - */ + /* num_cycles = (CTR2 + 1) * [(CTR1 + 1) * (2 * (CTR0 + 1) + 1) + 1] + 1 */ /* Load counters */ IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, - SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x83)); + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL)); IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, - SKIP_DELAY_LOOP_VALUE_OR_ZERO(0xFF)); + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL)); + IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL)); /* Load jump address */ IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_RESET_1_CKE_0); - IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, - __RW_MGR_INIT_RESET_1_CKE_0_inloop_1); + IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_RESET_1_CKE_0); + IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_RESET_1_CKE_0); + IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_RESET_1_CKE_0); @@ -1305,27 +1298,28 @@ static void rw_mgr_mem_initialize (void) /* tINIT = 200us */ - /* 200us @ 300MHz (3.33 ns) ~ 60000 clock cycles - * If a and b are the number of iteration in 2 nested loops - * it takes the following number of cycles to complete the operation: - * number_of_cycles = ((2 + n) * b + 2) * a - * where n is the number of instruction in the inner loop - * One possible solution is n = 0 , a = 256 , b = 118 => a = FF, - * b = 76 - */ + /* tINIT is typically 200us (but can be adjusted in the GUI) + * The total number of cycles required for this nested counter structure to + * complete is defined by: + * num_cycles = (CTR0 + 1) * [(CTR1 + 1) * (2 * (CTR2 + 1) + 1) + 1] + 1 + */ /*TODO: Need to manage multi-rank */ /* Load counters */ - IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0xFF)); - IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, SKIP_DELAY_LOOP_VALUE_OR_ZERO(0x76)); + IOWR_32DIRECT(RW_MGR_LOAD_CNTR_0, 0, + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL)); + IOWR_32DIRECT(RW_MGR_LOAD_CNTR_1, 0, + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL)); + IOWR_32DIRECT(RW_MGR_LOAD_CNTR_2, 0, + SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL)); /* Load jump address */ IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_0, 0, __RW_MGR_INIT_CKE_0); - IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_CKE_0_inloop); + IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_1, 0, __RW_MGR_INIT_CKE_0); + IOWR_32DIRECT(RW_MGR_LOAD_JUMP_ADD_2, 0, __RW_MGR_INIT_CKE_0); /* Execute count instruction */ - /* IOWR_32DIRECT(BASE_RW_MGR, 0, __RW_MGR_COUNT_REG_0); */ IOWR_32DIRECT(RW_MGR_RUN_SINGLE_GROUP, 0, __RW_MGR_INIT_CKE_0); /* indicate that memory is stable */ @@ -1717,8 +1711,25 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns (uint32_t rank_bgn, static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks (uint32_t group, uint32_t num_tries, t_btfld *bit_chk) { - return rw_mgr_mem_calibrate_read_test_patterns (0, group, - num_tries, bit_chk, 1); + if (rw_mgr_mem_calibrate_read_test_patterns(0, group, num_tries, bit_chk, 1)) { + return 1; + } else { + /* case:139851 - if guaranteed read fails, we can retry using + * different dqs enable phases. It is possible that with the + * initial phase, dqs enable is asserted/deasserted too close + * to an dqs edge, truncating the read burst. + */ + uint32_t p; + for (p = 0; p <= IO_DQS_EN_PHASE_MAX; p++) { + scc_mgr_set_dqs_en_phase_all_ranks (group, p); + if (rw_mgr_mem_calibrate_read_test_patterns(0, + group, num_tries, bit_chk, 1)) { + return 1; + } + } + + return 0; + } } /* load up the patterns we are going to use during a read test */ @@ -4260,6 +4271,7 @@ static int socfpga_sdram_calibration(const uint32_t *inst_rom_init, uint32_t ins param_t my_param; gbl_t my_gbl; uint32_t pass; + uint32_t i; param = &my_param; gbl = &my_gbl; @@ -4280,6 +4292,16 @@ static int socfpga_sdram_calibration(const uint32_t *inst_rom_init, uint32_t ins #if USE_DQS_TRACKING initialize_tracking(); #endif + + /* Enable all ranks, groups */ + for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++) + param->skip_ranks[i] = 0; + + for (i = 0; i < NUM_SHADOW_REGS; ++i) + param->skip_shadow_regs[i] = 0; + + param->skip_groups = 0; + pr_debug("Preparing to start memory calibration\n"); pr_debug("%s%s %s ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u " diff --git a/arch/arm/mach-socfpga/include/mach/sequencer.h b/arch/arm/mach-socfpga/include/mach/sequencer.h index c437106bc2..7c9157a257 100644 --- a/arch/arm/mach-socfpga/include/mach/sequencer.h +++ b/arch/arm/mach-socfpga/include/mach/sequencer.h @@ -2,31 +2,32 @@ #define _SEQUENCER_H_ /* -Copyright (c) 2012, Altera Corporation -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of Altera Corporation nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY -DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ + * Copyright Altera Corporation (C) 2012-2014. All rights reserved + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Altera Corporation nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ #define MRS_MIRROR_PING_PONG_ATSO 0 #define DYNAMIC_CALIBRATION_MODE 0 @@ -396,6 +397,48 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010 #define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020 +/* Init and Reset delay constants - Only use if defined by sequencer_defines.h, + * otherwise, revert to defaults + * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 = 200.75us @ 266MHz + */ +#ifdef TINIT_CNTR0_VAL + #define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL +#else + #define SEQ_TINIT_CNTR0_VAL 0 +#endif + +#ifdef TINIT_CNTR1_VAL + #define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL +#else + #define SEQ_TINIT_CNTR1_VAL 202 +#endif + +#ifdef TINIT_CNTR2_VAL + #define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL +#else + #define SEQ_TINIT_CNTR2_VAL 131 +#endif + + +/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 = 500.86us @ 266MHz */ +#ifdef TRESET_CNTR0_VAL + #define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL +#else + #define SEQ_TRESET_CNTR0_VAL 2 +#endif + +#ifdef TRESET_CNTR1_VAL + #define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL +#else + #define SEQ_TRESET_CNTR1_VAL 252 +#endif + +#ifdef TRESET_CNTR2_VAL + #define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL +#else + #define SEQ_TRESET_CNTR2_VAL 131 +#endif + /* Bitfield type changes depending on protocol */ typedef uint32_t t_btfld; @@ -409,6 +452,9 @@ typedef struct param_type { t_btfld read_correct_mask_vg; t_btfld write_correct_mask; t_btfld write_correct_mask_vg; + uint32_t skip_ranks[MAX_RANKS]; + uint32_t skip_groups; + uint32_t skip_shadow_regs[NUM_SHADOW_REGS]; /* set a particular entry to 1 if we need to skip a particular group */ } param_t; diff --git a/arch/arm/mach-socfpga/init.c b/arch/arm/mach-socfpga/init.c index 85002844d7..0c679e3d2d 100644 --- a/arch/arm/mach-socfpga/init.c +++ b/arch/arm/mach-socfpga/init.c @@ -10,7 +10,7 @@ #include <mach/generic.h> void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config, - unsigned long *pinmux, int num_pinmux) + struct socfpga_io_config *io_config) { uint32_t val; @@ -34,13 +34,13 @@ void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config, debug("Configure IOCSR\n"); /* configure the IOCSR through scan chain */ - scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_0, CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table); - scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_1, CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table); - scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_2, CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table); - scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_3, CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table); + scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_0, CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, io_config->iocsr_emac_mixed2); + scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_1, CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, io_config->iocsr_mixed1_flash); + scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_2, CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, io_config->iocsr_general); + scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_3, CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, io_config->iocsr_ddr); /* configure the pin muxing through system manager */ - socfpga_sysmgr_pinmux_init(pinmux, num_pinmux); + socfpga_sysmgr_pinmux_init(io_config->pinmux, io_config->num_pin); writel(RSTMGR_PERMODRST_L4WD0 | RSTMGR_PERMODRST_L4WD1, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS); |