diff options
| -rw-r--r-- | arch/arm/mach-imx/imx35.c | 19 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx35-regs.h | 1 |
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c index 74d63eb1ba..5a0cff4f09 100644 --- a/arch/arm/mach-imx/imx35.c +++ b/arch/arm/mach-imx/imx35.c @@ -16,6 +16,7 @@ */ #include <common.h> +#include <init.h> #include <asm/io.h> #include <mach/imx-regs.h> #include <mach/iim.h> @@ -39,3 +40,21 @@ int imx_silicon_revision() return (reg & 0xFF); } + +/* + * There are some i.MX35 CPUs in the wild, comming with bogus L2 cache settings. + * These misconfigured CPUs will run amok immediately when the L2 cache gets + * enabled. Workaraound is to setup the correct register setting prior enabling + * the L2 cache. This should not hurt already working CPUs, as they are using the + * same value + */ + +#define L2_MEM_VAL 0x10 + +static int imx35_l2_fix(void) +{ + writel(0x515, IMX_CLKCTL_BASE + L2_MEM_VAL); + + return 0; +} +core_initcall(imx35_l2_fix); diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h index 280d075c87..fafcd61e33 100644 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -31,6 +31,7 @@ #endif #define IMX_L2CC_BASE 0x30000000 +#define IMX_CLKCTL_BASE 0x43F0C000 #define IMX_UART1_BASE 0x43F90000 #define IMX_UART2_BASE 0x43F94000 #define IMX_TIM1_BASE 0x53F90000 |