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-rw-r--r--arch/arm/boards/stm32mp15x-ev1/board.c3
-rw-r--r--arch/arm/boards/stm32mp15xx-dkx/lowlevel.c2
-rw-r--r--arch/arm/dts/stm32mp135f-dk.dts6
-rw-r--r--arch/arm/mach-stm32mp/init.c106
-rw-r--r--drivers/mci/mci-core.c8
-rw-r--r--drivers/mci/stm32_sdmmc2.c14
-rw-r--r--include/mach/stm32mp/revision.h41
7 files changed, 59 insertions, 121 deletions
diff --git a/arch/arm/boards/stm32mp15x-ev1/board.c b/arch/arm/boards/stm32mp15x-ev1/board.c
index 51c3bb21e9..fd58e2817b 100644
--- a/arch/arm/boards/stm32mp15x-ev1/board.c
+++ b/arch/arm/boards/stm32mp15x-ev1/board.c
@@ -2,6 +2,7 @@
#include <bootsource.h>
#include <common.h>
+#include <deep-probe.h>
#include <init.h>
#include <mach/stm32mp/bbu.h>
@@ -30,7 +31,7 @@ static const struct of_device_id ed1_of_match[] = {
{ .compatible = "st,stm32mp157c-ed1" },
{ /* sentinel */ },
};
-MODULE_DEVICE_TABLE(of, ed1_of_match);
+BAREBOX_DEEP_PROBE_ENABLE(ed1_of_match);
static struct driver ed1_board_driver = {
.name = "board-stm32mp15x-ed1",
diff --git a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
index f52a3f4375..402658d592 100644
--- a/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
+++ b/arch/arm/boards/stm32mp15xx-dkx/lowlevel.c
@@ -24,7 +24,7 @@ ENTRY_FUNCTION(start_stm32mp15xx_dkx, r0, r1, r2)
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
- err = __stm32mp_get_cpu_type(&cputype);
+ err = __stm32mp15_get_cpu_type(&cputype);
if (!err && cputype == CPU_STM32MP157Axx)
fdt = __dtb_z_stm32mp157a_dk1_start;
else
diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts
index 3859566281..f07f7f5536 100644
--- a/arch/arm/dts/stm32mp135f-dk.dts
+++ b/arch/arm/dts/stm32mp135f-dk.dts
@@ -4,9 +4,5 @@
#include "stm32mp131.dtsi"
/ {
- model = "STM32MP153F-DK";
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
+ model = "STM32MP135F-DK";
};
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index b63c1be5be..2eb8b6beec 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -42,12 +42,9 @@
/* TAMP registers */
#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
-/* secure access */
-#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
-#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
/* non secure access */
-#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
-#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21)
+#define STM32MP13_TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30)
+#define STM32MP15_TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
#define TAMP_BOOT_MODE_SHIFT 8
@@ -60,9 +57,8 @@
#define FIXUP_CPU_NUM(mask) ((mask) >> 16)
#define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL)
-static void setup_boot_mode(void)
+static void setup_boot_mode(u32 boot_ctx)
{
- u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
u32 boot_mode =
(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
@@ -101,29 +97,6 @@ static void setup_boot_mode(void)
bootsource_set_raw(src, instance);
}
-static int __stm32mp_cputype;
-int stm32mp_cputype(void)
-{
- return __stm32mp_cputype;
-}
-
-static int __stm32mp_silicon_revision;
-int stm32mp_silicon_revision(void)
-{
- return __stm32mp_silicon_revision;
-}
-
-static int __stm32mp_package;
-int stm32mp_package(void)
-{
- return __stm32mp_package;
-}
-
-static u32 get_cpu_revision(void)
-{
- return (stm32mp_read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
-}
-
static int get_cpu_package(u32 *pkg)
{
int ret = bsec_read_field(BSEC_OTP_PKG, pkg);
@@ -181,118 +154,77 @@ static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg)
return fixup_pinctrl(root, "st,stm32mp157-z-pinctrl", pkg);
}
-static int setup_cpu_type(void)
+static int stm32mp15_setup_cpu_type(void)
{
- const char *cputypestr, *cpupkgstr, *cpurevstr;
unsigned long cpufixupctx = 0, pkgfixupctx = 0;
- u32 pkg;
- int ret;
+ int cputype, package;
- __stm32mp_get_cpu_type(&__stm32mp_cputype);
- switch (__stm32mp_cputype) {
+ __stm32mp15_get_cpu_type(&cputype);
+ switch (cputype) {
case CPU_STM32MP157Fxx:
- cputypestr = "157F";
cpufixupctx = FIXUP_CPU_MASK(2, 800);
break;
case CPU_STM32MP157Dxx:
- cputypestr = "157D";
cpufixupctx = FIXUP_CPU_MASK(2, 800);
break;
case CPU_STM32MP157Cxx:
- cputypestr = "157C";
cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP157Axx:
- cputypestr = "157A";
cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP153Fxx:
- cputypestr = "153F";
cpufixupctx = FIXUP_CPU_MASK(2, 800);
break;
case CPU_STM32MP153Dxx:
- cputypestr = "153D";
cpufixupctx = FIXUP_CPU_MASK(2, 800);
break;
case CPU_STM32MP153Cxx:
- cputypestr = "153C";
cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP153Axx:
- cputypestr = "153A";
cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP151Cxx:
- cputypestr = "151C";
cpufixupctx = FIXUP_CPU_MASK(1, 650);
break;
case CPU_STM32MP151Axx:
- cputypestr = "151A";
cpufixupctx = FIXUP_CPU_MASK(1, 650);
break;
case CPU_STM32MP151Fxx:
- cputypestr = "151F";
cpufixupctx = FIXUP_CPU_MASK(1, 800);
break;
case CPU_STM32MP151Dxx:
- cputypestr = "151D";
cpufixupctx = FIXUP_CPU_MASK(1, 800);
break;
default:
- cputypestr = "????";
break;
}
- get_cpu_package(&__stm32mp_package );
- switch (__stm32mp_package) {
+ get_cpu_package(&package);
+ switch (package) {
case PKG_AA_LBGA448:
- cpupkgstr = "AA";
pkgfixupctx = STM32MP_PKG_AA;
break;
case PKG_AB_LBGA354:
- cpupkgstr = "AB";
pkgfixupctx = STM32MP_PKG_AB;
break;
case PKG_AC_TFBGA361:
- cpupkgstr = "AC";
pkgfixupctx = STM32MP_PKG_AC;
break;
case PKG_AD_TFBGA257:
- cpupkgstr = "AD";
pkgfixupctx = STM32MP_PKG_AD;
break;
default:
- cpupkgstr = "??";
- break;
- }
-
- __stm32mp_silicon_revision = get_cpu_revision();
- switch (__stm32mp_silicon_revision) {
- case CPU_REV_A:
- cpurevstr = "A";
- break;
- case CPU_REV_B:
- cpurevstr = "B";
- break;
- case CPU_REV_Z:
- cpurevstr = "Z";
break;
- default:
- cpurevstr = "?";
}
- pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n",
- __stm32mp_cputype, pkg, __stm32mp_silicon_revision);
- pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr);
-
- if (cpufixupctx) {
- ret = of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
- if (ret)
- return ret;
- }
+ pr_debug("cputype = 0x%x, package = 0x%x\n", cputype, package);
+ if (cpufixupctx)
+ of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
if (pkgfixupctx)
- return of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx);
+ of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx);
return 0;
}
@@ -306,6 +238,8 @@ int stm32mp_soc(void)
static int stm32mp_init(void)
{
+ u32 boot_ctx;
+
if (of_machine_is_compatible("st,stm32mp135"))
__st32mp_soc = 32135;
else if (of_machine_is_compatible("st,stm32mp151"))
@@ -317,8 +251,14 @@ static int stm32mp_init(void)
else
return 0;
- setup_cpu_type();
- setup_boot_mode();
+ if (__st32mp_soc == 32135) {
+ boot_ctx = readl(STM32MP13_TAMP_BOOT_CONTEXT);
+ } else {
+ stm32mp15_setup_cpu_type();
+ boot_ctx = readl(STM32MP15_TAMP_BOOT_CONTEXT);
+ }
+
+ setup_boot_mode(boot_ctx);
return 0;
}
diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index 175753cca5..07eca96a9d 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -1289,7 +1289,13 @@ static int mci_mmc_select_hs_ddr(struct mci *mci)
struct mci_host *host = mci->host;
int ret;
- if (!(mci_caps(mci) & MMC_CAP_MMC_1_8V_DDR))
+ /*
+ * barebox MCI core does not change voltage, so we don't know here
+ * if we should check for the 1.8v or 3.3v mode. Until we support
+ * higher speed modes that require voltage switching like HS200/HS400,
+ * let's just check for either bit.
+ */
+ if (!(mci_caps(mci) & (MMC_CAP_MMC_1_8V_DDR | MMC_CAP_MMC_3_3V_DDR)))
return 0;
ret = mci_mmc_try_bus_width(mci, host->bus_width, MMC_TIMING_MMC_DDR52);
diff --git a/drivers/mci/stm32_sdmmc2.c b/drivers/mci/stm32_sdmmc2.c
index 90e969a867..1bfef1ccf0 100644
--- a/drivers/mci/stm32_sdmmc2.c
+++ b/drivers/mci/stm32_sdmmc2.c
@@ -538,11 +538,14 @@ static void stm32_sdmmc2_set_ios(struct mci_host *mci, struct mci_ios *ios)
struct stm32_sdmmc2_priv *priv = to_mci_host(mci);
u32 desired = mci->clock;
u32 sys_clock = clk_get_rate(priv->clk);
- u32 clk = 0;
+ u32 clk = 0, ddr = 0;
dev_dbg(priv->dev, "%s: bus_width = %d, clock = %d\n", __func__,
mci->bus_width, mci->clock);
+ if (mci_timing_is_ddr(ios->timing))
+ ddr = SDMMC_CLKCR_DDR;
+
if (mci->clock)
stm32_sdmmc2_pwron(priv);
else
@@ -555,13 +558,15 @@ static void stm32_sdmmc2_set_ios(struct mci_host *mci, struct mci_ios *ios)
* clk_div > 0 and NEGEDGE = 1 => command and data generated on
* SDMMCCLK falling edge
*/
- if (desired && (sys_clock > desired ||
+ if (desired && (sys_clock > desired || ddr ||
IS_RISING_EDGE(priv->clk_reg_msk))) {
clk = DIV_ROUND_UP(sys_clock, 2 * desired);
if (clk > SDMMC_CLKCR_CLKDIV_MAX)
clk = SDMMC_CLKCR_CLKDIV_MAX;
}
+ clk |= ddr;
+
if (mci->bus_width == MMC_BUS_WIDTH_4)
clk |= SDMMC_CLKCR_WIDBUS_4;
if (mci->bus_width == MMC_BUS_WIDTH_8)
@@ -624,6 +629,11 @@ static int stm32_sdmmc2_probe(struct amba_device *adev,
if (mci->f_max >= 52000000)
mci->host_caps |= MMC_CAP_MMC_HIGHSPEED_52MHZ;
+ if (of_property_read_bool(np, "mmc-ddr-3_3v"))
+ mci->host_caps |= MMC_CAP_MMC_3_3V_DDR;
+ if (of_property_read_bool(np, "mmc-ddr-1_8v"))
+ mci->host_caps |= MMC_CAP_MMC_1_8V_DDR;
+
return mci_register(&priv->mci);
priv_free:
diff --git a/include/mach/stm32mp/revision.h b/include/mach/stm32mp/revision.h
index 63bdcb3a4d..73cc862a4e 100644
--- a/include/mach/stm32mp/revision.h
+++ b/include/mach/stm32mp/revision.h
@@ -32,30 +32,14 @@
#define CPU_STM32MP151Fxx 0x050000AE
#define CPU_STM32MP151Dxx 0x050000AF
-#define cpu_stm32_is(mask, val) ({ \
- u32 type; \
- __stm32mp_get_cpu_type(&type) == 0 ? (type & mask) == val : 0; \
-})
-
-#define cpu_stm32_is_stm32mp15() cpu_stm32_is(0xFFFF0000, 0x05000000)
-#define cpu_stm32_is_stm32mp13() cpu_stm32_is(0xFFFF0000, 0x05010000)
+#define cpu_stm32_is_stm32mp15() (__stm32mp_get_cpu() == 0x0500)
+#define cpu_stm32_is_stm32mp13() (__stm32mp_get_cpu() == 0x0501)
/* silicon revisions */
#define CPU_REV_A 0x1000
#define CPU_REV_B 0x2000
#define CPU_REV_Z 0x2001
-int stm32mp_silicon_revision(void);
-int stm32mp_cputype(void);
-int stm32mp_package(void);
-
-#define cpu_is_stm32mp157c() (stm32mp_cputype() == CPU_STM32MP157Cxx)
-#define cpu_is_stm32mp157a() (stm32mp_cputype() == CPU_STM32MP157Axx)
-#define cpu_is_stm32mp153c() (stm32mp_cputype() == CPU_STM32MP153Cxx)
-#define cpu_is_stm32mp153a() (stm32mp_cputype() == CPU_STM32MP153Axx)
-#define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx)
-#define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx)
-
/* DBGMCU register */
#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
@@ -64,9 +48,6 @@ int stm32mp_package(void);
#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
#define DBGMCU_IDC_REV_ID_SHIFT 16
-#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
-#define RCC_DBGCFGR_DBGCKEN BIT(8)
-
/* BSEC OTP index */
#define BSEC_OTP_RPN 1
#define BSEC_OTP_PKG 16
@@ -77,12 +58,16 @@ int stm32mp_package(void);
static inline u32 stm32mp_read_idc(void)
{
- setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
return readl(IOMEM(DBGMCU_IDC));
}
+static inline u32 __stm32mp_get_cpu(void)
+{
+ return stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK >> DBGMCU_IDC_DEV_ID_SHIFT;
+}
+
/* Get Device Part Number (RPN) from OTP */
-static inline int __stm32mp_get_cpu_rpn(u32 *rpn)
+static inline int __stm32mp15_get_cpu_rpn(u32 *rpn)
{
int ret = bsec_read_field(BSEC_OTP_RPN, rpn);
if (ret)
@@ -92,15 +77,15 @@ static inline int __stm32mp_get_cpu_rpn(u32 *rpn)
return 0;
}
-static inline int __stm32mp_get_cpu_type(u32 *type)
+static inline int __stm32mp15_get_cpu_type(u32 *type)
{
- u32 id;
- int ret = __stm32mp_get_cpu_rpn(type);
+ int ret;
+
+ ret = __stm32mp15_get_cpu_rpn(type);
if (ret)
return ret;
- id = (stm32mp_read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
- *type |= id << 16;
+ *type |= __stm32mp_get_cpu() << 16;
return 0;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-25 22:49:38 +0000