diff options
181 files changed, 12057 insertions, 201 deletions
diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst index 8fe0a2828d..887b45c708 100644 --- a/Documentation/boards/imx.rst +++ b/Documentation/boards/imx.rst @@ -252,7 +252,7 @@ Header: +--------------------+--------------------------------------------------------------+ | ``loadaddr <adr>`` | The address the binary is uploaded to | +--------------------+--------------------------------------------------------------+ -| ``dcdofs <ofs>`` | The offset of the image header in the image. This should be: | +| ``ivtofs <ofs>`` | The offset of the image header in the image. This should be: | | | | | | * ``0x400``: MMC/SD, NAND, serial ROM, PATA, SATA | | | * ``0x1000``: NOR Flash | diff --git a/Documentation/boards/imx/nxp-imx8mp-evk.rst b/Documentation/boards/imx/nxp-imx8mp-evk.rst new file mode 100644 index 0000000000..fec366e0de --- /dev/null +++ b/Documentation/boards/imx/nxp-imx8mp-evk.rst @@ -0,0 +1,65 @@ +NXP i.MX8MP-EVK board +===================== + +The board comes with: + +* 6GiB of LPDDR4 RAM +* 32GiB eMMC + +Not including booting via serial, the device can boot from either SD or eMMC. + +Downloading DDR PHY firmware +---------------------------- + +As a part of DDR intialization routine NXP i.MX8MQ EVK requires and +uses several binary firmware blobs that are distributed under a +separate EULA and cannot be included in Barebox. In order to obtain +them do the following:: + + wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.7.bin + chmod +x firmware-imx-8.7.bin + ./firmware-imx-8.7.bin + +Executing that file should produce a EULA acceptance dialog as well as +result in the following files: + +- lpddr4_pmu_train_1d_dmem.bin +- lpddr4_pmu_train_1d_imem.bin +- lpddr4_pmu_train_2d_dmem.bin +- lpddr4_pmu_train_2d_imem.bin + +As a last step of this process those files need to be placed in +"firmware/":: + + for f in lpddr4_pmu_train_1d_dmem.bin \ + lpddr4_pmu_train_1d_imem.bin \ + lpddr4_pmu_train_2d_dmem.bin \ + lpddr4_pmu_train_2d_imem.bin; \ + do \ + cp firmware-imx-8.7/firmware/ddr/synopsys/${f} \ + firmware/${f}; \ + done + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Get ATF from https://source.codeaurora.org/external/imx/imx-atf, branch +imx_5.4.3_2.0.0:: + + make PLAT=imx8mp bl31 + cp build/imx8mp/release/bl31.bin ${barebox_srctree}/imx8mp-bl31.bin + +Build Barebox +------------- + +i.MX8MP-EVK support is contained in the imx_v8_defconfig to build it use:: + + make imx_v8_defconfig + make + +Boot Configuration +------------------ + +The NXP i.MX8MP-EVK board has four switches responsible for configuring +bootsource/boot mode. The settings for the different boot sources are +printed on the board. diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index e9e9163d58..304ae59851 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -85,6 +85,7 @@ obj-$(CONFIG_MACH_NVIDIA_JETSON) += nvidia-jetson-tk1/ obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += nxp-imx6ull-evk/ obj-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += nxp-imx8mq-evk/ obj-$(CONFIG_MACH_NXP_IMX8MM_EVK) += nxp-imx8mm-evk/ +obj-$(CONFIG_MACH_NXP_IMX8MP_EVK) += nxp-imx8mp-evk/ obj-$(CONFIG_MACH_OMAP343xSDP) += omap343xdsp/ obj-$(CONFIG_MACH_OMAP3EVM) += omap3evm/ obj-$(CONFIG_MACH_PANDA) += panda/ @@ -104,6 +105,7 @@ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/ obj-$(CONFIG_MACH_PM9261) += pm9261/ obj-$(CONFIG_MACH_PM9263) += pm9263/ obj-$(CONFIG_MACH_PM9G45) += pm9g45/ +obj-$(CONFIG_MACH_PROTONIC_IMX6) += protonic-imx6/ obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/ obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/ obj-$(CONFIG_MACH_RADXA_ROCK) += radxa-rock/ diff --git a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg index 996ecc708d..aefdf68e89 100644 --- a/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg +++ b/arch/arm/boards/advantech-mx6/flash-header-advantech-rom-7421.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e0774 0x000C0000 wm 32 0x020e0754 0x00000000 diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg index 47b572db46..5da5fd9419 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-1g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg index cf3716dbaa..3ccf7591c5 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6dl-2g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg index 8ed987daa8..7bdc0e736c 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg index e6d97d11c1..c6f5aa8484 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6q-2g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg index 50bbfc5bdd..797b9717e7 100644 --- a/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg +++ b/arch/arm/boards/boundarydevices-nitrogen6/flash-header-nitrogen6qp-max.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/ccxmx51/flash-header.imxcfg b/arch/arm/boards/ccxmx51/flash-header.imxcfg index 251c4c1b9b..3b1df11133 100644 --- a/arch/arm/boards/ccxmx51/flash-header.imxcfg +++ b/arch/arm/boards/ccxmx51/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg index 68d947c01d..390b75b4f2 100644 --- a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg +++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00200000 wm 32 0x53fa8558 0x00200040 wm 32 0x53fa8560 0x00200000 diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg index b707dd64a6..c32ab9c162 100644 --- a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg +++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00200000 wm 32 0x53fa8558 0x00200040 wm 32 0x53fa8560 0x00200000 diff --git a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg index 9e8dce5877..4bb615ebb0 100644 --- a/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg +++ b/arch/arm/boards/cm-fx6/flash-header-mx6-cm-fx6.imxcfg @@ -1,4 +1,4 @@ soc imx6 loadaddr 0x00907000 max_load_size 0x11000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg index 400a870154..14146bed22 100644 --- a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg +++ b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg @@ -1,3 +1,3 @@ soc imx6 loadaddr 0x00907000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg index 2be0210dd6..fe8bd8cbd6 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-micron.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg index fb34903e27..6919bd8c3f 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6q-nanya.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg index 42e98d65d3..709c11974b 100644 --- a/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg +++ b/arch/arm/boards/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x17800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg index 36edad7a3e..7b2a198672 100644 --- a/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg +++ b/arch/arm/boards/digi-ccimx6ulsom/flash-header-imx6ul-ccimx6ulsbcpro.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg b/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg index 53875ed319..60436e7e37 100644 --- a/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg +++ b/arch/arm/boards/efika-mx-smartbook/flash-header-imx51-genesi-efikasb.imxcfg @@ -1,6 +1,6 @@ soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000000 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 diff --git a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg index 7aa5dd8d45..798f2cbcb0 100644 --- a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg +++ b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg @@ -11,7 +11,7 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx7-ddr-regs.h> diff --git a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg index f04adf86a4..5b422a7867 100644 --- a/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg +++ b/arch/arm/boards/eltec-hipercam/flash-header-eltec-hipercam.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg index 1139312da6..d51dc17a12 100644 --- a/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg +++ b/arch/arm/boards/embedsky-e9/flash-header-e9.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x27800000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg index bdaf60cb4a..afc95d9bd9 100644 --- a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg +++ b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e05a8 0x00000030 wm 32 0x020e05b0 0x00000030 diff --git a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg index c9a8098f6d..bc30e4c387 100644 --- a/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg +++ b/arch/arm/boards/embest-riotboard/flash-header-embest-riotboard.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x20000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg index b0c3b69b46..129498ca85 100644 --- a/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg +++ b/arch/arm/boards/eukrea_cpuimx25/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx25 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8001008 0x00000000 wm 32 0xb8001010 0x00000004 diff --git a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg index 85200bbb50..c1353e2904 100644 --- a/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg +++ b/arch/arm/boards/eukrea_cpuimx35/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx35 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53F80004 0x00821000 wm 32 0x53F80004 0x00821000 diff --git a/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg b/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg index 5b51106284..85c128c8fd 100644 --- a/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg +++ b/arch/arm/boards/eukrea_cpuimx51/flash-header.imxcfg @@ -1,5 +1,5 @@ soc imx51 -dcdofs 0x400 +ivtofs 0x400 loadaddr 0x90000000 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 diff --git a/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg b/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg index f195e8c002..8c1a257829 100644 --- a/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg +++ b/arch/arm/boards/freescale-mx25-3ds/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx25 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8002050 0x0000d843 wm 32 0xb8002054 0x22252521 wm 32 0xb8002058 0x22220a00 diff --git a/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg b/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg index 6eb8bc242c..ea1803b7de 100644 --- a/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg +++ b/arch/arm/boards/freescale-mx35-3ds/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx35 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8002050 0x0000d843 wm 32 0xb8002054 0x22252521 diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg index bac6816fee..b4e11fc227 100644 --- a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg +++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x90000000 soc imx51 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 wm 32 0x73fa8510 0x000020c5 diff --git a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg index f43b484ee6..2025f5da08 100644 --- a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg +++ b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00300000 wm 32 0x53fa8558 0x00300040 wm 32 0x53fa8560 0x00300000 diff --git a/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg b/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg index 95bcd19805..fac4c29019 100644 --- a/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg +++ b/arch/arm/boards/freescale-mx53-smd/flash-header.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00300000 wm 32 0x53fa8558 0x00300040 wm 32 0x53fa8560 0x00300000 diff --git a/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg b/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg index 3bf73b65aa..e6f73df30e 100644 --- a/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg +++ b/arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x70000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8554 0x00300000 wm 32 0x53fa8558 0x00300040 wm 32 0x53fa8560 0x00300000 diff --git a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg index 3ce8562f51..d635c8b948 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg +++ b/arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg index 21f217cdf3..133f499ab9 100644 --- a/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx6-sabresd/flash-header-mx6-sabresd.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x20e05a8 0x00000030 wm 32 0x20e05b0 0x00000030 wm 32 0x20e0524 0x00000030 diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg b/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg index a96b3e7154..5536f342b4 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/flash-header-mx6sx-sabresdb.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg index f4920bc133..41e0e9ca61 100644 --- a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg +++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg @@ -1,5 +1,5 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/flash-header/imx7d-ddr-sabresd.imxcfg>
\ No newline at end of file diff --git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg index 71150802bf..bcef9921fa 100644 --- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg +++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg @@ -1,6 +1,6 @@ soc vf610 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/vf610-iomux-regs.h> #include <mach/vf610-ddrmc-regs.h> diff --git a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg index b9a6fc12ff..98c7ae6095 100644 --- a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg +++ b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/gk802/flash-header.imxcfg b/arch/arm/boards/gk802/flash-header.imxcfg index f26fe77b03..acc7a36785 100644 --- a/arch/arm/boards/gk802/flash-header.imxcfg +++ b/arch/arm/boards/gk802/flash-header.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h index 60a39f524b..82f5c627a3 100644 --- a/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h +++ b/arch/arm/boards/grinn-liteboard/flash-header-liteboard.h @@ -1,7 +1,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/guf-santaro/flash-header.imxcfg b/arch/arm/boards/guf-santaro/flash-header.imxcfg index 2e85e13ba9..4505d81ea1 100644 --- a/arch/arm/boards/guf-santaro/flash-header.imxcfg +++ b/arch/arm/boards/guf-santaro/flash-header.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/guf-vincell/flash-header.imxcfg b/arch/arm/boards/guf-vincell/flash-header.imxcfg index 8bfb5d0508..c17dcbab6e 100644 --- a/arch/arm/boards/guf-vincell/flash-header.imxcfg +++ b/arch/arm/boards/guf-vincell/flash-header.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 //============================================================================= //init script for i.MX53 DDR3 diff --git a/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg b/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg index 2345f18e93..6f8eaf0fc5 100644 --- a/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg +++ b/arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg @@ -4,7 +4,7 @@ # soc imx25 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0xb8001010 0x00000002 wm 32 0xb8001004 0x00095728 wm 32 0xb8001000 0x92116480 diff --git a/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg b/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg index ebb7c4f396..4aaa75a0ea 100644 --- a/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg +++ b/arch/arm/boards/karo-tx51/flash-header-karo-tx51.imxcfg @@ -1,6 +1,6 @@ soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x83fd9000 0x80000000 wm 32 0x83fd9014 0x04008008 wm 32 0x83fd9014 0x00008010 diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg index d5e6454b88..4bcb3b8b5e 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-rev1011.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fd406c 0xffffffff wm 32 0x53fd4070 0xffffffff diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg index 6962abd5e6..a4e3fab9a3 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30-samsung.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fa8004 0x00194005 /* set LDO to 1.3V */ diff --git a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg index 2b47d63bd4..5b6b79f705 100644 --- a/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg +++ b/arch/arm/boards/karo-tx53/flash-header-tx53-revxx30.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x71000000 soc imx53 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53fd4068 0xffcc0fff wm 32 0x53fd406c 0x000fffc3 wm 32 0x53fd4070 0x0f3c0000 diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg index b7a914fba5..7d77f54f00 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-1g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg index 3f6578e19c..eb63fa34d3 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6dl-512m.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg index 165b69fb19..e5a1ed2331 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6q-1g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg index fc00de957c..889416b849 100644 --- a/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg +++ b/arch/arm/boards/karo-tx6x/flash-header-tx6qp-2g.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg index fae10423c5..b8a4e824ef 100644 --- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr1.imxcfg @@ -7,7 +7,7 @@ soc imx50 loadaddr 0x70020000 -dcdofs 0x400 +ivtofs 0x400 # Switch pll1_sw_clk to step_clk wm 32 0x53fd400c 0x00000004 diff --git a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg index 94436a7b54..527d91dc78 100644 --- a/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg +++ b/arch/arm/boards/kindle-mx50/flash-header-kindle-lpddr2.imxcfg @@ -8,7 +8,7 @@ soc imx50 loadaddr 0x70020000 -dcdofs 0x400 +ivtofs 0x400 # Switch pll1_sw_clk to step_clk wm 32 0x53fd400c 0x00000004 diff --git a/arch/arm/boards/kindle3/flash-header.imxcfg b/arch/arm/boards/kindle3/flash-header.imxcfg index cb56acf9cd..74b65d6a5c 100644 --- a/arch/arm/boards/kindle3/flash-header.imxcfg +++ b/arch/arm/boards/kindle3/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx35 loadaddr 0x87eff400 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x53f80004 0x00821000 wm 32 0x53f80004 0x00821000 diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg index 9906617083..db1698d272 100644 --- a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-duallite.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e0774 0x000c0000 wm 32 0x020e0754 0x00000000 diff --git a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg index 7e6ffd7983..99608d0fe8 100644 --- a/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg +++ b/arch/arm/boards/kontron-samx6i/flash-header-samx6i-quad.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020e05a8 0x00000030 wm 32 0x020e05b0 0x00000030 diff --git a/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg b/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg index a507ab3e24..2538caea8a 100644 --- a/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg +++ b/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg @@ -9,7 +9,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg index 727439db7c..b013173113 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg +++ b/arch/arm/boards/nxp-imx8mm-evk/flash-header-imx8mm-evk.imxcfg @@ -2,4 +2,4 @@ soc imx8mm loadaddr 0x007e1000 max_load_size 0x3f000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/nxp-imx8mp-evk/Makefile b/arch/arm/boards/nxp-imx8mp-evk/Makefile new file mode 100644 index 0000000000..4d0d989015 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o lpddr4-timing.o diff --git a/arch/arm/boards/nxp-imx8mp-evk/board.c b/arch/arm/boards/nxp-imx8mp-evk/board.c new file mode 100644 index 0000000000..d75eb1c697 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/board.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Oleksij Rempel, Pengutronix + */ + +#include <asm/memory.h> +#include <bootsource.h> +#include <common.h> +#include <init.h> +#include <linux/phy.h> +#include <linux/sizes.h> +#include <mach/bbu.h> +#include <mach/iomux-mx8mp.h> +#include <gpio.h> +#include <envfs.h> + +static int nxp_imx8mp_evk_init(void) +{ + int emmc_bbu_flag = 0; + int emmc_sd_flag = 0; + u32 val; + + if (!of_machine_is_compatible("fsl,imx8mp-evk")) + return 0; + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 2) { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } else { + of_device_enable_path("/chosen/environment-sd"); + emmc_sd_flag = BBU_HANDLER_FLAG_DEFAULT; + } + } else { + of_device_enable_path("/chosen/environment-emmc"); + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT; + } + + imx8mq_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox", + emmc_sd_flag); + imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc2", + emmc_bbu_flag); + + val = readl(MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + val |= MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN; + writel(val, MX8MP_IOMUXC_GPR_BASE_ADDR + MX8MP_IOMUXC_GPR1); + + return 0; +} +coredevice_initcall(nxp_imx8mp_evk_init); diff --git a/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg b/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg new file mode 100644 index 0000000000..7739fe5be6 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg @@ -0,0 +1,5 @@ +soc imx8mp + +loadaddr 0x920000 +max_load_size 0x3f000 +ivtofs 0x0 diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c new file mode 100644 index 0000000000..5df1ed0780 --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <io.h> +#include <common.h> +#include <debug_ll.h> +#include <firmware.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/sections.h> +#include <asm/barebox-arm.h> +#include <asm/barebox-arm-head.h> +#include <i2c/i2c-early.h> +#include <linux/sizes.h> +#include <mach/atf.h> +#include <mach/xload.h> +#include <mach/esdctl.h> +#include <mach/generic.h> +#include <mach/imx8mp-regs.h> +#include <mach/iomux-mx8mp.h> +#include <mach/imx8m-ccm-regs.h> +#include <mfd/pca9450.h> +#include <soc/imx8m/ddr.h> +#include <soc/fsl/fsl_udc.h> + +extern char __dtb_imx8mp_evk_start[]; + +#define UART_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_FSEL) + +#define I2C_PAD_CTRL MUX_PAD_CTRL(MX8MP_PAD_CTL_DSE6 | \ + MX8MP_PAD_CTL_HYS | \ + MX8MP_PAD_CTL_PUE | \ + MX8MP_PAD_CTL_PE) + +static void setup_uart(void) +{ + imx8m_early_setup_uart_clock(); + + imx8mp_setup_pad(MX8MP_PAD_UART2_TXD__UART2_DCE_TX | UART_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_UART2_RXD__UART2_DCE_RX | UART_PAD_CTRL); + imx8m_uart_setup_ll(); + + putc_ll('>'); +} + +static void pmic_reg_write(void *i2c, int reg, uint8_t val) +{ + int ret; + u8 buf[32]; + struct i2c_msg msgs[] = { + { + .addr = 0x25, + .buf = buf, + }, + }; + + buf[0] = reg; + buf[1] = val; + + msgs[0].len = 2; + + ret = i2c_fsl_xfer(i2c, msgs, ARRAY_SIZE(msgs)); + if (ret != 1) + pr_err("Failed to write to pmic\n"); +} + +static int power_init_board(void) +{ + void *i2c; + + imx8mp_setup_pad(MX8MP_PAD_I2C1_SCL__I2C1_SCL | I2C_PAD_CTRL); + imx8mp_setup_pad(MX8MP_PAD_I2C1_SDA__I2C1_SDA | I2C_PAD_CTRL); + + imx8mm_early_clock_init(); + imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_I2C1); + + i2c = imx8m_i2c_early_init(IOMEM(MX8MP_I2C1_BASE_ADDR)); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(i2c, PCA9450_BUCK123_DVS, 0x29); + + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + pmic_reg_write(i2c, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(i2c, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(i2c, PCA9450_BUCK1CTRL, 0x59); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(i2c, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} + +extern struct dram_timing_info imx8mp_evk_dram_timing; + +static void start_atf(void) +{ + size_t bl31_size; + const u8 *bl31; + enum bootsource src; + int instance; + + /* + * If we are in EL3 we are running for the first time and need to + * initialize the DRAM and run TF-A (BL31). The TF-A will then jump + * to DRAM in EL2. + */ + if (current_el() != 3) + return; + + power_init_board(); + + imx8mm_ddr_init(&imx8mp_evk_dram_timing); + + imx8mp_get_boot_source(&src, &instance); + switch (src) { + case BOOTSOURCE_MMC: + imx8mp_esdhc_load_image(instance, false); + break; + default: + printf("Unhandled bootsource BOOTSOURCE_%d\n", src); + hang(); + } + + + /* + * On completion the TF-A will jump to MX8M_ATF_BL33_BASE_ADDR + * in EL2. Copy the image there, but replace the PBL part of + * that image with ourselves. On a high assurance boot only the + * currently running code is validated and contains the checksum + * for the piggy data, so we need to ensure that we are running + * the same code in DRAM. + */ + memcpy((void *)MX8M_ATF_BL33_BASE_ADDR, + __image_start, barebox_pbl_size); + + get_builtin_firmware(imx8mp_bl31_bin, &bl31, &bl31_size); + + imx8mp_atf_load_bl31(bl31, bl31_size); + + /* not reached */ +} + +/* + * Power-on execution flow of start_nxp_imx8mp_evk() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time. At entry the exception level is EL3. + * + * 2. DDR is initialized and the image is loaded from storage into DRAM. The PBL + * part is copied from OCRAM to the TF-A return address in DRAM. + * + * 3. TF-A is executed and exits into the PBL code in DRAM. TF-A has taken us + * from EL3 to EL2. + * + * 4. Standard barebox boot flow continues + */ +static __noreturn noinline void nxp_imx8mp_evk_start(void) +{ + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + start_atf(); + + /* + * Standard entry we hit once we initialized both DDR and ATF + */ + imx8mp_barebox_entry(__dtb_imx8mp_evk_start); +} + +ENTRY_FUNCTION(start_nxp_imx8mp_evk, r0, r1, r2) +{ + void __iomem *ccm = IOMEM(MX8M_CCM_BASE_ADDR); + + writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0), + ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_SCTR)); + + imx8mp_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + nxp_imx8mp_evk_start(); +} diff --git a/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c new file mode 100644 index 0000000000..bc4c10fe8d --- /dev/null +++ b/arch/arm/boards/nxp-imx8mp-evk/lpddr4-timing.c @@ -0,0 +1,1848 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include <common.h> +#include <soc/imx8m/ddr.h> +#include <soc/imx8m/lpddr4_define.h> + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x460048 }, + { 0x3d4000ec, 0x150048 }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x807bf }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x21 }, + { 0x3d403024, 0x30d400 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4846 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x15 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4846 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x15 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x4600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1500 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x4600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1500 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x448 }, + { 0x90169, 0x109 }, + { 0x9016a, 0xf }, + { 0x9016b, 0x7c0 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x0 }, + { 0x9016e, 0xe8 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x47 }, + { 0x90171, 0x630 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0x618 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0xe0 }, + { 0x90178, 0x109 }, + { 0x90179, 0x0 }, + { 0x9017a, 0x7c8 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x8140 }, + { 0x9017e, 0x10c }, + { 0x9017f, 0x0 }, + { 0x90180, 0x478 }, + { 0x90181, 0x109 }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info imx8mp_evk_dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg index 11463fe850..80ce03e22c 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg +++ b/arch/arm/boards/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg @@ -2,5 +2,5 @@ soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/habv4-imx8-gencsf.h> diff --git a/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg b/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg index 36b68cd7ee..d3049369d9 100644 --- a/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx35/flash-header.imxcfg @@ -1,5 +1,5 @@ soc imx35 -dcdofs 0x400 +ivtofs 0x400 loadaddr 0x80000000 wm 32 0x53f80004 0x00821000 wm 32 0x53f80004 0x00821000 diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg index 6e08b6c1b1..a18f3dbed1 100644 --- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg +++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg @@ -11,7 +11,7 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx7-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h index 06ba308fb8..1876a5aa9d 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h index 5401e4243e..9a8f5f18e1 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h @@ -1,7 +1,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h index 8b83aeae63..d32ee836a8 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h index da4708e4e3..e820cbf86b 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h index 6e7b740a6f..f3174f9bb7 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058qp.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 /* NOC setup */ wm 32 0x00bb0008 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h index c5ed9b759f..4a9b179f59 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h index b0f3faa0b7..be4084c161 100644 --- a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x10000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg index aff8321b9a..8921f32110 100644 --- a/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg +++ b/arch/arm/boards/phytec-som-imx8mq/flash-header-phycore-imx8mq.imxcfg @@ -2,4 +2,4 @@ soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/protonic-imx6/Makefile b/arch/arm/boards/protonic-imx6/Makefile new file mode 100644 index 0000000000..b08c4a93ca --- /dev/null +++ b/arch/arm/boards/protonic-imx6/Makefile @@ -0,0 +1 @@ +lwl-y += lowlevel.o diff --git a/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg b/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg new file mode 100644 index 0000000000..65bd1bc3c6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/ddr3-defines.imxcfg @@ -0,0 +1,350 @@ +/* + * Timing configuration: + * + * MDCFG0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRFC 2Gb 400MHz 0x3f (64) 24 0x3f000000 + * 4Gb 400MHz 0x77 (120) 24 0x77000000 + * 8Gb 400MHz 0x8b (140) 24 0x8b000000 + * 2Gb 533MHz 0x55 (86) 24 0x55000000 + * 4Gb 533MHz 0x9f (160) 24 0x9f000000 + * 8Gb 533MHz 0xba (187) 24 0xba000000 + * tXS 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * tXP * 400MHz 0x2 (3) 13 0x00004000 + * * 533MHz 0x3 (4) 13 0x00006000 + * tXPDLL * 400MHz 0x9 (10) 9 0x00001200 + * * 533MHz 0xc (13) 9 0x00001800 + * tFAW * 400MHz 0x13 (20) 4 0x00000130 + * * 533MHz 0x1a (27) 4 0x000001a0 + * tCL * 400MHz 0x3 (6) 0 0x00000003 + * * 533MHz-CL7 0x4 (7) 0 0x00000004 + * * 533MHz-CL8 0x5 (8) 0 0x00000005 + * ---------------------------------------------------------------- + */ +#define MDCFG0_2G_400MHZ 0x3f435333 +#define MDCFG0_4G_400MHZ 0x777b5333 +#define MDCFG0_8G_400MHZ 0x8b8f5333 +#define MDCFG0_2G_533MHZ_CL8 0x555b79a5 +#define MDCFG0_2G_533MHZ_CL7 0x555b79a4 +#define MDCFG0_4G_533MHZ_CL8 0x9fa579a5 +#define MDCFG0_4G_533MHZ_CL7 0x9fa579a4 +#define MDCFG0_8G_533MHZ_CL8 0xbac079a5 +#define MDCFG0_8G_533MHZ_CL7 0xbac079a4 + +/* + * MDCFG1: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRCD * 400MHz 0x5 (6) 28 0xa0000000 + * * 533MHz 0x7 (8) 28 0xe0000000 + * tRP * 400MHz 0x5 (6) 26 0x14000000 + * * 533MHz 0x7 (8) 26 0x1c000000 + * tRC * 400MHz 0x14 (21) 21 0x02800000 + * * 533MHz 0x1b (28) 21 0x03600000 + * tRAS * 400MHz 0x0e (15) 16 0x000e0000 + * * 533MHz 0x13 (20) 16 0x00130000 + * tRPA * 0x1 (tRP+1) 15 0x00008000 + * tWR * 400MHz 0x5 (6) 9 0x00000a00 + * * 533MHz 0x7 (8) 9 0x00000e00 + * tMRD * 0xb (12) 5 0x00000160 + * tCWL * 400MHz 0x3 (5) 0 0x00000003 + * * 533MHz 0x4 (6) 0 0x00000004 + * ---------------------------------------------------------------- + */ +#define MDCFG1_400MHZ 0xb68e8b63 +#define MDCFG1_533MHZ 0xff738f64 + +/* + * MDCFG2: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tDLLK * 0x1ff (512) 16 0x01ff0000 + * tRTP * 0x3 (4) 6 0x000000c0 + * tWTR * 0x3 (4) 3 0x00000018 + * tRRD * 400MHz 0x3 (4) 0 0x00000003 + * * 533MHz 0x5 (6) 0 0x00000005 + * ---------------------------------------------------------------- + */ +#define MDCFG2_400MHZ 0x01ff00db +#define MDCFG2_533MHZ 0x01ff00dd + +/* + * MDOR: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tXPR 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * SDE_to_RST * 0x10 (14) 8 0x00001000 + * RST_to_CKE * 0x23 (33) 0 0x00000023 + * ---------------------------------------------------------------- + */ +#define MDOR_2G_400MHZ 0x00431023 +#define MDOR_4G_400MHZ 0x007b1023 +#define MDOR_8G_400MHZ 0x008f1023 +#define MDOR_2G_533MHZ 0x005b1023 +#define MDOR_4G_533MHZ 0x00a51023 +#define MDOR_8G_533MHZ 0x00c01023 + +/* + * MDOTC ODT delays: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tAOFPD * 400MHz 0x0 (1) 27 0x00000000 + * * 533MHz 0x1 (2) 27 0x08000000 + * tAONPD * 400MHz 0x0 (1) 24 0x00000000 + * * 533MHz 0x1 (2) 24 0x01000000 + * tANPD * 400MHz 0x3 (4) 20 0x00300000 + * * 533MHz 0x4 (5) 20 0x00400000 + * tAXPD * 400MHz 0x3 (4) 16 0x00030000 + * * 533MHz 0x4 (5) 16 0x00040000 + * tODTLon * 400MHz 0x3 (3) 12 0x00003000 + * * 533MHz 0x4 (4) 12 0x00004000 + * tODTidle_off * 400MHz 0x3 (3) 4 0x00000030 + * * 533MHz 0x4 (4) 4 0x00000040 + * ---------------------------------------------------------------- + */ +#define MDOTC_400MHZ 0x00333030 +#define MDOTC_533MHZ 0x09444040 + +/* + * MDPDC: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * PRCT_1 * 0x0 28 0x00000000 + * PRCT_0 * 0x0 24 0x00000000 + * tCKE * 0x2 (3) 16 0x00020000 + * PWDT_1 * 0x5 (256) 12 0x00005000 + * PWDT_0 * 0x5 (256) 8 0x00000500 + * SLOW_PD * 0x0 (0) 7 0x00000000 + * BOTH_CS_PD * 0x1 (1) 6 0x00000040 + * tCKSRX * 400MHz 0x5 (5) 3 0x00000028 + * * 533MHz 0x6 (6) 3 0x00000030 + * tCKSRE * 400MHz 0x5 (5) 0 0x00000005 + * * 533MHz 0x6 (6) 0 0x00000006 + * ---------------------------------------------------------------- + */ +#define MDPDC_400MHZ 0x0002556d +#define MDPDC_533MHZ 0x00025576 + +/* + * MDCTL: + * 2Gb: CS0 enable, 14bit ROW, 10bit COL, BL=8, 64bit data + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * SDE_0 * 0x1 (1) 31 0x80000000 + * SDE_1 * 0x0 (0) 30 0x00000000 + * ROW 2Gb * 0x3 (14) 24 0x03000000 + * 4Gb * 0x4 (15) 24 0x04000000 + * 8Gb * 0x5 (16) 24 0x05000000 + * COL * 0x1 (10) 20 0x00100000 + * BL * 0x1 (8) 19 0x00080000 + * DSIZ 64bit 0x2 (64) 16 0x00020000 + * DSIZ 32bit 0x1 (32) 16 0x00010000 + * DSIZ 16bit 0x0 (16) 16 0x00000000 + * ---------------------------------------------------------------- + */ +#define MDCTL_2G_16BIT 0x83180000 +#define MDCTL_2G_32BIT 0x83190000 +#define MDCTL_2G 0x831a0000 +#define MDCTL_4G_16BIT 0x84180000 +#define MDCTL_4G_32BIT 0x84190000 +#define MDCTL_4G 0x841a0000 +#define MDCTL_8G 0x851a0000 + +/* + * MDASP Address space partitioning: + * + * At 0.25GiB, internal address space ends. Above that DDR3 should be + * located. The CS1/CS0 split-line determines where: + * + * For 1x2Gb chips (0.25GiB total on CS0): 0.5GiB + * For 2x4Gb chips (1GiB total on CS0): 1.25GiB + * For 4x2Gb chips (1GiB total on CS0): 1.25GiB + * For 4x4Gb chips (2GiB total on CS0): 2.25GiB + * For 4x8Gb chips (4GiB total on CS0): 4.00GiB (maximum possible, + * shadowed partially by internal address space). + * + * Register value Split + * --------------------------- + * 0x0000000f 0.5GiB + * 0x00000017 0.75GiB + * 0x00000027 1.25GiB + * 0x00000047 2.25GiB + * 0x0000007f 4.00GiB + */ +#define MDASP_512MIB 0x0000000f +#define MDASP_768MIB 0x00000017 +#define MDASP_1GIB25 0x00000027 +#define MDASP_2GIB25 0x00000047 +#define MDASP_4GIB00 0x0000007f + +/* + * Initialize DDR3 chips + * MDSCR: Value = 0xvvvv803n, with 0xvvvv = value, n = Reg. number (BA) + */ +/* + * DDR3 chip MR2, n = 2: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Rtt(wr) * 0x0 (disabled) 10, 9 0x0000 + * SR-Temp. * 0x1 (Extended) 7 0x0080 + * Auto-SR * 0x0 (Manual) 6 0x0000 + * CWL * 400MHz 0x0 (5tCK) 5, 4, 3 0x0000 + * * 533MHz 0x1 (6tCK) 5, 4, 3 0x0008 + * ---------------------------------------------------------------- + */ +#define DDR3_MR2_400MHZ_RTT_OFF 0x00808032 +#define DDR3_MR2_533MHZ_RTT_OFF 0x00888032 +#define DDR3_MR2_400MHZ_RTT_120 0x04808032 +#define DDR3_MR2_533MHZ_RTT_120 0x04888032 + +/* + * DDR3 chip MR1, n = 1: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Qoff * 0x0 (enabled) 12 0x0000 + * TDQS * 0x0 (disabled) 11 0x0000 + * Rtt * 0x0 (disabled) 9, 6, 2 0x0000 + * Write-levelling * 0x0 (disable) 7 0x0000 + * ODS * 0x0 (RZQ/6=40) 5, 1 0x0000 + * DLL * 0x0 (enable) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR1_RTT_OFF_ODS_40 0x00008031 +#define DDR3_MR1_RTT_120_ODS_40 0x00408031 +#define DDR3_MR1_RTT_60_ODS_40 0x00048031 +#define DDR3_MR1_RTT_OFF_ODS_34 0x00028031 +#define DDR3_MR1_RTT_120_ODS_34 0x00428031 +#define DDR3_MR1_RTT_60_ODS_34 0x00068031 + +/* + * DDR3 chip MR0, n = 0: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Precharge PD * 0x1 (fast exit) 12 0x1000 + * WR 400MHz 0x2 (6) 11,10,9 0x0400 + * 533MHz 0x4 (8) 11,10,9 0x0800 + * DLL reset * 0x1 (Yes) 8 0x0100 + * CL 400MHz 0x4 (6) 6,5,4,2 0x0020 + * 533MHz 0x6 (7) 6,5,4,2 0x0030 + * 533MHz 0x8 (8) 6,5,4,2 0x0040 + * RD burst type * 0x0 (seq.) 3 0x0000 + * BL * 0x0 (BL8) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR0_400MHZ 0x15208030 +#define DDR3_MR0_533MHZ_CL7 0x19308030 +#define DDR3_MR0_533MHZ_CL8 0x19408030 + + +/* + * MDREF: + * REF_SEL (bit 14,15): 0 (64kHz, needed for high-temp.) + * REFR (bit 11, 12, 13): 0x3 (4 refreshes) -> 0x00001800 + * 0x7 (8 refreshes) -> 0x00003800 + */ +#define MDREF_64KHZ 0x00001800 +#define MDREF_32KHZ 0x00007800 + +/* MPODTCTRL */ +#define MPODTCTRL_ODT_OFF 0x00000007 +#define MPODTCTRL_ODT_120 0x00011117 +#define MPODTCTRL_ODT_60 0x00022227 +#define MPODTCTRL_ODT_40 0x00033337 + +/* + * MPDGCTRL0: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * RST_RD_FIFO * 0 31 0x00000000 + * DG_CMP_CYC * 1 30 0x40000000 + * DG_DIS * 0 29 0x00000000 + * HW_DG_EN * 0 28 0x00000000 + * DG_HC_DEL1 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_EXT_UP * 0 23 0x00000000 + * DG_DL_ABS_OFFS1 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH0_400MHZ 0x42350231 +#define MPDGCTRL0_CH0_533MHZ 0x434b0350 +/* + * + * Channel 1: + * + * DG_HC_DEL1 (5) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS1 (5) 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 (4) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 (4) 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH1_400MHZ 0x42350231 +#define MPDGCTRL0_CH1_533MHZ 0x434b0350 + +/* + * MPDGCTRL1: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * DG_HC_DEL3 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x4c 16 0x004c0000 + * DG_HC_DEL2 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 400MHz 0x18 0 0x00000018 + * 533MHz 0x59 0 0x00000059 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH0_400MHZ 0x021a0218 +#define MPDGCTRL1_CH0_533MHZ 0x034c0359 +/* + * + * Channel 1: + * + * DG_HC_DEL3 (7) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 (7) 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x65 16 0x00650000 + * DG_HC_DEL2 (6) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 (6) 400MHz 0x18 0 0x00000018 + * 533MHz 0x48 0 0x00000048 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH1_400MHZ 0x021a0218 +#define MPDGCTRL1_CH1_533MHZ 0x03650348 diff --git a/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg new file mode 100644 index 0000000000..c778391d75 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-alti6p.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: ALTI6P doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg new file mode 100644 index 0000000000..b08e149834 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-lanmcu.imxcfg @@ -0,0 +1,115 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug 0 LED */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e060c 0x000130b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg new file mode 100644 index 0000000000..dbbb9818b6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-plybas.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg new file mode 100644 index 0000000000..dbbb9818b6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-plym2m.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg new file mode 100644 index 0000000000..ec9fb84108 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prti6g.imxcfg @@ -0,0 +1,81 @@ +soc imx6 +loadaddr 0x80000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" +#include "padsetup-ul.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 0x00000047 /* MDASP_512MIB */ +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000117 /* MPODTCTRL_ODT_120 */ + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b0850 0x40404040 /* For now set all to 50%. */ + +/* MPWLDECTRL0 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff diff --git a/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg new file mode 100644 index 0000000000..68b7909f82 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prti6q.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +wm 32 0x020e0244 0x00000005 +wm 32 0x020e05f8 0x000130b0 +wm 32 0x020e0614 0x0001b0b0 + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00000742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_8G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_8G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_4GIB00 +wm 32 0x021b0000 MDCTL_8G + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +wm 32 0x021b083c MPDGCTRL0_CH0_533MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_533MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_533MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_533MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ +wm 32 0x020e07ac 0x00000200 /* 60 Ohm ODT */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg new file mode 100644 index 0000000000..1131174f70 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtmvt.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg new file mode 100644 index 0000000000..dbbb9818b6 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtrvt.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_512MIB +wm 32 0x021b0000 MDCTL_2G_16BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg new file mode 100644 index 0000000000..019696295d --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtvt7.imxcfg @@ -0,0 +1,115 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug 0 LED */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e060c 0x000130b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_2G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_2G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_768MIB +wm 32 0x021b0000 MDCTL_2G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg new file mode 100644 index 0000000000..5f847c004d --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtwd2.imxcfg @@ -0,0 +1,229 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "lpddr2-defines.imxcfg" + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* Set DDR clk to 400MHz. */ +wm 32 0x020c4018 0x00060324 + +/* #include "padsetup-q.imxcfg" */ + +/* LPDDR2 i.MX6D/Q pad setup */ +wm 32 0x020e0798 0x00080000 +wm 32 0x020e0758 0x00000000 + +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 + +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 + +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 + +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00003030 +wm 32 0x020e05b0 0x00003030 +wm 32 0x020e0524 0x00003030 +wm 32 0x020e051c 0x00003030 +wm 32 0x020e0518 0x00003030 +wm 32 0x020e050c 0x00003030 +wm 32 0x020e05b8 0x00003030 +wm 32 0x020e05c0 0x00003030 + +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 + +wm 32 0x020e05ac 0x00000030 +wm 32 0x020e05b4 0x00000030 +wm 32 0x020e0528 0x00000030 +wm 32 0x020e0520 0x00000030 +wm 32 0x020e0514 0x00000030 +wm 32 0x020e0510 0x00000030 +wm 32 0x020e05bc 0x00000030 +wm 32 0x020e05c4 0x00000030 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 +wm 32 0x021b401c 0x00008000 +/* check 32 until_any_bit_set 0x021b401c 0x00004000 */ + + +wm 32 0x021b085c 0x1b4700c7 +wm 32 0x021b485c 0x1b4700c7 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0890 0x00400000 +wm 32 0x021b4890 0x00400000 + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +wm 32 0x021b083c 0x20000000 +wm 32 0x021b0840 0x00000000 +wm 32 0x021b483c 0x20000000 +wm 32 0x021b4840 0x00000000 + + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* Set Write data delay 3 delay units for all bits */ +wm 32 0x021b082c 0xf3333333 +wm 32 0x021b0830 0xf3333333 +wm 32 0x021b0834 0xf3333333 +wm 32 0x021b0838 0xf3333333 +wm 32 0x021b482c 0xf3333333 +wm 32 0x021b4830 0xf3333333 +wm 32 0x021b4834 0xf3333333 +wm 32 0x021b4838 0xf3333333 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* + * Configure MMDC Channel 0 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b0018 0x00001602 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b000c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b0010 MDCFG1_LPDDR2 +wm 32 0x021b0014 MDCFG2_LPDDR2 + +wm 32 0x021b0018 0x0000174c +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b0030 MDOR_LPDDR2 +wm 32 0x021b0038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b0040 0x0000004f /* NOTE: According to RM */ +wm 32 0x021b0400 0x11420000 /* MAARCR disable dyn jump */ +wm 32 0x021b0000 MDCTL_LPDDR2 + +/* + * Configure MMDC Channel 1 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b4018 0x00001602 +check 32 until_all_bits_clear 0x021b4018 0x00000002 + +wm 32 0x021b4004 0x00020036 +wm 32 0x021b4008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b400c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b4010 MDCFG1_LPDDR2 +wm 32 0x021b4014 MDCFG2_LPDDR2 + +wm 32 0x021b4018 0x0000174c +wm 32 0x021b401c 0x00008000 +wm 32 0x021b402c 0x0f9f26d2 /* MDOR */ +wm 32 0x021b4030 MDOR_LPDDR2 +wm 32 0x021b4038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b4040 MDASP_768MIB /* NOTE: According to RM */ +wm 32 0x021b4400 0x11420000 /* MAARCR disable dyn jump */ +wm 32 0x021b4000 MDCTL_LPDDR2 + +/* + * Configure LPDDR2 devices + */ + +wm 32 0x021b001c 0x00008010 /* Precharge all ch 0 */ +wm 32 0x021b401c 0x00008010 /* Precharge all ch 1 */ + +/* Channel 0 */ +wm 32 0x021b001c 0x003f8030 /* Reset */ +wm 32 0x021b001c 0xff0a8030 /* Calibrate */ +wm 32 0x021b001c 0x82018030 /* MR1: nWR=6, WC=0, BT=0, BL=BL4 */ +wm 32 0x021b001c 0x04028030 /* MR2: RL6/WL3 */ +wm 32 0x021b001c 0x02038030 /* MR3: DS = 40 Ohm */ + +/* Channel 1 */ +wm 32 0x021b401c 0x003f8030 +wm 32 0x021b401c 0xff0a8030 +wm 32 0x021b401c 0x82018030 +wm 32 0x021b401c 0x04028030 +wm 32 0x021b401c 0x02038030 + +/* MPDGCTRL disabled, reset fifos */ +wm 32 0x021b083c 0xa0000000 +wm 32 0x021b083c 0xa0000000 +check 32 until_all_bits_clear 0x021b083c 0x80000000 +wm 32 0x021b483c 0xa0000000 +wm 32 0x021b483c 0xa0000000 +check 32 until_all_bits_clear 0x021b483c 0x80000000 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0020 MDREF_64KHZ +wm 32 0x021b4020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000000 /* LPDDR2: Disable ODT! */ +wm 32 0x021b4818 0x00000000 + +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b4004 MDPDC_400MHZ + +/* MAPSR */ +wm 32 0x021b0404 0x00011006 /* Enable autorefresh */ +wm 32 0x021b4404 0x00011006 /* Enable autorefresh */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ +wm 32 0x021b401c 0x00000000 /* Disable configuration req */ + + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* configure 100K pull down on USB_ETH_CHG -> ADC_ICHG */ +wm 32 0x020e06cc 0x000130f9 diff --git a/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg new file mode 100644 index 0000000000..054043cc80 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-prtwd3.imxcfg @@ -0,0 +1,280 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "lpddr2-defines.imxcfg" + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* Set DDR clk to 400MHz. */ +wm 32 0x020c4018 0x00060324 + +/* #include "padsetup-q.imxcfg" */ + +/* LPDDR2 i.MX6D/Q pad setup */ +wm 32 0x020e0798 0x00080000 +wm 32 0x020e0758 0x00000000 + +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 + +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 + +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e078c 0x00000030 + +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00003030 +wm 32 0x020e05b0 0x00003030 +wm 32 0x020e0524 0x00003030 +wm 32 0x020e051c 0x00003030 +wm 32 0x020e0518 0x00003030 +wm 32 0x020e050c 0x00003030 +wm 32 0x020e05b8 0x00003030 +wm 32 0x020e05c0 0x00003030 + +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 + +wm 32 0x020e05ac 0x00000030 +wm 32 0x020e05b4 0x00000030 +wm 32 0x020e0528 0x00000030 +wm 32 0x020e0520 0x00000030 +wm 32 0x020e0514 0x00000030 +wm 32 0x020e0510 0x00000030 +wm 32 0x020e05bc 0x00000030 +wm 32 0x020e05c4 0x00000030 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 +wm 32 0x021b401c 0x00008000 +/* check 32 until_any_bit_set 0x021b401c 0x00004000 */ + + +wm 32 0x021b085c 0x1b4700c7 +wm 32 0x021b485c 0x1b4700c7 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0890 0x00400000 +wm 32 0x021b4890 0x00400000 + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +wm 32 0x021b083c 0x20000000 +wm 32 0x021b0840 0x00000000 +wm 32 0x021b483c 0x20000000 +wm 32 0x021b4840 0x00000000 + + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* Set Write data delay 3 delay units for all bits */ +wm 32 0x021b082c 0xf3333333 +wm 32 0x021b0830 0xf3333333 +wm 32 0x021b0834 0xf3333333 +wm 32 0x021b0838 0xf3333333 +wm 32 0x021b482c 0xf3333333 +wm 32 0x021b4830 0xf3333333 +wm 32 0x021b4834 0xf3333333 +wm 32 0x021b4838 0xf3333333 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* NOC: DDRCONF */ +/* Sabre-auto: wm 32 0x00bb0008 0x00000000 */ +/* Values (Address mapping for 64bit): + * 0 : 16 Row, 3 Bank, 10 Col interleave (11 Col for 32 bit) + * 1 : 15 Row, 3 Bank, 11 Col interleave (12 Col for 32 bit) + * 2 : 18 Row, 3 Bank, 8 Col interleave (9 Col for 32 bit) + * 3 : 17 Row, 3 Bank, 9 Col interleave (10 Col for 32 bit) + * 4 : 2 CS (?), 15 Row, 3 Bank, 10 Col, interleave + * ... + */ +wm 32 0x00bb0008 0x00000000 + +/* + * NOC DdrTiming: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * ActToAct 533MHz 0x1b (28) 0 0x0000001b + * LPDDR2 0x18 (24) 0 0x00000018 + * RdToMiss 533MHz 0x10 (16) 6 0x00000400 + * LPDDR2 0x11 (17) 6 0x00000440 + * WrToMiss * 0x1e (30) 12 0x0001e000 + * LPDDR2 0x19 (25) 12 0x00019000 + * BurstLen * 0x4 (8/2) 18 0x00100000 + * LPDDR2 0x2 (4/2) 18 0x00080000 + * RdToWr * 0x3 (3) 21 0x00600000 + * LPDDR2 0x5 (5) 21 0x00a00000 + * WrToRd * 0xa (10) 26 0x28000000 + * LPDDR2 0x6 (6) 26 0x18000000 + * BwRatio * 0x0 (0) 31 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb000c 0x2891E41A */ +wm 32 0x00bb000c 0x18a99459 + +/* + * NOC Activate: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * Rrd * 0x6 (6) 0 0x00000006 + * LPDDR2 0x4 (4) 0 0x00000004 + * Faw * 0x1b (27) 4 0x000001b0 + * LPDDR2 0x14 (20) 4 0x00000140 + * FawBank * 0x0 (0) 10 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb0038 0x00000564 */ +wm 32 0x00bb0038 0x00000144 + +/* + * NOC ReadLatency: (FIXME) + */ +wm 32 0x00bb0014 0x00000040 + +/* + * Configure MMDC Channel 0 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b0018 0x00001602 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b000c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b0010 MDCFG1_LPDDR2 +wm 32 0x021b0014 MDCFG2_LPDDR2 + +wm 32 0x021b0018 0x0000174c +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b0030 MDOR_LPDDR2 +wm 32 0x021b0038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b0040 0x0000004f /* NOTE: According to RM */ +wm 32 0x021b0400 0x15420000 /* MAARCR disable dyn jump/reordering */ +wm 32 0x021b0000 MDCTL_LPDDR2 + +/* + * Configure MMDC Channel 1 + */ + +/* MDMISC No addr mirror, 0 WALAT, 5 RALAT, LPDDR2 mode, RST */ +wm 32 0x021b4018 0x00001602 +check 32 until_all_bits_clear 0x021b4018 0x00000002 + +wm 32 0x021b4004 0x00020036 +wm 32 0x021b4008 0x12272000 /* FIXME: Why does script aid set this? */ +wm 32 0x021b400c MDCFG0_8G_LPDDR2_CL6 +wm 32 0x021b4010 MDCFG1_LPDDR2 +wm 32 0x021b4014 MDCFG2_LPDDR2 + +wm 32 0x021b4018 0x0000174c +wm 32 0x021b401c 0x00008000 +wm 32 0x021b402c 0x0f9f26d2 /* MDRWD */ +wm 32 0x021b4030 MDOR_LPDDR2 +wm 32 0x021b4038 0x00190778 /* MDCFG3LP */ +wm 32 0x021b4040 MDASP_768MIB /* NOTE: According to RM */ +wm 32 0x021b4400 0x15420000 /* MAARCR disable dyn jump/reordering */ +wm 32 0x021b4000 MDCTL_LPDDR2 + +/* + * Configure LPDDR2 devices + */ + +wm 32 0x021b001c 0x00008010 /* Precharge all ch 0 */ +wm 32 0x021b401c 0x00008010 /* Precharge all ch 1 */ + +/* Channel 0 */ +wm 32 0x021b001c 0x003f8030 /* Reset */ +wm 32 0x021b001c 0xff0a8030 /* Calibrate */ +wm 32 0x021b001c 0x82018030 /* MR1: nWR=6, WC=0, BT=0, BL=BL4 */ +wm 32 0x021b001c 0x04028030 /* MR2: RL6/WL3 */ +wm 32 0x021b001c 0x02038030 /* MR3: DS = 40 Ohm */ + +/* Channel 1 */ +wm 32 0x021b401c 0x003f8030 +wm 32 0x021b401c 0xff0a8030 +wm 32 0x021b401c 0x82018030 +wm 32 0x021b401c 0x04028030 +wm 32 0x021b401c 0x02038030 + +/* MPDGCTRL disabled, reset fifos */ +wm 32 0x021b083c 0xa0000000 +wm 32 0x021b083c 0xa0000000 +check 32 until_all_bits_clear 0x021b083c 0x80000000 +wm 32 0x021b483c 0xa0000000 +wm 32 0x021b483c 0xa0000000 +check 32 until_all_bits_clear 0x021b483c 0x80000000 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1380003 /* FIXME: Why different? */ + +wm 32 0x021b0020 MDREF_64KHZ +wm 32 0x021b4020 MDREF_64KHZ + +wm 32 0x021b0818 0x00000000 /* LPDDR2: Disable ODT! */ +wm 32 0x021b4818 0x00000000 + +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b4004 MDPDC_400MHZ + +/* MAPSR */ +wm 32 0x021b0404 0x00011006 /* Enable autorefresh */ +wm 32 0x021b4404 0x00011006 /* Enable autorefresh */ + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ +wm 32 0x021b401c 0x00000000 /* Disable configuration req */ + + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* configure 100K pull down on USB_ETH_CHG -> ADC_ICHG */ +wm 32 0x020e06cc 0x000130f9 diff --git a/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg new file mode 100644 index 0000000000..d3de7b6aab --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-victgo.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_1GIB25 +wm 32 0x021b0000 MDCTL_4G_32BIT + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config: MVT doesn't have GRMII, disable! */ +wm 32 0x020e0768 0x000c0000 /* 1V5 DDR IO */ +wm 32 0x020e0788 0x00000000 /* disable ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg new file mode 100644 index 0000000000..9926fbf4a2 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicut1.imxcfg @@ -0,0 +1,123 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x000130b0 +wm 32 0x020e0610 0x0001f0b0 + +#include "padsetup-dl.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011740 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 + +wm 32 0x021b000c MDCFG0_4G_400MHZ +wm 32 0x021b0010 MDCFG1_400MHZ +wm 32 0x021b0014 MDCFG2_400MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_400MHZ +wm 32 0x021b0008 MDOTC_400MHZ +wm 32 0x021b0004 MDPDC_400MHZ +wm 32 0x021b0040 MDASP_2GIB25 +wm 32 0x021b0000 MDCTL_4G + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_400MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_400MHZ + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_120 +wm 32 0x021b4818 MPODTCTRL_ODT_120 + +wm 32 0x021b083c MPDGCTRL0_CH0_400MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_400MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_400MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_400MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x00440044 /* FIXME: Why these seeminly arbitrary values? */ +wm 32 0x021b4810 0x00440044 + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00011007 /* 0x0001...? FIXME: Disable powersaving for now */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* RGMII config */ +wm 32 0x020e0768 0x00080000 /* 1V2 DDR IO */ +wm 32 0x020e0788 0x00000200 /* 60 Ohm ODT */ + +/* Debug */ +wm 32 0x020e023c 0x00000005 +wm 32 0x020e0240 0x00000005 +wm 32 0x020e060c 0x0001f0b0 +wm 32 0x020e0610 0x000130b0 diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg new file mode 100644 index 0000000000..a73a2c6fd0 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicut1q.imxcfg @@ -0,0 +1,127 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +/* wm 32 0x020e0244 0x00000005 */ +wm 32 0x020e05f8 0x000130b0 +/* wm 32 0x020e0614 0x000130b0 */ + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00011742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_8G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_8G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_4GIB00 +wm 32 0x021b0000 MDCTL_8G +// check 32 until_any_bit_set 0x021b0018 0x80000000 + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +/* DQS gating calibration measured on UT2 and UTC boards */ +wm 32 0x021b083c 0x43000300 +wm 32 0x021b483c 0x430a0310 + +wm 32 0x021b0840 0x030002b0 +wm 32 0x021b4840 0x02b00255 + +/* MPRDDLCTL, MPWRDLCTL */ +/* Measured on UT2 and UTC, good averages */ +wm 32 0x021b0848 0x453a3a3a +wm 32 0x021b4848 0x403b3947 +wm 32 0x021b0850 0x40444540 +wm 32 0x021b4850 0x46404840 + +/* MPWLDECTRL0,1 */ +/* Measured and averaged on UT2 and UTC boards */ +wm 32 0x021b080c 0x00200020 +wm 32 0x021b0810 0x0026001e +wm 32 0x021b480c 0x00100028 +wm 32 0x021b4810 0x0012001b + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* Clock configuration (CCM) */ +/* CCGR0..6 */ +wm 32 0x020c4068 0x00c03f3f +wm 32 0x020c406c 0x0030fc03 +wm 32 0x020c4070 0x0fffc000 +wm 32 0x020c4074 0x3ff00000 +wm 32 0x020c4078 0x00fff300 +wm 32 0x020c407c 0x0f0000c3 +wm 32 0x020c4080 0x000003ff + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ +wm 32 0x020e07ac 0x00000200 /* 60 Ohm ODT */ diff --git a/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg b/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg new file mode 100644 index 0000000000..13887ade0b --- /dev/null +++ b/arch/arm/boards/protonic-imx6/flash-header-vicutp.imxcfg @@ -0,0 +1,174 @@ +soc imx6 +loadaddr 0x10000000 +ivtofs 0x400 + +#include "ddr3-defines.imxcfg" + +/* Debug */ +wm 32 0x020e0228 0x00000005 +/* wm 32 0x020e0244 0x00000005 */ +wm 32 0x020e05f8 0x000130b0 +/* wm 32 0x020e0614 0x000130b0 */ + +#include "padsetup-q.imxcfg" + +/* Set Read data delay 3 delay units for all bits */ +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 + +/* MDMISC No addr mirror, 1 WALAT, 5 RALAT, DDR3 mode */ +wm 32 0x021b0018 0x00001742 +check 32 until_all_bits_clear 0x021b0018 0x00000002 + +/* CSCR: Configuration mode */ +wm 32 0x021b001c 0x00008000 +check 32 until_any_bit_set 0x021b001c 0x00004000 + +wm 32 0x021b000c MDCFG0_4G_533MHZ_CL7 +wm 32 0x021b0010 MDCFG1_533MHZ +wm 32 0x021b0014 MDCFG2_533MHZ + +/* MDRWD */ +wm 32 0x021b002c 0x000026d2 + +wm 32 0x021b0030 MDOR_4G_533MHZ +wm 32 0x021b0008 MDOTC_533MHZ +wm 32 0x021b0004 MDPDC_533MHZ +wm 32 0x021b0040 MDASP_2GIB25 + +/* Dual-Plus specific configuration */ +/* MMDC: MAARCR: Disable reordering */ +wm 32 0x021b0400 0x14420000 +/* MMDC: MPPDCMPR2: ZQ Offset setting (TODO) */ +wm 32 0x021b0890 0x00400008 /* Freescale sabre-auto: 0x00400C58 */ + +/* NOC: DDRCONF */ +/* Sabre-auto: wm 32 0x00bb0008 0x00000000 */ +/* Values (Address mapping for 64bit): + * 0 : 16 Row, 3 Bank, 10 Col interleave (11 Col for 32 bit) + * 1 : 15 Row, 3 Bank, 11 Col interleave (12 Col for 32 bit) + * 2 : 18 Row, 3 Bank, 8 Col interleave (9 Col for 32 bit) + * 3 : 17 Row, 3 Bank, 9 Col interleave (10 Col for 32 bit) + * 4 : 2 CS (?), 15 Row, 3 Bank, 10 Col, interleave + * ... + */ +wm 32 0x00bb0008 0x00000000 + +/* + * NOC DdrTiming: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * ActToAct 533MHz 0x1b (28) 0 0x0000001b + * RdToMiss 533MHz 0x10 (16) 6 0x00000400 + * WrToMiss * 0x1e (30) 12 0x0001e000 + * BurstLen * 0x4 (8/2) 18 0x00100000 + * RdToWr * 0x3 (3) 21 0x00600000 + * WrToRd * 0xa (10) 26 0x28000000 + * BwRatio * 0x0 (0) 31 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb000c 0x2891E41A */ +wm 32 0x00bb000c 0x2871e41c + +/* + * NOC Activate: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * Rrd * 0x6 (6) 0 0x00000006 + * Faw * 0x1b (27) 4 0x000001b0 + * FawBank * 0x0 (0) 10 0x00000000 + * ---------------------------------------------------------------- + */ +/* Sabre-auto: wm 32 0x00bb0038 0x00000564 */ +wm 32 0x00bb0038 0x000001b6 + +/* + * NOC ReadLatency: (FIXME) + */ +wm 32 0x00bb0014 0x00000040 + +/* + * NOC IPU1/IPU2 aging: (FIXME) + */ +wm 32 0x00bb0028 0x00000020 +wm 32 0x00bb002c 0x00000020 + +wm 32 0x021b0000 MDCTL_4G +// check 32 until_any_bit_set 0x021b0018 0x80000000 + +/* DDR3 MR config */ +wm 32 0x021b001c DDR3_MR2_533MHZ_RTT_120 + +/* + * DDR3 chip MR3, n = 3, vvvv = 0 (no configurable function of interest). + */ +wm 32 0x021b001c 0x00008033 + +wm 32 0x021b001c DDR3_MR1_RTT_120_ODS_40 +wm 32 0x021b001c DDR3_MR0_533MHZ_CL7 + +/* + * ZQ calibration, n = 0x10 (Precharge all): + * Bit 10 = 1: Start ZQ calibration + * REGISTER: 0x04008040 + */ +wm 32 0x021b001c 0x04008040 + +/* MPZQHWCTRL */ +wm 32 0x021b0800 0xa1390003 /* ZQ mode = 3 force calibration */ +wm 32 0x021b4800 0xa1390003 + +wm 32 0x021b0020 MDREF_64KHZ + +wm 32 0x021b0818 MPODTCTRL_ODT_60 +wm 32 0x021b4818 MPODTCTRL_ODT_60 + +wm 32 0x021b083c MPDGCTRL0_CH0_533MHZ +wm 32 0x021b483c MPDGCTRL0_CH1_533MHZ + +wm 32 0x021b0840 MPDGCTRL1_CH0_533MHZ +wm 32 0x021b4840 MPDGCTRL1_CH1_533MHZ + +/* MPRDDLCTL, MPWRDLCTL */ +wm 32 0x021b0848 0x40404040 /* TODO. Read delay line conf. */ +wm 32 0x021b4848 0x40404040 /* For now set all to 50%. */ +wm 32 0x021b0850 0x40404040 +wm 32 0x021b4850 0x40404040 + +/* MPWLDECTRL0,1 */ +wm 32 0x021b080c 0x001f001f /* TODO. Write level delay control */ +wm 32 0x021b0810 0x001f001f +wm 32 0x021b480c 0x001f001f +wm 32 0x021b4810 0x001f001f + +/* MPMUR0 */ +wm 32 0x021b08b8 0x00000800 /* Force measurement on delay lines */ +wm 32 0x021b48b8 0x00000800 + +/* MDSCR */ +wm 32 0x021b001c 0x00000000 /* Disable configuration req */ + +/* MAPSR */ +wm 32 0x021b0404 0x00001006 /* Enable autorefresh */ + +/* enable AXI cache for VDOA/PCIe/VPU/IPU */ +wm 32 0x020e0010 0xff0000cf +/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7) */ +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f + +/* DEBUG leds */ +wm 32 0x020e0244 0x00000005 +wm 32 0x020e0614 0x000130b0 + +/* RGMII config */ +wm 32 0x020e0790 0x00080000 /* 1V2 DDR IO */ +wm 32 0x020e07ac 0x00000200 /* 60 Ohm ODT */ diff --git a/arch/arm/boards/protonic-imx6/lowlevel.c b/arch/arm/boards/protonic-imx6/lowlevel.c new file mode 100644 index 0000000000..f5784cc6b1 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/lowlevel.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 Protonic Holland + * Copyright (C) 2020 Oleksij Rempel, Pengutronix + */ + +#include <asm/barebox-arm.h> +#include <common.h> +#include <mach/esdctl.h> +#include <mach/generic.h> + +extern char __dtb_z_imx6q_prti6q_start[]; +extern char __dtb_z_imx6q_prtwd2_start[]; +extern char __dtb_z_imx6q_vicut1_start[]; +extern char __dtb_z_imx6dl_alti6p_start[]; +extern char __dtb_z_imx6dl_lanmcu_start[]; +extern char __dtb_z_imx6dl_plybas_start[]; +extern char __dtb_z_imx6dl_plym2m_start[]; +extern char __dtb_z_imx6dl_prtmvt_start[]; +extern char __dtb_z_imx6dl_prtrvt_start[]; +extern char __dtb_z_imx6dl_prtvt7_start[]; +extern char __dtb_z_imx6dl_victgo_start[]; +extern char __dtb_z_imx6dl_vicut1_start[]; +extern char __dtb_z_imx6qp_prtwd3_start[]; +extern char __dtb_z_imx6qp_vicutp_start[]; +extern char __dtb_z_imx6ul_prti6g_start[]; + +ENTRY_FUNCTION(start_imx6q_prti6q, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_prti6q_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6q_prtwd2, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_prtwd2_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6q_vicut1, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6q_vicut1_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_alti6p, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_alti6p_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_lanmcu, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_lanmcu_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_plybas, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_plybas_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_plym2m, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_plym2m_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtmvt, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtmvt_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtrvt, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtrvt_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_prtvt7, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_prtvt7_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_victgo, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_victgo_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6dl_vicut1, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6dl_vicut1_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6qp_prtwd3, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6qp_prtwd3_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6qp_vicutp, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6qp_vicutp_start + get_runtime_offset(); + + imx6q_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_imx6ul_prti6g, r0, r1, r2) +{ + void *fdt; + + imx6ul_cpu_lowlevel_init(); + + fdt = __dtb_z_imx6ul_prti6g_start + get_runtime_offset(); + + imx6ul_barebox_entry(fdt); +} diff --git a/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg b/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg new file mode 100644 index 0000000000..29c42cc697 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/lpddr2-defines.imxcfg @@ -0,0 +1,384 @@ +/* + * Timing configuration: + * + * MDCFG0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRFC 2Gb 400MHz 0x3f (64) 24 0x3f000000 + * 4Gb 400MHz 0x77 (120) 24 0x77000000 + * 8Gb 400MHz 0x8b (140) 24 0x8b000000 + * 2Gb 533MHz 0x55 (86) 24 0x55000000 + * 4Gb 533MHz 0x9f (160) 24 0x9f000000 + * 8Gb 533MHz 0xba (187) 24 0xba000000 + * 4Gb LPDDR2 0x33 (52) 24 0x33000000 + * tXS 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * 4Gb LPDDR2 0x37 (56) 16 0x00370000 + * tXP * 400MHz 0x2 (3) 13 0x00004000 + * * 533MHz 0x3 (4) 13 0x00006000 + * * LPDDR2 0x2 (3) 13 0x00004000 + * tXPDLL * 400MHz 0x9 (10) 9 0x00001200 + * * 533MHz 0xc (13) 9 0x00001800 + * * LPDDR2 0x1 (-) 9 0x00000200 + * tFAW * 400MHz 0x13 (20) 4 0x00000130 + * * 533MHz 0x1a (27) 4 0x000001a0 + * * LPDDR2 0x13 (20) 4 0x00000130 + * tCL * 400MHz 0x3 (6) 0 0x00000003 + * * 533MHz-CL7 0x4 (7) 0 0x00000004 + * * 533MHz-CL8 0x5 (8) 0 0x00000005 + * * LPDDR2 0x3 (6) 0 0x00000003 + * ---------------------------------------------------------------- + */ +#define MDCFG0_2G_400MHZ 0x3f435333 +#define MDCFG0_4G_400MHZ 0x777b5333 +#define MDCFG0_8G_400MHZ 0x8b8f5333 +#define MDCFG0_2G_533MHZ_CL8 0x555b79a5 +#define MDCFG0_2G_533MHZ_CL7 0x555b79a4 +#define MDCFG0_4G_533MHZ_CL8 0x9fa579a5 +#define MDCFG0_4G_533MHZ_CL7 0x9fa579a4 +#define MDCFG0_8G_533MHZ_CL8 0xbac079a5 +#define MDCFG0_8G_533MHZ_CL7 0xbac079a4 +#define MDCFG0_4G_LPDDR2_CL6 0x33374133 +#define MDCFG0_8G_LPDDR2_CL6 0x53574133 + + +/* + * MDCFG1: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tRCD * 400MHz 0x5 (6) 28 0xa0000000 + * * 533MHz 0x7 (8) 28 0xe0000000 + * * LPDDR2 0x5 (-) 28 0xa0000000 + * tRP * 400MHz 0x5 (6) 26 0x14000000 + * * 533MHz 0x7 (8) 26 0x1c000000 + * * LPDDR2 0x5 (-) 26 0x14000000 + * tRC * 400MHz 0x14 (21) 21 0x02800000 + * * 533MHz 0x1b (28) 21 0x03600000 + * * LPDDR2 0x15 (-) 21 0x02a00000 + * tRAS * 400MHz 0x0e (15) 16 0x000e0000 + * * 533MHz 0x13 (20) 16 0x00130000 + * * LPDDR2 0x10 (17) 16 0x00100000 + * tRPA * 0x1 (tRP+1) 15 0x00008000 + * RM rev 4: unused, read-only! 15 0x00000000 + * tWR * 400MHz 0x5 (6) 9 0x00000a00 + * * 533MHz 0x7 (8) 9 0x00000e00 + * * LPDDR2 0x5 (6) 9 0x00000a00 + * tMRD * 0x3 (4) 5 0x00000060 + * max(tMRR,tMRW) LPDDR2 0x4 (5) 5 0x00000080 + * tCWL * 400MHz 0x3 (5) 0 0x00000003 + * * 533MHz 0x4 (6) 0 0x00000004 + * tWL * LPDDR2 0x2 (3) 0 0x00000002 + * ---------------------------------------------------------------- + */ +#define MDCFG1_400MHZ 0xb68e8a63 +#define MDCFG1_533MHZ 0xff738e64 +#define MDCFG1_LPDDR2 0x00100a82 + +/* + * MDCFG2: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tDLLK * 0x1ff (512) 16 0x01ff0000 + * LPDDR2 0x0c7 (-) 16 0x00c70000 + * tRTP * 0x3 (4) 6 0x000000c0 + * LPDDR2 0x2 (3) 6 0x00000080 + * tWTR * 0x3 (4) 3 0x00000018 + * LPDDR2 0x2 (3) 3 0x00000010 + * tRRD * 400MHz 0x3 (4) 0 0x00000003 + * * 533MHz 0x5 (6) 0 0x00000005 + * LPDDR2 0x3 (4) 0 0x00000003 + * ---------------------------------------------------------------- + */ +#define MDCFG2_400MHZ 0x01ff00db +#define MDCFG2_533MHZ 0x01ff00dd +#define MDCFG2_LPDDR2 0x00000093 + +/* + * MDOR: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tXPR 2Gb 400MHz 0x43 (68) 16 0x00430000 + * 4Gb 400MHz 0x7b (124) 16 0x007b0000 + * 8Gb 400MHz 0x8f (144) 16 0x008f0000 + * 2Gb 533MHz 0x5b (92) 16 0x005b0000 + * 4Gb 533MHz 0xa5 (166) 16 0x00a50000 + * 8Gb 533MHz 0xc0 (193) 16 0x00c00000 + * * LPDDR2 0x9f (-) 16 0x009f0000 + * SDE_to_RST * 0x10 (14) 8 0x00001000 + * * LPDDR2 0xe (-) 8 0x00000e00 + * RST_to_CKE * 0x23 (33) 0 0x00000023 + * * LPDDR2 0x10 (14) 0 0x00000010 + * ---------------------------------------------------------------- + */ +#define MDOR_2G_400MHZ 0x00431023 +#define MDOR_4G_400MHZ 0x007b1023 +#define MDOR_8G_400MHZ 0x008f1023 +#define MDOR_2G_533MHZ 0x005b1023 +#define MDOR_4G_533MHZ 0x00a51023 +#define MDOR_8G_533MHZ 0x00c01023 +#define MDOR_LPDDR2 0x009f0e10 + +/* + * MDOTC ODT delays: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * tAOFPD * 400MHz 0x3 (4) 27 0x18000000 + * * 533MHz 0x4 (5) 27 0x20000000 + * tAONPD * 400MHz 0x3 (4) 24 0x03000000 + * * 533MHz 0x4 (5) 24 0x04000000 + * tANPD * 400MHz 0x3 (4) 20 0x00300000 + * * 533MHz 0x4 (5) 20 0x00400000 + * tAXPD * 400MHz 0x3 (4) 16 0x00030000 + * * 533MHz 0x4 (5) 16 0x00040000 + * tODTLon * 400MHz 0x3 (3) 12 0x00003000 + * * 533MHz 0x4 (4) 12 0x00004000 + * tODTidle_off * 400MHz 0x3 (3) 4 0x00000030 + * * 533MHz 0x4 (4) 4 0x00000040 + * ---------------------------------------------------------------- + */ +#define MDOTC_400MHZ 0x1b333030 +#define MDOTC_533MHZ 0x24444040 +/* LPDDR2: not relevant, leave in reset state!! */ + +/* + * MDPDC: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * PRCT_1 * 0x0 28 0x00000000 + * PRCT_0 * 0x0 24 0x00000000 + * tCKE * 0x2 (3) 16 0x00020000 + * PWDT_1 * 0x5 (256) 12 0x00005000 + * PWDT_0 * 0x5 (256) 8 0x00000500 + * SLOW_PD * 0x0 (0) 7 0x00000000 + * BOTH_CS_PD * 0x1 (1) 6 0x00000040 + * tCKSRX * 400MHz 0x5 (5) 3 0x00000028 + * * 533MHz 0x6 (6) 3 0x00000030 + * tCKSRE * 400MHz 0x5 (5) 0 0x00000005 + * * 533MHz 0x6 (6) 0 0x00000006 + * ---------------------------------------------------------------- + */ +#define MDPDC_400MHZ 0x0002556d +#define MDPDC_533MHZ 0x00025576 +#define MDPDC_LPDDR2 0x00025576 /* FIXME? */ + +/* + * MDCTL: + * 2Gb: CS0 enable, 14bit ROW, 10bit COL, BL=8, 64bit data + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * SDE_0 * 0x1 (1) 31 0x80000000 + * SDE_1 * 0x0 (0) 30 0x00000000 + * SDE_1 LPDDR2 0x1 (1) 30 0x40000000 + * ROW 2Gb * 0x3 (14) 24 0x03000000 + * 4Gb * 0x4 (15) 24 0x04000000 + * 8Gb * 0x5 (16) 24 0x05000000 + * * LPDDR2 0x3 (14) 24 0x03000000 + * COL * 0x1 (10) 20 0x00100000 + * BL * 0x1 (8) 19 0x00080000 + * LPDDR2 0x0 (4) 19 0x00000000 + * DSIZ 64bit 0x2 (64) 16 0x00020000 + * DSIZ 32bit 0x1 (32) 16 0x00010000 + * DSIZ 16bit 0x0 (16) 16 0x00000000 + * ---------------------------------------------------------------- + */ +#define MDCTL_2G_16BIT 0x83180000 +#define MDCTL_2G_32BIT 0x83190000 +#define MDCTL_2G 0x831a0000 +#define MDCTL_4G_16BIT 0x84180000 +#define MDCTL_4G_32BIT 0x84190000 +#define MDCTL_4G 0x841a0000 +#define MDCTL_8G 0x851a0000 +#define MDCTL_LPDDR2 0x83110000 + + +/* + * MDASP Address space partitioning: + * + * At 0.25GiB, internal address space ends. Above that DDR3 should be + * located. The CS1/CS0 split-line determines where: + * + * For 1x2Gb chips (0.25GiB total on CS0): 0.5GiB + * For 2x4Gb chips (1GiB total on CS0): 1.25GiB + * For 4x2Gb chips (1GiB total on CS0): 1.25GiB + * For 4x4Gb chips (2GiB total on CS0): 2.25GiB + * For 4x8Gb chips (4GiB total on CS0): 4.00GiB (maximum possible, + * shadowed partially by internal address space). + * + * Register value Split + * --------------------------- + * 0x0000000f 0.5GiB + * 0x00000017 0.75GiB + * 0x00000027 1.25GiB + * 0x00000047 2.25GiB + * 0x0000007f 4.00GiB + */ +#define MDASP_512MIB 0x0000000f +#define MDASP_768MIB 0x00000017 +#define MDASP_1GIB25 0x00000027 +#define MDASP_2GIB25 0x00000047 +#define MDASP_4GIB00 0x0000007f + +/* + * Initialize DDR3 chips + * MDSCR: Value = 0xvvvv803n, with 0xvvvv = value, n = Reg. number (BA) + */ +/* + * DDR3 chip MR2, n = 2: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Rtt(wr) * 0x0 (disabled) 10, 9 0x0000 + * SR-Temp. * 0x1 (Extended) 7 0x0080 + * Auto-SR * 0x0 (Manual) 6 0x0000 + * CWL * 400MHz 0x0 (5tCK) 5, 4, 3 0x0000 + * * 533MHz 0x1 (6tCK) 5, 4, 3 0x0008 + * ---------------------------------------------------------------- + */ +#define DDR3_MR2_400MHZ_RTT_OFF 0x00808032 +#define DDR3_MR2_533MHZ_RTT_OFF 0x00888032 +#define DDR3_MR2_400MHZ_RTT_120 0x04808032 +#define DDR3_MR2_533MHZ_RTT_120 0x04888032 + +/* + * DDR3 chip MR1, n = 1: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Qoff * 0x0 (enabled) 12 0x0000 + * TDQS * 0x0 (disabled) 11 0x0000 + * Rtt * 0x0 (disabled) 9, 6, 2 0x0000 + * Write-levelling * 0x0 (disable) 7 0x0000 + * ODS * 0x0 (RZQ/6=40) 5, 1 0x0000 + * DLL * 0x0 (enable) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR1_RTT_OFF_ODS_40 0x00008031 +#define DDR3_MR1_RTT_120_ODS_40 0x00408031 +#define DDR3_MR1_RTT_60_ODS_40 0x00048031 +#define DDR3_MR1_RTT_OFF_ODS_34 0x00028031 +#define DDR3_MR1_RTT_120_ODS_34 0x00428031 +#define DDR3_MR1_RTT_60_ODS_34 0x00068031 + +/* + * DDR3 chip MR0, n = 0: + * + * Par. Chip VALUE BITS vvvv + * ---------------------------------------------------------------- + * Precharge PD * 0x1 (fast exit) 12 0x1000 + * WR 400MHz 0x2 (6) 11,10,9 0x0400 + * 533MHz 0x4 (8) 11,10,9 0x0800 + * DLL reset * 0x1 (Yes) 8 0x0100 + * CL 400MHz 0x4 (6) 6,5,4,2 0x0020 + * 533MHz 0x6 (7) 6,5,4,2 0x0030 + * 533MHz 0x8 (8) 6,5,4,2 0x0040 + * RD burst type * 0x0 (seq.) 3 0x0000 + * BL * 0x0 (BL8) 0 0x0000 + * ---------------------------------------------------------------- + */ +#define DDR3_MR0_400MHZ 0x15208030 +#define DDR3_MR0_533MHZ_CL7 0x19308030 +#define DDR3_MR0_533MHZ_CL8 0x19408030 + + +/* + * MDREF: + * REF_SEL (bit 14,15): 0 (64kHz, needed for high-temp.) + * REFR (bit 11, 12, 13): 0x3 (4 refreshes) -> 0x00001800 + * 0x7 (8 refreshes) -> 0x00003800 + */ +#define MDREF_64KHZ 0x00001800 +#define MDREF_32KHZ 0x00007800 + +/* MPODTCTRL */ +#define MPODTCTRL_ODT_OFF 0x00000007 +#define MPODTCTRL_ODT_120 0x00011117 +#define MPODTCTRL_ODT_60 0x00022227 +#define MPODTCTRL_ODT_40 0x00033337 + +/* + * MPDGCTRL0: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * RST_RD_FIFO * 0 31 0x00000000 + * DG_CMP_CYC * 1 30 0x40000000 + * DG_DIS * 0 29 0x00000000 + * HW_DG_EN * 0 28 0x00000000 + * DG_HC_DEL1 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_EXT_UP * 0 23 0x00000000 + * DG_DL_ABS_OFFS1 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH0_400MHZ 0x42350231 +#define MPDGCTRL0_CH0_533MHZ 0x434b0350 +/* + * + * Channel 1: + * + * DG_HC_DEL1 (5) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS1 (5) 400MHz 0x35 16 0x00350000 + * 533MHz 0x4b 16 0x004b0000 + * DG_HC_DEL0 (4) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS0 (4) 400MHz 0x35 0 0x00000031 + * 533MHz 0x4b 0 0x00000050 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL0_CH1_400MHZ 0x42350231 +#define MPDGCTRL0_CH1_533MHZ 0x434b0350 + +/* + * MPDGCTRL1: + * + * Channel 0: + * + * Par. Chip VALUE SHIFT Reg. field + * ---------------------------------------------------------------- + * DG_HC_DEL3 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x4c 16 0x004c0000 + * DG_HC_DEL2 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 400MHz 0x18 0 0x00000018 + * 533MHz 0x59 0 0x00000059 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH0_400MHZ 0x021a0218 +#define MPDGCTRL1_CH0_533MHZ 0x034c0359 +/* + * + * Channel 1: + * + * DG_HC_DEL3 (7) 400MHz 2 24 0x02000000 + * 533MHz 3 24 0x03000000 + * DG_DL_ABS_OFFS3 (7) 400MHz 0x1a 16 0x001a0000 + * 533MHz 0x65 16 0x00650000 + * DG_HC_DEL2 (6) 400MHz 2 8 0x00000200 + * 533MHz 3 8 0x00000300 + * DG_DL_ABS_OFFS2 (6) 400MHz 0x18 0 0x00000018 + * 533MHz 0x48 0 0x00000048 + * ---------------------------------------------------------------- + */ +#define MPDGCTRL1_CH1_400MHZ 0x021a0218 +#define MPDGCTRL1_CH1_533MHZ 0x03650348 diff --git a/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg new file mode 100644 index 0000000000..f60d37f63e --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-dl.imxcfg @@ -0,0 +1,70 @@ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_DIFF_IN_DSE_48 0x00020028 +#define PAD_DIFF_IN_DSE_40 0x00020030 +#define PAD_DIFF_IN_DSE_34 0x00020038 + +/* Disable ISB LED ASAP */ +wm 32 0x020e04a8 0x000130b0 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e04bc PAD_SDQS /* SDQS0_P */ +wm 32 0x020e04c0 PAD_SDQS /* SDQS1_P */ +wm 32 0x020e04c4 PAD_SDQS /* SDQS2_P */ +wm 32 0x020e04c8 PAD_SDQS /* SDQS3_P */ +wm 32 0x020e04cc PAD_SDQS /* SDQS4_P */ +wm 32 0x020e04d0 PAD_SDQS /* SDQS5_P */ +wm 32 0x020e04d4 PAD_SDQS /* SDQS6_P */ +wm 32 0x020e04d8 PAD_SDQS /* SDQS7_P */ + +#define PAD_DQM_CTRL PAD_DIFF_IN_DSE_48 +#define PAD_SDCLK PAD_DIFF_IN_DSE_40 +wm 32 0x020e0470 PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e0474 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e0478 PAD_DQM_CTRL /* DQM2 */ +wm 32 0x020e047c PAD_DQM_CTRL /* DQM3 */ +wm 32 0x020e0480 PAD_DQM_CTRL /* DQM4 */ +wm 32 0x020e0484 PAD_DQM_CTRL /* DQM5 */ +wm 32 0x020e0488 PAD_DQM_CTRL /* DQM6 */ +wm 32 0x020e048c PAD_DQM_CTRL /* DQM7 */ +wm 32 0x020e0464 PAD_DQM_CTRL /* CAS */ +wm 32 0x020e0490 PAD_DQM_CTRL /* RAS */ +wm 32 0x020e04ac PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e04b0 PAD_SDCLK /* SDCLK1_P */ +wm 32 0x020e0494 PAD_DQM_CTRL /* RESET */ + +/* 0x00003000 = 100k PU */ +wm 32 0x020e04a4 0x00003000 /* SDCKE0 */ +wm 32 0x020e04a8 0x00003000 /* SDCKE1 */ +wm 32 0x020e04a0 0x00000000 /* SDBA2: disable PU */ + +/* 0x00003030 = PU + 40 Ohm drive */ +wm 32 0x020e04b4 0x00003030 /* ODT0 */ +wm 32 0x020e04b8 0x00003030 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0764 PAD_BxDS /* B0DS */ +wm 32 0x020e0770 PAD_BxDS /* B1DS */ +wm 32 0x020e0778 PAD_BxDS /* B2DS */ +wm 32 0x020e077c PAD_BxDS /* B3DS */ +wm 32 0x020e0780 PAD_BxDS /* B4DS */ +wm 32 0x020e0784 PAD_BxDS /* B5DS */ +wm 32 0x020e078c PAD_BxDS /* B6DS */ +wm 32 0x020e0748 PAD_BxDS /* B7DS */ +wm 32 0x020e074c PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0750 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e0754 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e0760 0x00020000 /* DDRMODE data */ + +wm 32 0x020e076c 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e0774 0x000c0000 /* DDR_TYPE DDR3 */ + diff --git a/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg new file mode 100644 index 0000000000..f5fa3e8d28 --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-q.imxcfg @@ -0,0 +1,69 @@ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_DIFF_IN_DSE_48 0x00020028 +#define PAD_DIFF_IN_DSE_40 0x00020030 +#define PAD_DIFF_IN_DSE_34 0x00020038 + +/* Disable ISB LED ASAP */ +wm 32 0x020e0420 0x000130b0 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e05a8 PAD_SDQS /* SDQS0_P */ +wm 32 0x020e05b0 PAD_SDQS /* SDQS1_P */ +wm 32 0x020e0524 PAD_SDQS /* SDQS2_P */ +wm 32 0x020e051c PAD_SDQS /* SDQS3_P */ +wm 32 0x020e0518 PAD_SDQS /* SDQS4_P */ +wm 32 0x020e050c PAD_SDQS /* SDQS5_P */ +wm 32 0x020e05b8 PAD_SDQS /* SDQS6_P */ +wm 32 0x020e05c0 PAD_SDQS /* SDQS7_P */ + +#define PAD_DQM_CTRL PAD_DIFF_IN_DSE_48 +#define PAD_SDCLK PAD_DIFF_IN_DSE_40 +wm 32 0x020e05ac PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e05b4 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e0528 PAD_DQM_CTRL /* DQM2 */ +wm 32 0x020e0520 PAD_DQM_CTRL /* DQM3 */ +wm 32 0x020e0514 PAD_DQM_CTRL /* DQM4 */ +wm 32 0x020e0510 PAD_DQM_CTRL /* DQM5 */ +wm 32 0x020e05bc PAD_DQM_CTRL /* DQM6 */ +wm 32 0x020e05c4 PAD_DQM_CTRL /* DQM7 */ +wm 32 0x020e056c PAD_DQM_CTRL /* CAS */ +wm 32 0x020e0578 PAD_DQM_CTRL /* RAS */ +wm 32 0x020e0588 PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e0594 PAD_SDCLK /* SDCLK1_P */ +wm 32 0x020e057c PAD_DQM_CTRL /* RESET */ + +/* 0x00003000 = 100k PU */ +wm 32 0x020e0590 0x00003000 /* SDCKE0 */ +wm 32 0x020e0598 0x00003000 /* SDCKE1 */ +wm 32 0x020e058c 0x00000000 /* SDBA2: disable PU */ + +/* 0x00003030 = PU + 40 Ohm drive */ +wm 32 0x020e059c 0x00003030 /* ODT0 */ +wm 32 0x020e05a0 0x00003030 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0784 PAD_BxDS /* B0DS */ +wm 32 0x020e0788 PAD_BxDS /* B1DS */ +wm 32 0x020e0794 PAD_BxDS /* B2DS */ +wm 32 0x020e079c PAD_BxDS /* B3DS */ +wm 32 0x020e07a0 PAD_BxDS /* B4DS */ +wm 32 0x020e07a4 PAD_BxDS /* B5DS */ +wm 32 0x020e07a8 PAD_BxDS /* B6DS */ +wm 32 0x020e0748 PAD_BxDS /* B7DS */ +wm 32 0x020e074c PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0750 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e0758 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e0774 0x00020000 /* DDRMODE data */ + +wm 32 0x020e078c 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e0798 0x000c0000 /* DDR_TYPE DDR3 */ diff --git a/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg b/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg new file mode 100644 index 0000000000..e36601942d --- /dev/null +++ b/arch/arm/boards/protonic-imx6/padsetup-ul.imxcfg @@ -0,0 +1,42 @@ + +/* + * Some defines for PAD setup: + * Unfortunately we don't have a powerful pre-processor, so we need to + * define explicit 32-bit hex values. + */ + +#define PAD_DSE_48 0x00000028 +#define PAD_DSE_40 0x00000030 + +#define PAD_SDQS PAD_DSE_48 +wm 32 0x020e0280 PAD_SDQS /* SDQS0_P */ +wm 32 0x020e0284 PAD_SDQS /* SDQS1_P */ + +#define PAD_DQM_CTRL PAD_DSE_48 +#define PAD_SDCLK PAD_DSE_48 + +wm 32 0x020e0244 PAD_DQM_CTRL /* DQM0 */ +wm 32 0x020e0248 PAD_DQM_CTRL /* DQM1 */ +wm 32 0x020e024c PAD_DQM_CTRL /* RAS */ +wm 32 0x020e0250 PAD_DQM_CTRL /* CAS */ +wm 32 0x020e027c PAD_SDCLK /* SDCLK0_P */ +wm 32 0x020e0288 PAD_DQM_CTRL /* RESET */ + +wm 32 0x020e0270 0x00000000 /* SDBA2: disable PU */ + +wm 32 0x020e0260 PAD_DSE_48 /* ODT0 */ +wm 32 0x020e0264 PAD_DSE_48 /* ODT1 */ + +#define PAD_BxDS PAD_DSE_48 +wm 32 0x020e0498 PAD_BxDS /* B0DS */ +wm 32 0x020e04a4 PAD_BxDS /* B1DS */ + +wm 32 0x020e0490 PAD_DSE_48 /* ADDDS */ + +wm 32 0x020e0494 0x00020000 /* DDRMODE_CTL */ +wm 32 0x020e04ac 0x00000000 /* DDRPKE disable PU */ +wm 32 0x020e04b0 0x00020000 /* DDRMODE data */ + +wm 32 0x020e04a0 0x00000030 /* CTLDS 40 Ohm */ + +wm 32 0x020e04b4 0x000c0000 /* DDR_TYPE DDR3 */ diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg index eb7bc8486d..2c6a32eed4 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg index 8930012885..7f9b2a3988 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg index 4eb937a717..7f75a17a35 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg index 438bd8ea4d..9d5bc03c96 100644 --- a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg index 12cda04e60..6d2d37de59 100644 --- a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg index 0a1915b982..201493e6a3 100644 --- a/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg +++ b/arch/arm/boards/technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x020c4068 0xffffffff wm 32 0x020c406c 0xffffffff diff --git a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg index 68cb08e200..5f91bed6f3 100644 --- a/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg +++ b/arch/arm/boards/technexion-wandboard/flash-header-technexion-wandboard.imxcfg @@ -1,4 +1,4 @@ loadaddr 0x00907000 soc imx6 max_load_size 0x11000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h index 4d16b0667a..b9492bbcb3 100644 --- a/arch/arm/boards/tqma53/flash-header-tq-tqma53.h +++ b/arch/arm/boards/tqma53/flash-header-tq-tqma53.h @@ -1,6 +1,6 @@ soc imx53 loadaddr 0x70000000 -dcdofs 0x400 +ivtofs 0x400 /* IOMUX */ wm 32 0x53fa8554 0x00300000 diff --git a/arch/arm/boards/tqma53/flash-header.imxcfg b/arch/arm/boards/tqma53/flash-header.imxcfg index 3d52ff1dec..bbe2300ece 100644 --- a/arch/arm/boards/tqma53/flash-header.imxcfg +++ b/arch/arm/boards/tqma53/flash-header.imxcfg @@ -1,6 +1,6 @@ soc imx53 loadaddr 0x70000000 -dcdofs 0x400 +ivtofs 0x400 /* IOMUX */ wm 32 0x53fa8554 0x00300000 diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg index 192ebda743..4f557d5db5 100644 --- a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg +++ b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> diff --git a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg index 1fd75a24b2..deda53b464 100644 --- a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg +++ b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg index 39f2a8a221..a349b1022b 100644 --- a/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg +++ b/arch/arm/boards/udoo-neo/flash-header-mx6sx-udoo-neo_full.imxcfg @@ -7,7 +7,7 @@ loadaddr 0x80000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 /* Enable all clocks */ wm 32 0x020c4068 0xffffffff diff --git a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg index a0647a71a8..fc88a0b8b4 100644 --- a/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg +++ b/arch/arm/boards/udoo/flash-header-mx6-udoo.imxcfg @@ -1,6 +1,6 @@ soc imx6 loadaddr 0x20000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg index 2c82f2316f..50968d7940 100644 --- a/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg +++ b/arch/arm/boards/variscite-mx6/flash-header-variscite.imxcfg @@ -1,6 +1,6 @@ loadaddr 0x10000000 soc imx6 -dcdofs 0x400 +ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6q-ddr-regs.h> diff --git a/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg b/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg index 76f4c6b59b..5674e7a6e1 100644 --- a/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg +++ b/arch/arm/boards/zii-imx51-rdu1/flash-header-imx51-zii-rdu1.imxcfg @@ -1,6 +1,6 @@ soc imx51 loadaddr 0x90000000 -dcdofs 0x400 +ivtofs 0x400 wm 32 0x73fa88a0 0x00000200 wm 32 0x73fa850c 0x000020c5 diff --git a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg index a4abe197e4..fcfef9c234 100644 --- a/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg +++ b/arch/arm/boards/zii-imx6q-rdu2/flash-header-rdu2.imxcfg @@ -1,4 +1,4 @@ soc imx6 loadaddr 0x00907000 max_load_size 0x31000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg index 46f3d95048..022f9711b2 100644 --- a/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg +++ b/arch/arm/boards/zii-imx7d-dev/flash-header-zii-imx7d-dev.imxcfg @@ -1,6 +1,6 @@ soc imx7 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/flash-header/imx7d-ddr-sabresd.imxcfg> diff --git a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg index aff8321b9a..8921f32110 100644 --- a/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg +++ b/arch/arm/boards/zii-imx8mq-dev/flash-header-zii-imx8mq-dev.imxcfg @@ -2,4 +2,4 @@ soc imx8mq loadaddr 0x007E1000 max_load_size 0x3F000 -dcdofs 0x400 +ivtofs 0x400 diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg index 7076a6431f..4b73da4c19 100644 --- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg +++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg @@ -1,6 +1,6 @@ soc vf610 loadaddr 0x80000000 -dcdofs 0x400 +ivtofs 0x400 #include <mach/vf610-iomux-regs.h> #include <mach/vf610-ddrmc-regs.h> diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig index bd19fc45aa..b3d5741c69 100644 --- a/arch/arm/configs/eukrea_cpuimx35_defconfig +++ b/arch/arm/configs/eukrea_cpuimx35_defconfig @@ -74,7 +74,6 @@ CONFIG_MTD_RAW_DEVICE=y CONFIG_NAND=y CONFIG_NAND_ALLOW_ERASE_BAD=y CONFIG_NAND_IMX=y -CONFIG_NAND_IMX_BBM=y CONFIG_USB_HOST=y CONFIG_USB_IMX_CHIPIDEA=y CONFIG_USB_EHCI=y diff --git a/arch/arm/configs/freescale-mx21-ads_defconfig b/arch/arm/configs/freescale-mx21-ads_defconfig index 7dc8cb1426..e1843db3e2 100644 --- a/arch/arm/configs/freescale-mx21-ads_defconfig +++ b/arch/arm/configs/freescale-mx21-ads_defconfig @@ -36,5 +36,4 @@ CONFIG_DRIVER_CFI=y CONFIG_CFI_BUFFER_WRITE=y CONFIG_NAND=y CONFIG_NAND_IMX=y -CONFIG_NAND_IMX_BBM=y CONFIG_FS_TFTP=y diff --git a/arch/arm/configs/imx_defconfig b/arch/arm/configs/imx_defconfig index ede70d7eaf..02e33e122e 100644 --- a/arch/arm/configs/imx_defconfig +++ b/arch/arm/configs/imx_defconfig @@ -90,7 +90,6 @@ CONFIG_NAND=y # CONFIG_NAND_ECC_HW_SYNDROME is not set CONFIG_NAND_ALLOW_ERASE_BAD=y CONFIG_NAND_IMX=y -CONFIG_NAND_IMX_BBM=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_USB_HOST=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index fb7872434e..5dcdff0638 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -12,6 +12,7 @@ CONFIG_MACH_TQMA53=y CONFIG_MACH_FREESCALE_MX53_VMX53=y CONFIG_MACH_TX53=y CONFIG_MACH_PHYTEC_SOM_IMX6=y +CONFIG_MACH_PROTONIC_IMX6=y CONFIG_MACH_KONTRON_SAMX6I=y CONFIG_MACH_DFI_FS700_M60=y CONFIG_MACH_GUF_SANTARO=y @@ -30,6 +31,7 @@ CONFIG_MACH_TECHNEXION_WANDBOARD=y CONFIG_MACH_EMBEST_MARSBOARD=y CONFIG_MACH_EMBEST_RIOTBOARD=y CONFIG_MACH_UDOO=y +CONFIG_MACH_UDOO_NEO=y CONFIG_MACH_VARISCITE_MX6=y CONFIG_MACH_GW_VENTANA=y CONFIG_MACH_CM_FX6=y @@ -39,10 +41,12 @@ CONFIG_MACH_VF610_TWR=y CONFIG_MACH_ZII_RDU1=y CONFIG_MACH_ZII_RDU2=y CONFIG_MACH_ZII_VF610_DEV=y +CONFIG_MACH_ZII_IMX7D_DEV=y CONFIG_MACH_PHYTEC_PHYCORE_IMX7=y CONFIG_MACH_FREESCALE_MX7_SABRESD=y CONFIG_MACH_NXP_IMX6ULL_EVK=y CONFIG_MACH_GRINN_LITEBOARD=y +CONFIG_MACH_DIGI_CCIMX6ULSBCPRO=y CONFIG_IMX_IIM_FUSE_BLOW=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y @@ -65,6 +69,8 @@ CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_PARTITION_DISK_EFI=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_STATE=y +CONFIG_BOOTCHOOSER=y CONFIG_RESET_SOURCE=y CONFIG_FASTBOOT_CMD_OEM=y CONFIG_CMD_DMESG=y @@ -127,6 +133,8 @@ CONFIG_CMD_OF_NODE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OFTREE=y CONFIG_CMD_TIME=y +CONFIG_CMD_STATE=y +CONFIG_CMD_BOOTCHOOSER=y CONFIG_NET=y CONFIG_NET_NETCONSOLE=y CONFIG_OF_BAREBOX_DRIVERS=y @@ -144,7 +152,6 @@ CONFIG_MTD_SST25L=y CONFIG_NAND=y CONFIG_NAND_ALLOW_ERASE_BAD=y CONFIG_NAND_IMX=y -CONFIG_NAND_IMX_BBM=y CONFIG_NAND_MXS=y CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y @@ -174,6 +181,7 @@ CONFIG_MFD_DA9063=y CONFIG_MFD_MC34704=y CONFIG_MFD_MC9SDZ60=y CONFIG_MFD_STMPE=y +CONFIG_STATE_DRV=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_LED_GPIO_OF=y diff --git a/arch/arm/configs/imx_v8_defconfig b/arch/arm/configs/imx_v8_defconfig index b96867ad0c..7e3bfadd9e 100644 --- a/arch/arm/configs/imx_v8_defconfig +++ b/arch/arm/configs/imx_v8_defconfig @@ -2,6 +2,7 @@ CONFIG_ARCH_IMX=y CONFIG_IMX_MULTI_BOARDS=y CONFIG_MACH_ZII_IMX8MQ_DEV=y CONFIG_MACH_NXP_IMX8MM_EVK=y +CONFIG_MACH_NXP_IMX8MP_EVK=y CONFIG_MACH_NXP_IMX8MQ_EVK=y CONFIG_MACH_PHYTEC_SOM_IMX8MQ=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d61a052310..3cbf65078d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -74,6 +74,22 @@ lwl-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o lwl-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += imx8mq-phytec-phycore-som.dtb.o lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o lwl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o +lwl-$(CONFIG_MACH_PROTONIC_IMX6) += \ + imx6q-prti6q.dtb.o \ + imx6q-prtwd2.dtb.o \ + imx6q-vicut1.dtb.o \ + imx6dl-alti6p.dtb.o \ + imx6dl-lanmcu.dtb.o \ + imx6dl-plybas.dtb.o \ + imx6dl-plym2m.dtb.o \ + imx6dl-prtmvt.dtb.o \ + imx6dl-prtrvt.dtb.o \ + imx6dl-prtvt7.dtb.o \ + imx6dl-victgo.dtb.o \ + imx6dl-vicut1.dtb.o \ + imx6qp-prtwd3.dtb.o \ + imx6qp-vicutp.dtb.o \ + imx6ul-prti6g.dtb.o lwl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o lwl-$(CONFIG_MACH_PHYTEC_SOM_RK3288) += rk3288-phycore-som.dtb.o lwl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o @@ -100,6 +116,7 @@ lwl-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboar lwl-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o lwl-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o lwl-$(CONFIG_MACH_NXP_IMX8MM_EVK) += imx8mm-evk.dtb.o +lwl-$(CONFIG_MACH_NXP_IMX8MP_EVK) += imx8mp-evk.dtb.o lwl-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += imx8mq-evk.dtb.o lwl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o lwl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o diff --git a/arch/arm/dts/imx6dl-alti6p.dts b/arch/arm/dts/imx6dl-alti6p.dts new file mode 100644 index 0000000000..8d53100bea --- /dev/null +++ b/arch/arm/dts/imx6dl-alti6p.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-prti6q.dtsi" + +/ { + model = "Altesco I6P Board"; + compatible = "alt,alti6p", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +/* DDC */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T configure DDC pins for HDMI! */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1 + MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-lanmcu.dts b/arch/arm/dts/imx6dl-lanmcu.dts new file mode 100644 index 0000000000..b05ed9c3ba --- /dev/null +++ b/arch/arm/dts/imx6dl-lanmcu.dts @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2019 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "LANMCU"; + compatible = "lan,lanmcu", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + memory { + reg = <0x10000000 0x10000000>; + }; + + reg_usb_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-OTG-VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_npd>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + + display: display0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "bgr666"; + status = "okay"; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0bdh6"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 5 7 9 12 15 20 27 35 47 62 81 107 142 188 248 + 328 433 573 757 1000>; + default-brightness-level = <20>; + status = "okay"; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug0 { + label = "debug0"; + gpios = <&gpio1 8 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + prti6q { + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW revision detect */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 /* REV_ID4 */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_wlan_npd: wlan_npd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 + >; + }; + + pinctrl_ts_edt: ts1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + rts-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + linux,rs485-enabled-at-boot-time; + rts-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + touchscreen: edt_ft5406@38 { + compatible = "edt,edt-ft5406"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts_edt>; + reg = <0x38>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + + touchscreen-fuzz-x = <0>; + touchscreen-fuzz-y = <0>; + + /* Touch screen calibration */ + threshold = <50>; + gain = <5>; + offset = <10>; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_pwrseq>; + pm-ignore-notify; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; + + partitions { + /* + * Map a partition at the last 64k of the area available for + * the second stage bootloader. + */ + compatible = "fixed-partitions"; + #size-cells = <1>; + #address-cells = <1>; + + bootstate_backend: bootstate_backend@f0000 { + reg = <0xf0000 0x10000>; + label = "bootstate"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-plybas.dts b/arch/arm/dts/imx6dl-plybas.dts new file mode 100644 index 0000000000..de0ba05e13 --- /dev/null +++ b/arch/arm/dts/imx6dl-plybas.dts @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Plymovent BAS board"; + compatible = "ply,plybas", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x10000000>; + }; + + backlight_lcd { + status = "disabled"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@20 { + label = "START"; + linux,code = <31>; + gpios = <&gpio5 8 1>; + }; + button@21 { + label = "CLEAN"; + linux,code = <46>; + gpios = <&gpio5 9 1>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug0 { + label = "debug0"; + gpios = <&gpio1 8 0>; + }; + + debug1 { + label = "debug1"; + gpios = <&gpio1 9 0>; + }; + + light_tower1 { + label = "light_tower1"; + gpios = <&gpio4 22 0>; + linux,default-trigger = "heartbeat"; + }; + + light_tower2 { + label = "light_tower2"; + gpios = <&gpio4 23 0>; + }; + + light_tower3 { + label = "light_tower3"; + gpios = <&gpio4 24 0>; + }; + + light_tower4 { + label = "light_tower4"; + gpios = <&gpio4 25 0>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <0 20>; + status = "okay"; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + /* CAN1_SR + CAN2_SR GPIO outputs */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* YACO_nIRQ */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 /* YACO_BOOT0 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* YACO_nRESET */ + + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x13070 /* BUZZER */ + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x13070 /* ANA_OUT_SD */ + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 /* ANA_OUT_ERR */ + + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x13070 /* RELAY1 */ + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x13070 /* RELAY2 */ + + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 /* IN1 */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 /* IN2 */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 /* IN3 */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 /* IN4 */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 /* IN5 */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 /* IN6 */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 /* IN7 */ + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 /* IN8 */ + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 /* IN9 */ + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 /* IN10 */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* IN11 */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 /* IN12 */ + + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1a0b0 /* HMI */ + + /* HW revision detect */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 /* REV_ID4 */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* DEBUG0 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* DEBUG1 */ + + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x13070 /* LED1 (lighttower) */ + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x13070 /* LED2 (lighttower) */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x13070 /* LED3 (lighttower) */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x13070 /* LED4 (lighttower) */ + >; + }; + + /* RS485 UART */ + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x130b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-plym2m.dts b/arch/arm/dts/imx6dl-plym2m.dts new file mode 100644 index 0000000000..b66321fb46 --- /dev/null +++ b/arch/arm/dts/imx6dl-plym2m.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-prti6q.dtsi" + +/ { + model = "Plymovent M2M board"; + compatible = "ply,plym2m", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x10000000>; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug0 { + label = "debug0"; + gpios = <&gpio1 8 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + /* CAN1_SR GPIO output */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CAN1_TERM */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 /* TSC_BUSY */ + + /* HW revision detect */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 /* REV_ID4 */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_backlight_m2m: backlightm2mgrp { + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-prtmvt.dts b/arch/arm/dts/imx6dl-prtmvt.dts new file mode 100644 index 0000000000..05fce7178f --- /dev/null +++ b/arch/arm/dts/imx6dl-prtmvt.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Protonic MVT board"; + compatible = "prt,prtmvt", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + button@20 { + label = "GPIO Key F1"; + linux,code = <59>; + gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>; + }; + button@21 { + label = "GPIO Key F2"; + linux,code = <60>; + gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>; + }; + button@22 { + label = "GPIO Key F3"; + linux,code = <61>; + gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>; + }; + button@23 { + label = "GPIO Key F4"; + linux,code = <62>; + gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>; + }; + button@24 { + label = "GPIO Key F5"; + linux,code = <63>; + gpios = <&pca_gpio 4 GPIO_ACTIVE_LOW>; + }; + + // Center + button@25 { + label = "GPIO Key CYCLE"; + linux,code = <154>; + gpios = <&pca_gpio 5 GPIO_ACTIVE_LOW>; + }; + button@26 { + label = "GPIO Key ESC"; + linux,code = <1>; + gpios = <&pca_gpio 6 GPIO_ACTIVE_LOW>; + }; + button@27 { + label = "GPIO Key UP"; + linux,code = <103>; + gpios = <&pca_gpio 7 GPIO_ACTIVE_LOW>; + }; + button@28 { + label = "GPIO Key DOWN"; + linux,code = <108>; + gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; + }; + button@29 { + label = "GPIO Key OK"; + linux,code = <0x160>; + gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; + }; + + button@2a { + label = "GPIO Key F6"; + linux,code = <64>; + gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; + }; + button@2b { + label = "GPIO Key F7"; + linux,code = <65>; + gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; + }; + button@2c { + label = "GPIO Key F8"; + linux,code = <66>; + gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; + }; + button@2d { + label = "GPIO Key F9"; + linux,code = <67>; + gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; + }; + button@2e { + label = "GPIO Key F10"; + linux,code = <68>; + gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&pwm2 { + status = "disabled"; +}; + +&pcie { + status = "disabled"; +}; + +&i2c1 { + pca_gpio: gpio@74 { + #gpio-cells = <2>; + compatible = "nxp,pca9539"; + reg = <0x74>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9539>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + }; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_pca9539: pca9539 { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-prtrvt.dts b/arch/arm/dts/imx6dl-prtrvt.dts new file mode 100644 index 0000000000..802bd50ae6 --- /dev/null +++ b/arch/arm/dts/imx6dl-prtrvt.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Protonic RVT board"; + compatible = "prt,prtrvt", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + nfc@0 { + compatible = "ti,trf7970a"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + spi-max-frequency = <2000000>; + interrupts-extended = <&gpio5 14 IRQ_TYPE_LEVEL_LOW>; + ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, + <&gpio5 11 GPIO_ACTIVE_LOW>; + vin-supply = <®_3v3>; + vin-voltage-override = <3100000>; + autosuspend-delay = <30000>; + irq-status-read-quirk; + en2-rf-quirk; + t5t-rmb-extra-byte-quirk; + status = "okay"; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* nc */ + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* nc */ + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_l */ + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_h */ + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&pcie { + status = "okay"; +}; + +&usbh1 { + status = "disabled"; +}; + +&vpu { + status = "disabled"; +}; + +&iomuxc { + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + /* NFC_ASK_OOK */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x100b1 + /* NFC_PWR_EN */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x100b1 + /* NFC_EN2 */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x100b1 + /* NFC_EN */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + /* NFC_MOD */ + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1 + /* NFC_IRQ */ + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-prtvt7.dts b/arch/arm/dts/imx6dl-prtvt7.dts new file mode 100644 index 0000000000..c202e6786d --- /dev/null +++ b/arch/arm/dts/imx6dl-prtvt7.dts @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Protonic VT7"; + compatible = "prt,prtvt7", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000>; + brightness-levels = <0 20 81 248 1000>; + default-brightness-level = <20>; + num-interpolated-steps = <21>; + power-supply = <®_12v_bl>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + status = "okay"; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + + esc { + label = "GPIO Key ESC"; + linux,code = <KEY_ESC>; + gpios = <&gpio_pca 0 GPIO_ACTIVE_LOW>; + }; + + up { + label = "GPIO Key UP"; + linux,code = <KEY_UP>; + gpios = <&gpio_pca 1 GPIO_ACTIVE_LOW>; + }; + + down { + label = "GPIO Key DOWN"; + linux,code = <KEY_DOWN>; + gpios = <&gpio_pca 4 GPIO_ACTIVE_LOW>; + }; + + enter { + label = "GPIO Key Enter"; + linux,code = <KEY_ENTER>; + gpios = <&gpio_pca 3 GPIO_ACTIVE_LOW>; + }; + + cycle { + label = "GPIO Key CYCLE"; + linux,code = <KEY_CYCLEWINDOWS>; + gpios = <&gpio_pca 2 GPIO_ACTIVE_LOW>; + }; + + f1 { + label = "GPIO Key F1"; + linux,code = <KEY_F1>; + gpios = <&gpio_pca 14 GPIO_ACTIVE_LOW>; + }; + + f2 { + label = "GPIO Key F2"; + linux,code = <KEY_F2>; + gpios = <&gpio_pca 13 GPIO_ACTIVE_LOW>; + }; + + f3 { + label = "GPIO Key F3"; + linux,code = <KEY_F3>; + gpios = <&gpio_pca 12 GPIO_ACTIVE_LOW>; + }; + + f4 { + label = "GPIO Key F4"; + linux,code = <KEY_F4>; + gpios = <&gpio_pca 11 GPIO_ACTIVE_LOW>; + }; + + f5 { + label = "GPIO Key F5"; + linux,code = <KEY_F5>; + gpios = <&gpio_pca 10 GPIO_ACTIVE_LOW>; + }; + + f6 { + label = "GPIO Key F6"; + linux,code = <KEY_F6>; + gpios = <&gpio_pca 5 GPIO_ACTIVE_LOW>; + }; + + f7 { + label = "GPIO Key F7"; + linux,code = <KEY_F7>; + gpios = <&gpio_pca 6 GPIO_ACTIVE_LOW>; + }; + + f8 { + label = "GPIO Key F8"; + linux,code = <KEY_F8>; + gpios = <&gpio_pca 7 GPIO_ACTIVE_LOW>; + }; + + f9 { + label = "GPIO Key F9"; + linux,code = <KEY_F9>; + gpios = <&gpio_pca 8 GPIO_ACTIVE_LOW>; + }; + + f10 { + label = "GPIO Key F10"; + linux,code = <KEY_F10>; + gpios = <&gpio_pca 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "innolux,g070y2t0ec"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_12v_bl: regulator-bl-12v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_12v_bl>; + regulator-name = "12v-bl"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + tsc@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + spi-max-frequency = <100000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + vcc-supply = <®_3v3>; + + ti,vref-delay-usecs = /bits/ 16 <100>; + + ti,x-min = /bits/ 16 <0>; + ti,x-max = /bits/ 16 <8000>; + ti,y-min = /bits/ 16 <0>; + ti,y-max = /bits/ 16 <4800>; + ti,x-plate-ohms = /bits/ 16 <800>; + ti,y-plate-ohms = /bits/ 16 <300>; + ti,pressure-max = /bits/ 16 <4095>; + + ti,skip-samples = <2>; + ti,sample-period-msecs = <10>; + ti,report-period-msecs = <30>; + + ti,filter-tolerance = <80>; + ti,touch-resistance-threshold = <3500>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux_ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux_pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +}; + +&i2c1 { + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; +}; + +&i2c3 { + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + gpio_pca: gpio@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + interrupts-extended = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&ipu1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&usbh1 { + status = "disabled"; +}; + +&vpu { + status = "disabled"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xb0 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xb0 + + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xb0 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xb0 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xb0 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xb0 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xb0 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xb0 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xb0 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xb0 + + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xb0 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xb0 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xb0 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xb0 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xb0 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xb0 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xb0 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xb0 + + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xb0 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xb0 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xb0 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xb0 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xb0 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xb0 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xb0 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xb0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_reg_12v_bl: 12blgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-victgo.dts b/arch/arm/dts/imx6dl-victgo.dts new file mode 100644 index 0000000000..55bc4c8d41 --- /dev/null +++ b/arch/arm/dts/imx6dl-victgo.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2016 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-vicut1.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Kverneland Tellus GO"; + compatible = "kvg,victgo", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x20000000>; + }; + + rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-0 = <&pinctrl_rotary_ch>; + gpios = <&gpio2 3 0>, <&gpio2 4 0>; + linux,axis = <8>; /* REL_WHEEL */ + rotary-encoder,steps-per-period = <4>; + rotary-encoder,relative-axis; + rotary-encoder,rollover; + wakeup-source; + }; + + rotary-button { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_rotary_btn>; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Rotary Key"; + gpios = <&gpio2 05 1>; + linux,code = <KEY_ENTER>; + gpio-key,wakeup; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&i2c1 { + ht16k33: ht16k33@70 { + compatible = "holtek,ht16k33"; + pinctrl-0 = <&pinctrl_ht16k33>; + reg = <0x70>; + refresh-rate-hz = <20>; + debounce-delay-ms = <50>; + interrupt-parent = <&gpio4>; + interrupts = <5 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + keypad,num-rows = <12>; + keypad,num-columns = <3>; + linux,keymap = < + MATRIX_KEY(2, 0, KEY_F6) + MATRIX_KEY(3, 0, KEY_F8) + MATRIX_KEY(4, 0, KEY_F10) + MATRIX_KEY(5, 0, KEY_F4) + MATRIX_KEY(6, 0, KEY_F2) + MATRIX_KEY(2, 1, KEY_F5) + MATRIX_KEY(3, 1, KEY_F7) + MATRIX_KEY(4, 1, KEY_F9) + MATRIX_KEY(5, 1, KEY_F3) + MATRIX_KEY(6, 1, KEY_F1) + >; + }; +}; + +&pwm2 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 + >; + }; + + pinctrl_rotary_ch: rotarygrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 /* ROTARY_A */ + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 /* ROTARY_B */ + >; + }; + + pinctrl_rotary_btn: rotarygrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b0 /* ROTARY_BTN */ + >; + }; + + pinctrl_ht16k33: ht16k33grp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* IRQ */ + >; + }; + + pinctrl_tsc2046e: tsc2046egrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-vicut1.dts b/arch/arm/dts/imx6dl-vicut1.dts new file mode 100644 index 0000000000..725acbefc5 --- /dev/null +++ b/arch/arm/dts/imx6dl-vicut1.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6dl.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Kverneland UT1 Board"; + compatible = "kvg,vicut1", "fsl,imx6dl"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP_RGMII_MD(0x1b030, 0x10030) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-prti6q.dts b/arch/arm/dts/imx6q-prti6q.dts new file mode 100644 index 0000000000..f0469d5f62 --- /dev/null +++ b/arch/arm/dts/imx6q-prti6q.dts @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6q.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/leds/common.h> +#include <dt-bindings/sound/fsl-imx-audmux.h> + +/ { + model = "Protonic PRTI6Q board"; + compatible = "prt,prti6q", "fsl,imx6q"; + + chosen { + environment { + compatible = "barebox,environment"; + device-path = &ecspi1, "partname:env"; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <16>; + power-supply = <®_3v3>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + can3_25m_osc: can3-25m-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-debug1 { + function = LED_FUNCTION_SD; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + enable-active-high; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "regulator-WL12xx"; + startup-delay-us = <70000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; + spdif-out; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux_ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux_pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "env"; + reg = <0x100000 0x10000>; + }; + + partition@110000 { + label = "spare"; + reg = <0x110000 0x2f0000>; + }; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can3>; + clocks = <&can3_25m_osc>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <5000000>; + }; + + adc@1 { + compatible = "ti,adc128s052"; + reg = <1>; + spi-max-frequency = <2000000>; + vref-supply = <®_3v3>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; +}; + +/* DDC */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* can2_l */ + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can2_h */ + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_l */ + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + /* can1_h */ + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + pinctrl-0 = <&pinctrl_usbotg &pinctrl_usbotg_id>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + vmmc-supply = <®_wifi>; + cap-power-off-card; + keep-power-in-suspend; + status = "okay"; + + wifi { + compatible = "ti,wl1271"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; + ref-clock-frequency = "38400000"; + tcxo-clock-frequency = "19200000"; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 + >; + }; + + pinctrl_can3: can3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + /* ADC128S022 CS */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T + * configure DDC pins for HDMI! + */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + /* DDC */ + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg_id: usbotgidgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f058 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + /* WL12xx IRQ */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-prtwd2.dts b/arch/arm/dts/imx6q-prtwd2.dts new file mode 100644 index 0000000000..8572917865 --- /dev/null +++ b/arch/arm/dts/imx6q-prtwd2.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2018 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6q.dtsi> +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "Protonic WD2 board"; + compatible = "prt,prtwd2", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + + /* PRTWD2 rev 1 bitbang I2C for Ethernet Switch */ + i2c@4 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <20>; /* ~10 kHz */ + i2c-gpio,scl-output-only; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&can1 { + pinctrl-0 = <&pinctrl_can1 &pinctrl_can1phy>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>; + clock-names = "ipg", "ahb"; + status = "okay"; + + fixed-link { + speed = <100>; + pause; + full-duplex; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* V in */ + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* I charge */ + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* V bus */ + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* nc */ + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + pm-ignore-notify; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth_chg>; + + pinctrl_can1phy: can1phy { + fsl,pins = < + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x130b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1f8b0 + MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f8b0 + >; + }; + + pinctrl_usb_eth_chg: usbethchggrp { + fsl,pins = < + /* USB charging control */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; diff --git a/arch/arm/dts/imx6q-vicut1.dts b/arch/arm/dts/imx6q-vicut1.dts new file mode 100644 index 0000000000..9f60ed1ac2 --- /dev/null +++ b/arch/arm/dts/imx6q-vicut1.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6q.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Kverneland UT1Q Board"; + compatible = "kvg,vicut1q", "fsl,imx6q"; + + memory { + reg = <0x10000000 0xf0000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + /* phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; */ + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP_RGMII_MD(0x1b030, 0x10030) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-prti6q.dtsi b/arch/arm/dts/imx6qdl-prti6q.dtsi new file mode 100644 index 0000000000..ed526d185f --- /dev/null +++ b/arch/arm/dts/imx6qdl-prti6q.dtsi @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2014 Protonic Holland + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + chosen { + stdout-path = &uart4; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-vicut1.dtsi b/arch/arm/dts/imx6qdl-vicut1.dtsi new file mode 100644 index 0000000000..dc18614f89 --- /dev/null +++ b/arch/arm/dts/imx6qdl-vicut1.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +#include "imx6qdl-prti6q.dtsi" +#include <dt-bindings/input/input.h> + +/ { + gpio_key_pwr: gpio_keys { + compatible = "gpio-keys"; + autorepeat; + + power { + label = "GPIO Key Power"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug0 { + label = "debug0"; + gpios = <&gpio1 8 0>; + linux,default-trigger = "heartbeat"; + }; + + debug1 { + label = "debug1"; + gpios = <&gpio1 9 0>; + linux,default-trigger = "mmc"; + }; + + power_led { + label = "power_led"; + gpios = <&gpio2 24 0>; + default-state = "on"; + }; + + isb_led { + label = "isb_led"; + gpios = <&gpio4 31 0>; + default-state = "off"; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&i2c3 { + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + /* CAN1_SR + CAN2_SR GPIO outputs */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* CAM1_MIRROR */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 + /* CAM2_MIRROR */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 + /* CAM_nDETECT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + /* ISB_IN1 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 + /* ISB_nIN2 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + /* WARN_LIGHT */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 + /* ON2_FB */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 + /* YACO_nIRQ */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + /* YACO_BOOT0 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 + /* YACO_nRESET */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + /* FORCE_ON1 */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + + /* HW revision detect */ + /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + /* REV_ID1 = PWM output LED_PWM (SION) */ + /* defined in &pinctrl_pwm3 */ + /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + /* REV_ID4 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + + /* New in HW revision 1 */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 /* ON1_FB */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 /* DIP1_FB */ + + /* New in UTC (UT1 HW revision 1) and TGO */ + /* WHEEL */ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x100b0 + /* RADAR */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x100b0 + /* PTO */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x100b0 + /* CPU_ON1_CTRL */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 + /* CPU_ON2_CTRL */ + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b0 + /* CPU_HITCH_IN_OUT */ + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x100b0 + /* CPU_LIGHT_ON */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b0 + /* CPU_CONTACT_IN */ + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + /* YaCO AUX Uart */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* YaCO Touchscreen UART */ + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + /* DEBUG0A */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 + /* DEBUG1A */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 + /* DEBUG0 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + /* DEBUG1 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + /* POWER_LED */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + /* ISB_LED */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + /* ISB LED (not in TGO or UTC version 1+) */ + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + /* REV_ID1 = PWM output LED_PWM (SION for ID) */ + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x4001b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qp-prtwd3.dts b/arch/arm/dts/imx6qp-prtwd3.dts new file mode 100644 index 0000000000..0ef0bae036 --- /dev/null +++ b/arch/arm/dts/imx6qp-prtwd3.dts @@ -0,0 +1,675 @@ +/* + * Copyright (c) 2018 Protonic Holland + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include <arm/imx6qp.dtsi> +#include "imx6qdl-prti6q.dtsi" + +/ { + model = "Protonic WD3 board"; + compatible = "prt,prtwd3", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; + + usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + + clk20m_can: fdcan_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + clk25m_switch: switch_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk25m_phy3: phy3_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk50m_phy: phy_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio0>; + + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH>; + }; + + display_panel0 { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + + port { + display_panel0_in: endpoint { + remote-endpoint = <&serializer0_out>; + }; + }; + }; + + display_panel1 { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_panel1>; + + port { + display_panel1_in: endpoint { + remote-endpoint = <&serializer1_out>; + }; + }; + }; + + backlight_lcd: backlight_lcd { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 1 2 4 6 8 12 16 24 32 48 64 96 128 192 255>; + default-brightness-level = <15>; + power-supply = <®_3v3>; + }; + + backlight_panel1: backlight_panel1 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000>; + brightness-levels = <0 1 2 4 6 8 12 16 24 32 48 64 96 128 192 255>; + default-brightness-level = <0>; + power-supply = <®_3v3>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>; + assigned-clock-rates = <125000000>; + + phy-mode = "rgmii"; + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* Microchip KSZ9031 */ + rgmii_phy: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + + interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; + + /* FIXME: tx/rx clk skew are currently set by imx + * platform driver. Write own walues here to not depend + * fixup of horror. + */ + + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + /* reset assert time is provided by documentation */ + reset-assert-us = <10000>; + /* documented reset deassert time (100us) is not enough + * use test value of 300us. + */ + reset-deassert-us = <1000>; + + clocks = <&clk25m_phy3>; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + sja1105_switch: sja1105@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,sja1105q"; + spi-max-frequency = <4000000>; + spi-cpha; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + + clocks = <&clk25m_switch>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "usb"; + phy-handle = <&usbeth_phy>; + phy-mode = "rmii"; + }; + + port@1 { + reg = <1>; + label = "t1slave"; + phy-handle = <&tja1102_phy1>; + phy-mode = "rmii"; + }; + + port@2 { + reg = <2>; + label = "t1master"; + phy-handle = <&tja1102_phy0>; + phy-mode = "rmii"; + + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +&mdio0 { + usbeth_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + + interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <1000>; + + /* FIXME: the clock is provided by switch and we should know + * and we should request it only after switch have done clock + * configuration. Since it is currently not implemented, + * use fixed clock. + * WARNING: Using fixed clocks in this case is potential source + * for evil bugs. Switch may reconfigure, stop or change clk + * freq without letting PHY to know about it. + */ + clocks = <&clk50m_phy>; + clock-names = "rmii-ref"; + }; + + tja1102_phy0: ethernet-phy@4 { + compatible = "ethernet-phy-id0180.dc80"; + reg = <0x4>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + /* reset detection time is 20 usec. */ + reset-assert-us = <20>; + /* reset to standby 2 msec. */ + reset-deassert-us = <2000>; + #address-cells = <1>; + #size-cells = <0>; + + tja1102_phy1: ethernet-phy@5 { + reg = <0x5>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + can3: can@0 { + compatible = "microchip,mcp2518fd"; + spi-max-frequency = <5000000>; + reg = <0>; + clocks = <&clk20m_can>; + interrupt-parent = <&gpio4>; + interrupts = <25 0x2>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + serializer0: ds90ub927@c { + compatible = "ti,ds90ub927"; + reg = <0x0c>; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + serializer0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + /* port@1 { + reg = <1>; + serializer0_audio_in: endpoint { + remote-endpoint = <&audio_i2s0_out>; + }; + }; */ + port@2 { + reg = <2>; + serializer0_out: endpoint { + remote-endpoint = <&display_panel0_in>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + serializer1: ds90ub927@c { + compatible = "ti,ds90ub927"; + reg = <0x0c>; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + serializer1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + port@2 { + reg = <2>; + serializer1_out: endpoint { + remote-endpoint = <&display_panel1_in>; + }; + }; + }; + + camdeser: ds90ub954@30 { + compatible = "ti,ds90ub954"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + camdeser_fpd_link_in: endpoint { + }; + }; + port@1 { + reg = <1>; + camdeser_mipi_out: endpoint { + remote-endpoint = <&mipi_csi_in>; + }; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; /* force 3.3V VIO */ + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + pm-ignore-notify; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&serializer0_in>; + }; + }; + }; + + lvds-channel@1 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds1_out: endpoint { + remote-endpoint = <&serializer1_in>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + port@0 { + reg = <0>; + + mipi_csi_in: endpoint { + remote-endpoint = <&camdeser_mipi_out>; + }; + }; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + /* Empty, to disable parallel camera from PRTI6Q */ +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Configure clock provider for RGMII ref clock */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + /* Configure clock consumer for RGMII ref clock */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + + /* SJA1105Q switch reset */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 + + /* phy3/rgmii_phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 + /* phy3/rgmii_phy int */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 + >; + }; + + pinctrl_mdio0: mdio0grp { + fsl,pins = < + /* phy0/usbeth_phy reset */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 + /* phy0/usbeth_phy int */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + + /* phy12/tja1102_phy0 reset */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 + /* phy12/tja1102_phy0 int */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 + /* phy12/tja1102_phy0 enable. Set 100K pull-up */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + + + pinctrl_hog: hoggrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + /* CAN1_SR + CAN2_SR GPIO outputs */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + /* CAN1_TERM (not used on WD3) */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + + /* HW revision detect */ + /* REV_ID0 */ + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + /* REV_ID1 */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* REV_ID2 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + /* REV_ID3 */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + /* REV_ID4 */ + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + + /* USB charging control */ + /* CHG Control */ + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0 + /* RID0 */ + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0 + /* RID1 */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0 + /* RID2 */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0 + + /* Power VSEL and TG */ + /* VSEL */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + /* TG */ + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + + /* Display panel 0 GPIO */ + /* L/R */ + MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0 + /* TS_nINT */ + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0 + /* EN */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 + /* LVDS0_nINT */ + MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x1b0b0 + /* LVDS0_PD */ + MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x1b0b0 + + /* Display panel 1 GPIO */ + /* L/R */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + /* TS_nINT */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + /* EN */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + /* LVDS1_nINT */ + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x1b0b0 + /* LVDS1_PD */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 + + /* Camera */ + /* CAM_GPIO0 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + /* CAM_nINT */ + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x1b0b0 + /* CAM_GPIO1 */ + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0 + /* CAM_nPD */ + MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1b0b0 + /* CAM_LOCK */ + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0 + + /* USB ethernet reset (asix) */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001f8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_leds: ledsgrp { + /* No leds */ + fsl,pins = <>; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + /* CAN2_nINT */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx6qp-vicutp.dts b/arch/arm/dts/imx6qp-vicutp.dts new file mode 100644 index 0000000000..44cfe68867 --- /dev/null +++ b/arch/arm/dts/imx6qp-vicutp.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2014 Protonic Holland + */ + +/dts-v1/; +#include <arm/imx6qp.dtsi> +#include "imx6qdl-vicut1.dtsi" + +/ { + model = "Kverneland UT1P Board"; + compatible = "kvg,vicutp", "fsl,imx6qp"; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + /* phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; */ + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP_RGMII_MD(0x1b030, 0x10030) */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; +}; diff --git a/arch/arm/dts/imx6ul-prti6g.dts b/arch/arm/dts/imx6ul-prti6g.dts new file mode 100644 index 0000000000..e65198bab2 --- /dev/null +++ b/arch/arm/dts/imx6ul-prti6g.dts @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2016 Protonic Holland + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "imx6ul-prti6g.dtsi" + +/ { + model = "Protonic PRTI6G Board"; + compatible = "prt,prti6g", "fsl,imx6ul"; +}; + +&pinctrl_hog { + fsl,pins = < + /* HW revision detect */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BOARD_ID0 */ + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 /* BOARD_ID1 */ + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* BOARD_ID2 */ + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 /* BOARD_ID3 */ + + /* Safety controller IO */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WAKE_SC */ + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* PROGRAM_SC */ + >; +}; + +&ecspi2 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c2 { + can_adc: ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; +}; diff --git a/arch/arm/dts/imx6ul-prti6g.dtsi b/arch/arm/dts/imx6ul-prti6g.dtsi new file mode 100644 index 0000000000..c20bbd5bc2 --- /dev/null +++ b/arch/arm/dts/imx6ul-prti6g.dtsi @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2016 Protonic Holland + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arm/imx6ul.dtsi> +#include <dt-bindings/gpio/gpio.h> + +/ { + chosen { + stdout-path = &uart1; + environment@0 { + compatible = "barebox,environment"; + device-path = &flash, "partname:env"; + }; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p2v: 3p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; + + reg_1p35v: 1p35-regulator { + compatible = "regulator-fixed"; + regulator-name = "regulator-1P35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + debug { + label = "debug0"; + gpios = <&gpio4 16 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p2v>; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: w25q64fv@0 { + compatible = "winbond,w25q64", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + m25p,fast-read; + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0 0x60000>; /* 384 Kb */ + }; + + partition@60000 { + label = "env"; + reg = <0x60000 0x10000>; /* 64 Kb */ + }; + + partition@70000 { + label = "dtb"; + reg = <0x70000 0x10000>; /* 64 Kb */ + }; + + partition@80000 { + label = "kernel"; + reg = <0x80000 0x780000>; /* 7680 Kb */ + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + /* RFID chip */ +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + rtc: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tmp103: tmp103@70 { + compatible = "ti,tmp103", "tmp103"; + reg = <0x70>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1 &pinctrl_ethphy0_rst>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <11>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + prti6g { + pinctrl_hog: hoggrp { + fsl,pins = < + /* HW revision detect */ + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0 /* REV_ID0 */ + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x1b0b0 /* REV_ID1 */ + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 /* REV_ID2 */ + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x1b0b0 /* REV_ID3 */ + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x1b0b0 /* BOARD_ID0 */ + MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0 /* BOARD_ID1 */ + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* BOARD_ID2 */ + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0 /* BOARD_ID3 */ + + /* CAN diagnostics (nSMBALERT) */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x170b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x0b0b0 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x000b1 + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x0b0b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x0b0b0 + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x000b1 + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x0b0b0 + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x0b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x100b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_ethphy0_rst: ethphy-rstgrp-0 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x00880 /* PHY RESET */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 /* SR */ + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* TERM */ + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0 /* nSMBALERT */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* SR */ + >; + }; + }; +}; diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts new file mode 100644 index 0000000000..bb255e2c94 --- /dev/null +++ b/arch/arm/dts/imx8mp-evk.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 NXP + * Copyright (C) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> + */ + +/dts-v1/; + +#include <arm64/freescale/imx8mp-evk.dts> + +/ { + chosen { + environment-sd { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + status = "disabled"; + }; + environment-emmc { + compatible = "barebox,environment"; + device-path = &usdhc3, "partname:barebox-environment"; + status = "disabled"; + }; + }; + + gpio-leds { + status { + barebox,default-trigger = "heartbeat"; + }; + }; +}; + +ðphy1 { + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xe0000>; + }; + + partition@e0000 { + label = "barebox-environment"; + reg = <0xe0000 0x20000>; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec 0x640>; +}; diff --git a/arch/arm/dts/vf610-zii-dev-rev-c.dts b/arch/arm/dts/vf610-zii-dev-rev-c.dts index 62c70c8905..c1b3bc86dc 100644 --- a/arch/arm/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/dts/vf610-zii-dev-rev-c.dts @@ -17,6 +17,8 @@ */ switch0-eeprom = &switch0; switch1-eeprom = &switch1; + fiber-eeprom0 = &fiber_eeprom0; + fiber-eeprom1 = &fiber_eeprom1; }; }; @@ -31,3 +33,19 @@ }; }; }; + +&sff2_i2c { + fiber_eeprom0: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber0"; + }; +}; + +&sff3_i2c { + fiber_eeprom1: eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "fiber1"; + }; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 6dd5cb2aca..7e42659004 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -190,6 +190,10 @@ config ARCH_IMX8MM select ARCH_IMX8M bool +config ARCH_IMX8MP + select ARCH_IMX8M + bool + config ARCH_IMX8MQ select ARCH_IMX8M bool @@ -336,6 +340,12 @@ config MACH_PHYTEC_SOM_IMX6 select ARCH_IMX6 select ARCH_IMX6UL +config MACH_PROTONIC_IMX6 + bool "Protonic-Holland i.MX6 based boards" + select ARCH_IMX6 + select ARCH_IMX6UL + select ARM_USE_COMPRESSED_DTB + config MACH_KONTRON_SAMX6I bool "Kontron sAMX6i" select ARCH_IMX6 @@ -522,6 +532,17 @@ config MACH_NXP_IMX8MM_EVK select I2C_IMX_EARLY select USB_GADGET_DRIVER_ARC_PBL +config MACH_NXP_IMX8MP_EVK + bool "NXP i.MX8MP EVK Board" + select ARCH_IMX8MP + select FIRMWARE_IMX_LPDDR4_PMU_TRAIN + select FIRMWARE_IMX8MP_ATF + select ARM_SMCCC + select MCI_IMX_ESDHC_PBL + select IMX8M_DRAM + select I2C_IMX_EARLY + select USB_GADGET_DRIVER_ARC_PBL + config MACH_NXP_IMX8MQ_EVK bool "NXP i.MX8MQ EVK Board" select ARCH_IMX8MQ diff --git a/arch/arm/mach-imx/atf.c b/arch/arm/mach-imx/atf.c index 4ced8cd083..03857e6b9b 100644 --- a/arch/arm/mach-imx/atf.c +++ b/arch/arm/mach-imx/atf.c @@ -47,6 +47,11 @@ void imx8mm_atf_load_bl31(const void *fw, size_t fw_size) imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MM_ATF_BL31_BASE_ADDR); } +void imx8mp_atf_load_bl31(const void *fw, size_t fw_size) +{ + imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MP_ATF_BL31_BASE_ADDR); +} + void imx8mq_atf_load_bl31(const void *fw, size_t fw_size) { imx8m_atf_load_bl31(fw, fw_size, (void *)MX8MQ_ATF_BL31_BASE_ADDR); diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index ef868301cd..c3cf4b85ff 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -28,6 +28,7 @@ #include <mach/imx6-regs.h> #include <mach/imx7-regs.h> #include <mach/imx8mm-regs.h> +#include <mach/imx8mp-regs.h> #include <mach/imx8mq-regs.h> #include <mach/vf610-regs.h> #include <mach/imx8mq.h> @@ -651,3 +652,19 @@ void imx8mm_boot_save_loc(void) { imx_boot_save_loc(imx8mm_get_boot_source); } + +void imx8mp_get_boot_source(enum bootsource *src, int *instance) +{ + unsigned long addr; + void __iomem *src_base = IOMEM(MX8MP_SRC_BASE_ADDR); + uint32_t sbmr2 = readl(src_base + 0x70); + + addr = IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0; + + __imx7_get_boot_source(src, instance, addr, sbmr2); +} + +void imx8mp_boot_save_loc(void) +{ + imx_boot_save_loc(imx8mp_get_boot_source); +} diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index c6a0ac7c50..cc7a409e37 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -82,6 +82,11 @@ void imx8mm_cpu_lowlevel_init(void) imx8m_cpu_lowlevel_init(); } +void imx8mp_cpu_lowlevel_init(void) +{ + imx8m_cpu_lowlevel_init(); +} + void imx8mq_cpu_lowlevel_init(void) { imx8m_cpu_lowlevel_init(); diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c index 5d595addb8..cc5d3a8359 100644 --- a/arch/arm/mach-imx/esdctl.c +++ b/arch/arm/mach-imx/esdctl.c @@ -889,6 +889,11 @@ void __noreturn imx8mm_barebox_entry(void *boarddata) imx8m_barebox_entry(boarddata); } +void __noreturn imx8mp_barebox_entry(void *boarddata) +{ + imx8m_barebox_entry(boarddata); +} + void __noreturn imx8mq_barebox_entry(void *boarddata) { imx8m_barebox_entry(boarddata); diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c index a922470988..1b3cb70da8 100644 --- a/arch/arm/mach-imx/imx-bbu-internal.c +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -384,16 +384,21 @@ static enum filetype imx_bbu_expected_filetype(void) static unsigned long imx_bbu_flash_header_offset_mmc(void) { - unsigned long offset = SZ_1K; + /* + * i.MX8MQ moved the header by 32K to accomodate for GPT partition + * tables. The offset to the IVT is 1KiB. + */ + if (cpu_is_mx8mm() || cpu_is_mx8mq()) + return SZ_32K + SZ_1K; /* - * i.MX8MQ moved the header by 32K to accomodate for GPT - * partition tables + * i.MX8MP moved the header by 32K to accomodate for GPT partition + * tables, but the IVT is right at the beginning of the image. */ - if (cpu_is_mx8m()) - offset += SZ_32K; + if (cpu_is_mx8mp()) + return SZ_32K; - return offset; + return SZ_1K; } static int imx_bbu_update(struct bbu_handler *handler, struct bbu_data *data) diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c index 0bbe44e4dd..3d8c55c54e 100644 --- a/arch/arm/mach-imx/imx.c +++ b/arch/arm/mach-imx/imx.c @@ -82,6 +82,8 @@ static int imx_soc_from_dt(void) return IMX_CPU_IMX8MQ; if (of_machine_is_compatible("fsl,imx8mm")) return IMX_CPU_IMX8MM; + if (of_machine_is_compatible("fsl,imx8mp")) + return IMX_CPU_IMX8MP; if (of_machine_is_compatible("fsl,vf610")) return IMX_CPU_VF610; @@ -124,6 +126,8 @@ static int imx_init(void) ret = imx7_init(); else if (cpu_is_mx8mm()) ret = imx8mm_init(); + else if (cpu_is_mx8mp()) + ret = imx8mp_init(); else if (cpu_is_mx8mq()) ret = imx8mq_init(); else if (cpu_is_vf610()) diff --git a/arch/arm/mach-imx/imx5.c b/arch/arm/mach-imx/imx5.c index 96288f99e0..dd6c079fe3 100644 --- a/arch/arm/mach-imx/imx5.c +++ b/arch/arm/mach-imx/imx5.c @@ -37,10 +37,13 @@ void imx5_init_lowlevel(void) { u32 r; - /* ARM errata ID #468414 */ __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r)); + + if (r & (1 << 1)) + return; + + /* ARM errata ID #468414 */ r |= (1 << 5); /* enable L1NEON bit */ - r &= ~(1 << 1); /* explicitly disable L2 cache */ __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r)); /* reconfigure L2 cache aux control reg */ diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c index d2ed7d52a9..b9e01a1d18 100644 --- a/arch/arm/mach-imx/imx8m.c +++ b/arch/arm/mach-imx/imx8m.c @@ -22,6 +22,7 @@ #include <mach/imx8m-ccm-regs.h> #include <mach/reset-reason.h> #include <mach/ocotp.h> +#include <mach/imx8mp-regs.h> #include <mach/imx8mq-regs.h> #include <mach/imx8m-ccm-regs.h> #include <soc/imx8m/clk-early.h> @@ -105,6 +106,29 @@ int imx8mm_init(void) return imx8m_init(cputypestr); } +int imx8mp_init(void) +{ + void __iomem *anatop = IOMEM(MX8MP_ANATOP_BASE_ADDR); + uint32_t type = FIELD_GET(DIGPROG_MAJOR, + readl(anatop + MX8MP_ANATOP_DIGPROG)); + const char *cputypestr; + + imx8mp_boot_save_loc(); + + switch (type) { + case IMX8M_CPUTYPE_IMX8MP: + cputypestr = "i.MX8MP"; + break; + default: + cputypestr = "unknown i.MX8M"; + break; + }; + + imx_set_silicon_revision(cputypestr, imx8mp_cpu_revision()); + + return imx8m_init(cputypestr); +} + int imx8mq_init(void) { void __iomem *anatop = IOMEM(MX8M_ANATOP_BASE_ADDR); diff --git a/arch/arm/mach-imx/include/mach/atf.h b/arch/arm/mach-imx/include/mach/atf.h index f64a9dd2ba..c21ffaeb56 100644 --- a/arch/arm/mach-imx/include/mach/atf.h +++ b/arch/arm/mach-imx/include/mach/atf.h @@ -7,12 +7,14 @@ #define MX8M_ATF_BL31_SIZE_LIMIT SZ_64K #define MX8MM_ATF_BL31_BASE_ADDR 0x00920000 +#define MX8MP_ATF_BL31_BASE_ADDR 0x00960000 #define MX8MQ_ATF_BL31_BASE_ADDR 0x00910000 #define MX8M_ATF_BL33_BASE_ADDR 0x40200000 #define MX8MM_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR #define MX8MQ_ATF_BL33_BASE_ADDR MX8M_ATF_BL33_BASE_ADDR void imx8mm_atf_load_bl31(const void *fw, size_t fw_size); +void imx8mp_atf_load_bl31(const void *fw, size_t fw_size); void imx8mq_atf_load_bl31(const void *fw, size_t fw_size); -#endif
\ No newline at end of file +#endif diff --git a/arch/arm/mach-imx/include/mach/debug_ll.h b/arch/arm/mach-imx/include/mach/debug_ll.h index 5eed01631c..f2114d50e9 100644 --- a/arch/arm/mach-imx/include/mach/debug_ll.h +++ b/arch/arm/mach-imx/include/mach/debug_ll.h @@ -15,6 +15,7 @@ #include <mach/imx53-regs.h> #include <mach/imx6-regs.h> #include <mach/imx7-regs.h> +#include <mach/imx8mp-regs.h> #include <mach/imx8mq-regs.h> #include <mach/vf610-regs.h> @@ -48,6 +49,8 @@ #define IMX_DEBUG_SOC MX6 #elif defined CONFIG_DEBUG_IMX7D_UART #define IMX_DEBUG_SOC MX7 +#elif defined CONFIG_DEBUG_IMX8MP_UART +#define IMX_DEBUG_SOC MX8MP #elif defined CONFIG_DEBUG_IMX8MQ_UART #define IMX_DEBUG_SOC MX8MQ #elif defined CONFIG_DEBUG_VF610_UART diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h index 41eb9f6729..e6bbc3145a 100644 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -140,6 +140,7 @@ void __noreturn imx6q_barebox_entry(void *boarddata); void __noreturn imx6ul_barebox_entry(void *boarddata); void __noreturn vf610_barebox_entry(void *boarddata); void __noreturn imx8mm_barebox_entry(void *boarddata); +void __noreturn imx8mp_barebox_entry(void *boarddata); void __noreturn imx8mq_barebox_entry(void *boarddata); void __noreturn imx7d_barebox_entry(void *boarddata); #define imx6sx_barebox_entry(boarddata) imx6ul_barebox_entry(boarddata) diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 7742a002ce..f30133a05a 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -17,6 +17,7 @@ void imx6_boot_save_loc(void); void imx7_boot_save_loc(void); void vf610_boot_save_loc(void); void imx8mm_boot_save_loc(void); +void imx8mp_boot_save_loc(void); void imx8mq_boot_save_loc(void); void imx25_get_boot_source(enum bootsource *src, int *instance); @@ -28,6 +29,7 @@ void imx6_get_boot_source(enum bootsource *src, int *instance); void imx7_get_boot_source(enum bootsource *src, int *instance); void vf610_get_boot_source(enum bootsource *src, int *instance); void imx8mm_get_boot_source(enum bootsource *src, int *instance); +void imx8mp_get_boot_source(enum bootsource *src, int *instance); void imx8mq_get_boot_source(enum bootsource *src, int *instance); int imx1_init(void); @@ -43,6 +45,7 @@ int imx6_init(void); int imx7_init(void); int vf610_init(void); int imx8mm_init(void); +int imx8mp_init(void); int imx8mq_init(void); int imx1_devices_init(void); @@ -63,6 +66,7 @@ void imx7_cpu_lowlevel_init(void); void vf610_cpu_lowlevel_init(void); void imx8mq_cpu_lowlevel_init(void); void imx8mm_cpu_lowlevel_init(void); +void imx8mp_cpu_lowlevel_init(void); /* There's a off-by-one betweem the gpio bank number and the gpiochip */ /* range e.g. GPIO_1_5 is gpio 5 under linux */ @@ -215,6 +219,18 @@ extern unsigned int __imx_cpu_type; # define cpu_is_mx8mm() (0) #endif +#ifdef CONFIG_ARCH_IMX8MP +# ifdef imx_cpu_type +# undef imx_cpu_type +# define imx_cpu_type __imx_cpu_type +# else +# define imx_cpu_type IMX_CPU_IMX8MP +# endif +# define cpu_is_mx8mp() (imx_cpu_type == IMX_CPU_IMX8MP) +#else +# define cpu_is_mx8mp() (0) +#endif + #ifdef CONFIG_ARCH_IMX8MQ # ifdef imx_cpu_type # undef imx_cpu_type @@ -251,6 +267,6 @@ extern unsigned int __imx_cpu_type; #define cpu_is_mx23() (0) #define cpu_is_mx28() (0) -#define cpu_is_mx8m() (cpu_is_mx8mq() || cpu_is_mx8mm()) +#define cpu_is_mx8m() (cpu_is_mx8mq() || cpu_is_mx8mm() || cpu_is_mx8mp()) #endif /* __MACH_GENERIC_H */ diff --git a/arch/arm/mach-imx/include/mach/imx-header.h b/arch/arm/mach-imx/include/mach/imx-header.h index dc8e2eee2f..f1e076dab9 100644 --- a/arch/arm/mach-imx/include/mach/imx-header.h +++ b/arch/arm/mach-imx/include/mach/imx-header.h @@ -94,7 +94,7 @@ static inline bool is_imx_flash_header_v2(const void *blob) struct config_data { uint32_t image_load_addr; - uint32_t image_dcd_offset; + uint32_t image_ivt_offset; uint32_t image_size; uint32_t max_load_size; uint32_t load_size; diff --git a/arch/arm/mach-imx/include/mach/imx8mp-regs.h b/arch/arm/mach-imx/include/mach/imx8mp-regs.h new file mode 100644 index 0000000000..29e8a45706 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx8mp-regs.h @@ -0,0 +1,46 @@ +#ifndef __MACH_IMX8MP_REGS_H +#define __MACH_IMX8MP_REGS_H + +#include <mach/imx8m-regs.h> + +#define MX8MP_M4_BOOTROM_BASE_ADDR 0x007e0000 + +#define MX8MP_GPIO1_BASE_ADDR 0x30200000 +#define MX8MP_GPIO2_BASE_ADDR 0x30210000 +#define MX8MP_GPIO3_BASE_ADDR 0x30220000 +#define MX8MP_GPIO4_BASE_ADDR 0x30230000 +#define MX8MP_GPIO5_BASE_ADDR 0x30240000 +#define MX8MP_WDOG1_BASE_ADDR 0x30280000 +#define MX8MP_WDOG2_BASE_ADDR 0x30290000 +#define MX8MP_WDOG3_BASE_ADDR 0x302a0000 +#define MX8MP_IOMUXC_BASE_ADDR 0x30330000 +#define MX8MP_IOMUXC_GPR_BASE_ADDR 0x30340000 +#define MX8MP_OCOTP_BASE_ADDR 0x30350000 +#define MX8MP_ANATOP_BASE_ADDR 0x30360000 +#define MX8MP_CCM_BASE_ADDR 0x30380000 +#define MX8MP_SRC_BASE_ADDR 0x30390000 +#define MX8MP_GPC_BASE_ADDR 0x303a0000 +#define MX8MP_SYSCNT_RD_BASE_ADDR 0x306a0000 +#define MX8MP_SYSCNT_CMP_BASE_ADDR 0x306b0000 +#define MX8MP_SYSCNT_CTRL_BASE_ADDR 0x306c0000 +#define MX8MP_UART1_BASE_ADDR 0x30860000 +#define MX8MP_UART3_BASE_ADDR 0x30880000 +#define MX8MP_UART2_BASE_ADDR 0x30890000 +#define MX8MP_I2C1_BASE_ADDR 0x30a20000 +#define MX8MP_I2C2_BASE_ADDR 0x30a30000 +#define MX8MP_I2C3_BASE_ADDR 0x30a40000 +#define MX8MP_I2C4_BASE_ADDR 0x30a50000 +#define MX8MP_UART4_BASE_ADDR 0x30a60000 +#define MX8MP_USDHC1_BASE_ADDR 0x30b40000 +#define MX8MP_USDHC2_BASE_ADDR 0x30b50000 +#define MX8MP_USDHC3_BASE_ADDR 0x30b60000 +#define MX8MP_USB1_BASE_ADDR 0x32e40000 +#define MX8MP_USB2_BASE_ADDR 0x32e50000 +#define MX8MP_TZASC_BASE_ADDR 0x32f80000 +#define MX8MP_SRC_IPS_BASE_ADDR 0x30390000 +#define MX8MP_SRC_DDRC_RCR_ADDR 0x30391000 +#define MX8MP_SRC_DDRC2_RCR_ADDR 0x30391004 +#define MX8MP_DDRC_DDR_SS_GPR0 0x3d000000 +#define MX8MP_DDR_CSD1_BASE_ADDR 0x40000000 + +#endif /* __MACH_IMX8MP_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h index 2ef2987188..1494fd661f 100644 --- a/arch/arm/mach-imx/include/mach/imx8mq.h +++ b/arch/arm/mach-imx/include/mach/imx8mq.h @@ -5,6 +5,7 @@ #include <mach/generic.h> #include <mach/imx8mq-regs.h> #include <mach/imx8mm-regs.h> +#include <mach/imx8mp-regs.h> #include <mach/revision.h> #include <linux/bitfield.h> @@ -15,12 +16,14 @@ #define MX8MQ_ANATOP_DIGPROG 0x6c #define MX8MM_ANATOP_DIGPROG 0x800 +#define MX8MP_ANATOP_DIGPROG 0x800 #define DIGPROG_MAJOR GENMASK(23, 8) #define DIGPROG_MINOR GENMASK(7, 0) #define IMX8M_CPUTYPE_IMX8MQ 0x8240 #define IMX8M_CPUTYPE_IMX8MM 0x8241 +#define IMX8M_CPUTYPE_IMX8MP 0x8243 static inline int imx8mm_cpu_revision(void) { @@ -30,6 +33,14 @@ static inline int imx8mm_cpu_revision(void) return revision; } +static inline int imx8mp_cpu_revision(void) +{ + void __iomem *anatop = IOMEM(MX8MP_ANATOP_BASE_ADDR); + uint32_t revision = FIELD_GET(DIGPROG_MINOR, + readl(anatop + MX8MP_ANATOP_DIGPROG)); + return revision; +} + static inline int imx8mq_cpu_revision(void) { void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR); @@ -62,4 +73,4 @@ static inline int imx8mq_cpu_revision(void) u64 imx8m_uid(void); -#endif /* __MACH_IMX8_H */
\ No newline at end of file +#endif /* __MACH_IMX8_H */ diff --git a/arch/arm/mach-imx/include/mach/imx_cpu_types.h b/arch/arm/mach-imx/include/mach/imx_cpu_types.h index b3fccfadb5..6d96f7c590 100644 --- a/arch/arm/mach-imx/include/mach/imx_cpu_types.h +++ b/arch/arm/mach-imx/include/mach/imx_cpu_types.h @@ -14,6 +14,7 @@ #define IMX_CPU_IMX7 7 #define IMX_CPU_IMX8MQ 8 #define IMX_CPU_IMX8MM 81 +#define IMX_CPU_IMX8MP 83 #define IMX_CPU_VF610 610 #endif /* __MACH_IMX_CPU_TYPES_H */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx8mp.h b/arch/arm/mach-imx/include/mach/iomux-mx8mp.h new file mode 100644 index 0000000000..2607ba21f6 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx8mp.h @@ -0,0 +1,1103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __ASM_ARCH_IMX8MP_PINS_H__ +#define __ASM_ARCH_IMX8MP_PINS_H__ + +#include <mach/iomux-v3.h> +#include <mach/imx8mp-regs.h> +#include <mach/iomux-mx8m.h> + +enum { + MX8MP_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x0274, 0x0014, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0), + MX8MP_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K = IOMUX_PAD(0x0274, 0x0014, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__SJC_FAIL = IOMUX_PAD(0x0274, 0x0014, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x0278, 0x0018, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0278, 0x0018, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0), + MX8MP_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M = IOMUX_PAD(0x0278, 0x0018, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__SJC_ACTIVE = IOMUX_PAD(0x0278, 0x0018, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x027C, 0x001C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x027C, 0x001C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x027C, 0x001C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__SJC_DE_B = IOMUX_PAD(0x027C, 0x001C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x0280, 0x0020, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x0280, 0x0020, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__SDMA1_EXT_EVENT00 = IOMUX_PAD(0x0280, 0x0020, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__ANAMIX_XTAL_OK = IOMUX_PAD(0x0280, 0x0020, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__SJC_DONE = IOMUX_PAD(0x0280, 0x0020, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x0284, 0x0024, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x0284, 0x0024, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__SDMA1_EXT_EVENT01 = IOMUX_PAD(0x0284, 0x0024, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV = IOMUX_PAD(0x0284, 0x0024, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__USDHC1_TEST_TRIG = IOMUX_PAD(0x0284, 0x0024, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x0288, 0x0028, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__M7_NMI = IOMUX_PAD(0x0288, 0x0028, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x0288, 0x0028, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__USDHC2_TEST_TRIG = IOMUX_PAD(0x0288, 0x0028, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x028C, 0x002C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__ENET_QOS_MDC = IOMUX_PAD(0x028C, 0x002C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0), + MX8MP_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x028C, 0x002C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__ECSPI1_TEST_TRIG = IOMUX_PAD(0x028C, 0x002C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0290, 0x0030, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ENET_QOS_MDIO = IOMUX_PAD(0x0290, 0x0030, 1, 0x0590, 0, 0), + MX8MP_PAD_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x0290, 0x0030, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ECSPI2_TEST_TRIG = IOMUX_PAD(0x0290, 0x0030, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0294, 0x0034, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0294, 0x0034, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0294, 0x0034, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN = IOMUX_PAD(0x0294, 0x0034, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x0294, 0x0034, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0294, 0x0034, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__FLEXSPI_TEST_TRIG = IOMUX_PAD(0x0294, 0x0034, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x0298, 0x0038, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0298, 0x0038, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0298, 0x0038, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__USDHC3_RESET_B = IOMUX_PAD(0x0298, 0x0038, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0298, 0x0038, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__RAWNAND_TEST_TRIG = IOMUX_PAD(0x0298, 0x0038, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x029C, 0x003C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__HSIOMIX_usb1_OTG_ID = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x029C, 0x003C, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__OCOTP_FUSE_LATCHED = IOMUX_PAD(0x029C, 0x003C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02A0, 0x0040, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__HSIOMIX_usb2_OTG_ID = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x02A0, 0x0040, 2, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__USDHC3_VSELECT = IOMUX_PAD(0x02A0, 0x0040, 4, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0), + MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0 = IOMUX_PAD(0x02A0, 0x0040, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02A0, 0x0040, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02A4, 0x0044, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1 = IOMUX_PAD(0x02A4, 0x0044, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x02A4, 0x0044, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02A8, 0x0048, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__HSIOMIX_usb1_OTG_OC = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02A8, 0x0048, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2 = IOMUX_PAD(0x02A8, 0x0048, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x02A8, 0x0048, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02AC, 0x004C, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__USDHC3_CD_B = IOMUX_PAD(0x02AC, 0x004C, 4, 0x0608, 0, 0), + MX8MP_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02AC, 0x004C, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x02AC, 0x004C, 7, 0x0000, 0, 0), + + MX8MP_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02B0, 0x0050, 0, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__HSIOMIX_usb2_OTG_OC = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__USDHC3_WP = IOMUX_PAD(0x02B0, 0x0050, 4, 0x0634, 0, 0), + MX8MP_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02B0, 0x0050, 5, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02B0, 0x0050, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_MDC__ENET_QOS_MDC = IOMUX_PAD(0x02B4, 0x0054, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x02B4, 0x0054, 2, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02B4, 0x0054, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDC__USDHC3_STROBE = IOMUX_PAD(0x02B4, 0x0054, 6, 0x0630, 0, 0), + MX8MP_PAD_ENET_MDC__SIM_M_HADDR15 = IOMUX_PAD(0x02B4, 0x0054, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x02B8, 0x0058, 0, 0x0590, 1, 0), + MX8MP_PAD_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x02B8, 0x0058, 2, 0x0528, 0, 0), + MX8MP_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02B8, 0x0058, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_MDIO__USDHC3_DATA5 = IOMUX_PAD(0x02B8, 0x0058, 6, 0x0624, 0, 0), + MX8MP_PAD_ENET_MDIO__SIM_M_HADDR16 = IOMUX_PAD(0x02B8, 0x0058, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x02BC, 0x005C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x02BC, 0x005C, 2, 0x0524, 0, 0), + MX8MP_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02BC, 0x005C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD3__USDHC3_DATA6 = IOMUX_PAD(0x02BC, 0x005C, 6, 0x0628, 0, 0), + MX8MP_PAD_ENET_TD3__SIM_M_HADDR17 = IOMUX_PAD(0x02BC, 0x005C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x02C0, 0x0060, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x02C0, 0x0060, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x02C0, 0x0060, 2, 0x051C, 0, 0), + MX8MP_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02C0, 0x0060, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD2__USDHC3_DATA7 = IOMUX_PAD(0x02C0, 0x0060, 6, 0x062C, 0, 0), + MX8MP_PAD_ENET_TD2__SIM_M_HADDR18 = IOMUX_PAD(0x02C0, 0x0060, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x02C4, 0x0064, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x02C4, 0x0064, 2, 0x0520, 0, 0), + MX8MP_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02C4, 0x0064, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD1__USDHC3_CD_B = IOMUX_PAD(0x02C4, 0x0064, 6, 0x0608, 1, 0), + MX8MP_PAD_ENET_TD1__SIM_M_HADDR19 = IOMUX_PAD(0x02C4, 0x0064, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x02C8, 0x0068, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x02C8, 0x0068, 2, 0x0518, 0, 0), + MX8MP_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02C8, 0x0068, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TD0__USDHC3_WP = IOMUX_PAD(0x02C8, 0x0068, 6, 0x0634, 1, 0), + MX8MP_PAD_ENET_TD0__SIM_M_HADDR20 = IOMUX_PAD(0x02C8, 0x0068, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x02CC, 0x006C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x02CC, 0x006C, 2, 0x0514, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02CC, 0x006C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__USDHC3_DATA0 = IOMUX_PAD(0x02CC, 0x006C, 6, 0x0610, 0, 0), + MX8MP_PAD_ENET_TX_CTL__SIM_M_HADDR21 = IOMUX_PAD(0x02CC, 0x006C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x02D0, 0x0070, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x02D0, 0x0070, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x02D0, 0x0070, 2, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02D0, 0x0070, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_TXC__USDHC3_DATA1 = IOMUX_PAD(0x02D0, 0x0070, 6, 0x0614, 0, 0), + MX8MP_PAD_ENET_TXC__SIM_M_HADDR22 = IOMUX_PAD(0x02D0, 0x0070, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x02D4, 0x0074, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x02D4, 0x0074, 2, 0x0540, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 0, 0), + MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02D4, 0x0074, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RX_CTL__USDHC3_DATA2 = IOMUX_PAD(0x02D4, 0x0074, 6, 0x0618, 0, 0), + MX8MP_PAD_ENET_RX_CTL__SIM_M_HADDR23 = IOMUX_PAD(0x02D4, 0x0074, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x02D8, 0x0078, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x02D8, 0x0078, 1, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x02D8, 0x0078, 2, 0x053C, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 0, 0), + MX8MP_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02D8, 0x0078, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RXC__USDHC3_DATA3 = IOMUX_PAD(0x02D8, 0x0078, 6, 0x061C, 0, 0), + MX8MP_PAD_ENET_RXC__SIM_M_HADDR24 = IOMUX_PAD(0x02D8, 0x0078, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x02DC, 0x007C, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x02DC, 0x007C, 2, 0x0534, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 0, 0), + MX8MP_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02DC, 0x007C, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD0__USDHC3_DATA4 = IOMUX_PAD(0x02DC, 0x007C, 6, 0x0620, 0, 0), + MX8MP_PAD_ENET_RD0__SIM_M_HADDR25 = IOMUX_PAD(0x02DC, 0x007C, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x02E0, 0x0080, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x02E0, 0x0080, 2, 0x0538, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 0, 0), + MX8MP_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02E0, 0x0080, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__USDHC3_RESET_B = IOMUX_PAD(0x02E0, 0x0080, 6, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD1__SIM_M_HADDR26 = IOMUX_PAD(0x02E0, 0x0080, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x02E4, 0x0084, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x02E4, 0x0084, 2, 0x0530, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_CLK = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x02E4, 0x0084, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__USDHC3_CLK = IOMUX_PAD(0x02E4, 0x0084, 6, 0x0604, 0, 0), + MX8MP_PAD_ENET_RD2__SIM_M_HADDR27 = IOMUX_PAD(0x02E4, 0x0084, 7, 0x0000, 0, 0), + + MX8MP_PAD_ENET_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x02E8, 0x0088, 0, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x02E8, 0x0088, 2, 0x052C, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0), + MX8MP_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x02E8, 0x0088, 5, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD3__USDHC3_CMD = IOMUX_PAD(0x02E8, 0x0088, 6, 0x060C, 0, 0), + MX8MP_PAD_ENET_RD3__SIM_M_HADDR28 = IOMUX_PAD(0x02E8, 0x0088, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02EC, 0x008C, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__ENET1_MDC = IOMUX_PAD(0x02EC, 0x008C, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__I2C5_SCL = IOMUX_PAD(0x02EC, 0x008C, 3 | IOMUX_CONFIG_SION, 0x05C4, 0, 0), + MX8MP_PAD_SD1_CLK__UART1_DCE_TX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__UART1_DTE_RX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x05E8, 0, 0), + MX8MP_PAD_SD1_CLK__GPIO2_IO00 = IOMUX_PAD(0x02EC, 0x008C, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_CLK__SIM_M_HADDR29 = IOMUX_PAD(0x02EC, 0x008C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02F0, 0x0090, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__ENET1_MDIO = IOMUX_PAD(0x02F0, 0x0090, 1, 0x057C, 0, 0), + MX8MP_PAD_SD1_CMD__I2C5_SDA = IOMUX_PAD(0x02F0, 0x0090, 3 | IOMUX_CONFIG_SION, 0x05C8, 0, 0), + MX8MP_PAD_SD1_CMD__UART1_DCE_RX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x05E8, 1, 0), + MX8MP_PAD_SD1_CMD__UART1_DTE_TX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__GPIO2_IO01 = IOMUX_PAD(0x02F0, 0x0090, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_CMD__SIM_M_HADDR30 = IOMUX_PAD(0x02F0, 0x0090, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02F4, 0x0094, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__ENET1_RGMII_TD1 = IOMUX_PAD(0x02F4, 0x0094, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__I2C6_SCL = IOMUX_PAD(0x02F4, 0x0094, 3 | IOMUX_CONFIG_SION, 0x05CC, 0, 0), + MX8MP_PAD_SD1_DATA0__UART1_DCE_RTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x05E4, 0, 0), + MX8MP_PAD_SD1_DATA0__UART1_DTE_CTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__GPIO2_IO02 = IOMUX_PAD(0x02F4, 0x0094, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA0__SIM_M_HADDR31 = IOMUX_PAD(0x02F4, 0x0094, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02F8, 0x0098, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__ENET1_RGMII_TD0 = IOMUX_PAD(0x02F8, 0x0098, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__I2C6_SDA = IOMUX_PAD(0x02F8, 0x0098, 3 | IOMUX_CONFIG_SION, 0x05D0, 0, 0), + MX8MP_PAD_SD1_DATA1__UART1_DCE_CTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__UART1_DTE_RTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x05E4, 1, 0), + MX8MP_PAD_SD1_DATA1__GPIO2_IO03 = IOMUX_PAD(0x02F8, 0x0098, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA1__SIM_M_HBURST00 = IOMUX_PAD(0x02F8, 0x0098, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02FC, 0x009C, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__ENET1_RGMII_RD0 = IOMUX_PAD(0x02FC, 0x009C, 1, 0x0580, 0, 0), + MX8MP_PAD_SD1_DATA2__I2C4_SCL = IOMUX_PAD(0x02FC, 0x009C, 3 | IOMUX_CONFIG_SION, 0x05BC, 0, 0), + MX8MP_PAD_SD1_DATA2__UART2_DCE_TX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__UART2_DTE_RX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x05F0, 0, 0), + MX8MP_PAD_SD1_DATA2__GPIO2_IO04 = IOMUX_PAD(0x02FC, 0x009C, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA2__SIM_M_HBURST01 = IOMUX_PAD(0x02FC, 0x009C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x0300, 0x00A0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__ENET1_RGMII_RD1 = IOMUX_PAD(0x0300, 0x00A0, 1, 0x0584, 0, 0), + MX8MP_PAD_SD1_DATA3__I2C4_SDA = IOMUX_PAD(0x0300, 0x00A0, 3 | IOMUX_CONFIG_SION, 0x05C0, 0, 0), + MX8MP_PAD_SD1_DATA3__UART2_DCE_RX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x05F0, 1, 0), + MX8MP_PAD_SD1_DATA3__UART2_DTE_TX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__GPIO2_IO05 = IOMUX_PAD(0x0300, 0x00A0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA3__SIM_M_HBURST02 = IOMUX_PAD(0x0300, 0x00A0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0304, 0x00A4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0304, 0x00A4, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__I2C1_SCL = IOMUX_PAD(0x0304, 0x00A4, 3 | IOMUX_CONFIG_SION, 0x05A4, 0, 0), + MX8MP_PAD_SD1_DATA4__UART2_DCE_RTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x05EC, 0, 0), + MX8MP_PAD_SD1_DATA4__UART2_DTE_CTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__GPIO2_IO06 = IOMUX_PAD(0x0304, 0x00A4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA4__SIM_M_HRESP = IOMUX_PAD(0x0304, 0x00A4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0308, 0x00A8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__ENET1_TX_ER = IOMUX_PAD(0x0308, 0x00A8, 1, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__I2C1_SDA = IOMUX_PAD(0x0308, 0x00A8, 3 | IOMUX_CONFIG_SION, 0x05A8, 0, 0), + MX8MP_PAD_SD1_DATA5__UART2_DCE_CTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__UART2_DTE_RTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x05EC, 1, 0), + MX8MP_PAD_SD1_DATA5__GPIO2_IO07 = IOMUX_PAD(0x0308, 0x00A8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA5__TPSMP_HDATA05 = IOMUX_PAD(0x0308, 0x00A8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x030C, 0x00AC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x030C, 0x00AC, 1, 0x0588, 0, 0), + MX8MP_PAD_SD1_DATA6__I2C2_SCL = IOMUX_PAD(0x030C, 0x00AC, 3 | IOMUX_CONFIG_SION, 0x05AC, 0, 0), + MX8MP_PAD_SD1_DATA6__UART3_DCE_TX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__UART3_DTE_RX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x05F8, 0, 0), + MX8MP_PAD_SD1_DATA6__GPIO2_IO08 = IOMUX_PAD(0x030C, 0x00AC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA6__TPSMP_HDATA06 = IOMUX_PAD(0x030C, 0x00AC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x0310, 0x00B0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__ENET1_RX_ER = IOMUX_PAD(0x0310, 0x00B0, 1, 0x058C, 0, 0), + MX8MP_PAD_SD1_DATA7__I2C2_SDA = IOMUX_PAD(0x0310, 0x00B0, 3 | IOMUX_CONFIG_SION, 0x05B0, 0, 0), + MX8MP_PAD_SD1_DATA7__UART3_DCE_RX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x05F8, 1, 0), + MX8MP_PAD_SD1_DATA7__UART3_DTE_TX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__GPIO2_IO09 = IOMUX_PAD(0x0310, 0x00B0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_DATA7__TPSMP_HDATA07 = IOMUX_PAD(0x0310, 0x00B0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0314, 0x00B4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__ENET1_TX_CLK = IOMUX_PAD(0x0314, 0x00B4, 1, 0x0578, 0, 0), + MX8MP_PAD_SD1_RESET_B__I2C3_SCL = IOMUX_PAD(0x0314, 0x00B4, 3 | IOMUX_CONFIG_SION, 0x05B4, 0, 0), + MX8MP_PAD_SD1_RESET_B__UART3_DCE_RTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x05F4, 0, 0), + MX8MP_PAD_SD1_RESET_B__UART3_DTE_CTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0314, 0x00B4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_RESET_B__ECSPI3_TEST_TRIG = IOMUX_PAD(0x0314, 0x00B4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0318, 0x00B8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0318, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x05B8, 0, 0), + MX8MP_PAD_SD1_STROBE__UART3_DCE_CTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__UART3_DTE_RTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x05F4, 1, 0), + MX8MP_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0318, 0x00B8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD1_STROBE__USDHC3_TEST_TRIG = IOMUX_PAD(0x0318, 0x00B8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x00BC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x031C, 0x00BC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK = IOMUX_PAD(0x031C, 0x00BC, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0320, 0x00C0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__ECSPI2_SCLK = IOMUX_PAD(0x0320, 0x00C0, 2, 0x0568, 0, 0), + MX8MP_PAD_SD2_CLK__UART4_DCE_RX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0600, 0, 0), + MX8MP_PAD_SD2_CLK__UART4_DTE_TX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x0320, 0x00C0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0320, 0x00C0, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_CLK__OBSERVE_MUX_OUT00 = IOMUX_PAD(0x0320, 0x00C0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0324, 0x00C4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__ECSPI2_MOSI = IOMUX_PAD(0x0324, 0x00C4, 2, 0x0570, 0, 0), + MX8MP_PAD_SD2_CMD__UART4_DCE_TX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__UART4_DTE_RX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0600, 1, 0), + MX8MP_PAD_SD2_CMD__AUDIOMIX_CLK = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0324, 0x00C4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0324, 0x00C4, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__OBSERVE_MUX_OUT01 = IOMUX_PAD(0x0324, 0x00C4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0328, 0x00C8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0328, 0x00C8, 2 | IOMUX_CONFIG_SION, 0x05C0, 1, 0), + MX8MP_PAD_SD2_DATA0__UART2_DCE_RX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x05F0, 2, 0), + MX8MP_PAD_SD2_DATA0__UART2_DTE_TX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 1, 0), + MX8MP_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0328, 0x00C8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x0328, 0x00C8, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA0__OBSERVE_MUX_OUT02 = IOMUX_PAD(0x0328, 0x00C8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x032C, 0x00CC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x032C, 0x00CC, 2 | IOMUX_CONFIG_SION, 0x05BC, 1, 0), + MX8MP_PAD_SD2_DATA1__UART2_DCE_TX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__UART2_DTE_RX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x05F0, 3, 0), + MX8MP_PAD_SD2_DATA1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 1, 0), + MX8MP_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x032C, 0x00CC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x032C, 0x00CC, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA1__OBSERVE_MUX_OUT03 = IOMUX_PAD(0x032C, 0x00CC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0330, 0x00D0, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__ECSPI2_SS0 = IOMUX_PAD(0x0330, 0x00D0, 2, 0x0574, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 1, 0), + MX8MP_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x0330, 0x00D0, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0330, 0x00D0, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__OBSERVE_MUX_OUT04 = IOMUX_PAD(0x0330, 0x00D0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0334, 0x00D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__ECSPI2_MISO = IOMUX_PAD(0x0334, 0x00D4, 2, 0x056C, 0, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 1, 0), + MX8MP_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0334, 0x00D4, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0338, 0x00D8, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0338, 0x00D8, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0), + + MX8MP_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x033C, 0x00DC, 0, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x033C, 0x00DC, 5, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__CORESIGHT_EVENTI = IOMUX_PAD(0x033C, 0x00DC, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_WP__SIM_M_HMASTLOCK = IOMUX_PAD(0x033C, 0x00DC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__FLEXSPI_A_SCLK = IOMUX_PAD(0x0340, 0x00E0, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0340, 0x00E0, 2, 0x04E8, 0, 0), + MX8MP_PAD_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0), + MX8MP_PAD_NAND_ALE__UART3_DCE_RX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x05F8, 2, 0), + MX8MP_PAD_NAND_ALE__UART3_DTE_TX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__GPIO3_IO00 = IOMUX_PAD(0x0340, 0x00E0, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__CORESIGHT_TRACE_CLK = IOMUX_PAD(0x0340, 0x00E0, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__SIM_M_HPROT00 = IOMUX_PAD(0x0340, 0x00E0, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__FLEXSPI_A_SS0_B = IOMUX_PAD(0x0344, 0x00E4, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x0344, 0x00E4, 2, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0), + MX8MP_PAD_NAND_CE0_B__UART3_DCE_TX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__UART3_DTE_RX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x05F8, 3, 0), + MX8MP_PAD_NAND_CE0_B__GPIO3_IO01 = IOMUX_PAD(0x0344, 0x00E4, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL = IOMUX_PAD(0x0344, 0x00E4, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__SIM_M_HPROT01 = IOMUX_PAD(0x0344, 0x00E4, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__FLEXSPI_A_SS1_B = IOMUX_PAD(0x0348, 0x00E8, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE = IOMUX_PAD(0x0348, 0x00E8, 2, 0x0630, 1, 0), + MX8MP_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E8, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0), + MX8MP_PAD_NAND_CE1_B__GPIO3_IO02 = IOMUX_PAD(0x0348, 0x00E8, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__CORESIGHT_TRACE00 = IOMUX_PAD(0x0348, 0x00E8, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__SIM_M_HPROT02 = IOMUX_PAD(0x0348, 0x00E8, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__FLEXSPI_B_SS0_B = IOMUX_PAD(0x034C, 0x00EC, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 = IOMUX_PAD(0x034C, 0x00EC, 2, 0x0624, 1, 0), + MX8MP_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x034C, 0x00EC, 4 | IOMUX_CONFIG_SION, 0x05C0, 2, 0), + MX8MP_PAD_NAND_CE2_B__GPIO3_IO03 = IOMUX_PAD(0x034C, 0x00EC, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__CORESIGHT_TRACE01 = IOMUX_PAD(0x034C, 0x00EC, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__SIM_M_HPROT03 = IOMUX_PAD(0x034C, 0x00EC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__FLEXSPI_B_SS1_B = IOMUX_PAD(0x0350, 0x00F0, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 = IOMUX_PAD(0x0350, 0x00F0, 2, 0x0628, 1, 0), + MX8MP_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x0350, 0x00F0, 4 | IOMUX_CONFIG_SION, 0x05B8, 1, 0), + MX8MP_PAD_NAND_CE3_B__GPIO3_IO04 = IOMUX_PAD(0x0350, 0x00F0, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__CORESIGHT_TRACE02 = IOMUX_PAD(0x0350, 0x00F0, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__SIM_M_HADDR00 = IOMUX_PAD(0x0350, 0x00F0, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__FLEXSPI_B_SCLK = IOMUX_PAD(0x0354, 0x00F4, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 = IOMUX_PAD(0x0354, 0x00F4, 2, 0x062C, 1, 0), + MX8MP_PAD_NAND_CLE__UART4_DCE_RX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0600, 2, 0), + MX8MP_PAD_NAND_CLE__UART4_DTE_TX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__GPIO3_IO05 = IOMUX_PAD(0x0354, 0x00F4, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__CORESIGHT_TRACE03 = IOMUX_PAD(0x0354, 0x00F4, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__SIM_M_HADDR01 = IOMUX_PAD(0x0354, 0x00F4, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__FLEXSPI_A_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 2, 0x04E4, 0, 0), + MX8MP_PAD_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__UART4_DCE_RX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0600, 3, 0), + MX8MP_PAD_NAND_DATA00__UART4_DTE_TX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__GPIO3_IO06 = IOMUX_PAD(0x0358, 0x00F8, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__CORESIGHT_TRACE04 = IOMUX_PAD(0x0358, 0x00F8, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__SIM_M_HADDR02 = IOMUX_PAD(0x0358, 0x00F8, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__FLEXSPI_A_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x035C, 0x00FC, 2, 0x04EC, 0, 0), + MX8MP_PAD_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__UART4_DCE_TX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__UART4_DTE_RX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0600, 4, 0), + MX8MP_PAD_NAND_DATA01__GPIO3_IO07 = IOMUX_PAD(0x035C, 0x00FC, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__CORESIGHT_TRACE05 = IOMUX_PAD(0x035C, 0x00FC, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__SIM_M_HADDR03 = IOMUX_PAD(0x035C, 0x00FC, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__FLEXSPI_A_DATA02 = IOMUX_PAD(0x0360, 0x0100, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__USDHC3_CD_B = IOMUX_PAD(0x0360, 0x0100, 2, 0x0608, 2, 0), + MX8MP_PAD_NAND_DATA02__UART4_DCE_CTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__UART4_DTE_RTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x05FC, 0, 0), + MX8MP_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x0360, 0x0100, 4 | IOMUX_CONFIG_SION, 0x05C0, 3, 0), + MX8MP_PAD_NAND_DATA02__GPIO3_IO08 = IOMUX_PAD(0x0360, 0x0100, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__CORESIGHT_TRACE06 = IOMUX_PAD(0x0360, 0x0100, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__SIM_M_HADDR04 = IOMUX_PAD(0x0360, 0x0100, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__FLEXSPI_A_DATA03 = IOMUX_PAD(0x0364, 0x0104, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__USDHC3_WP = IOMUX_PAD(0x0364, 0x0104, 2, 0x0634, 2, 0), + MX8MP_PAD_NAND_DATA03__UART4_DCE_RTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x05FC, 1, 0), + MX8MP_PAD_NAND_DATA03__UART4_DTE_CTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0), + MX8MP_PAD_NAND_DATA03__GPIO3_IO09 = IOMUX_PAD(0x0364, 0x0104, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__CORESIGHT_TRACE07 = IOMUX_PAD(0x0364, 0x0104, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__SIM_M_HADDR05 = IOMUX_PAD(0x0364, 0x0104, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__FLEXSPI_B_DATA00 = IOMUX_PAD(0x0368, 0x0108, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 = IOMUX_PAD(0x0368, 0x0108, 2, 0x0610, 1, 0), + MX8MP_PAD_NAND_DATA04__FLEXSPI_A_DATA04 = IOMUX_PAD(0x0368, 0x0108, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0), + MX8MP_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0368, 0x0108, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__CORESIGHT_TRACE08 = IOMUX_PAD(0x0368, 0x0108, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__SIM_M_HADDR06 = IOMUX_PAD(0x0368, 0x0108, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__FLEXSPI_B_DATA01 = IOMUX_PAD(0x036C, 0x010C, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 = IOMUX_PAD(0x036C, 0x010C, 2, 0x0614, 1, 0), + MX8MP_PAD_NAND_DATA05__FLEXSPI_A_DATA05 = IOMUX_PAD(0x036C, 0x010C, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x036C, 0x010C, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__CORESIGHT_TRACE09 = IOMUX_PAD(0x036C, 0x010C, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__SIM_M_HADDR07 = IOMUX_PAD(0x036C, 0x010C, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__FLEXSPI_B_DATA02 = IOMUX_PAD(0x0370, 0x0110, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 = IOMUX_PAD(0x0370, 0x0110, 2, 0x0618, 1, 0), + MX8MP_PAD_NAND_DATA06__FLEXSPI_A_DATA06 = IOMUX_PAD(0x0370, 0x0110, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x0370, 0x0110, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__CORESIGHT_TRACE10 = IOMUX_PAD(0x0370, 0x0110, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__SIM_M_HADDR08 = IOMUX_PAD(0x0370, 0x0110, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__FLEXSPI_B_DATA03 = IOMUX_PAD(0x0374, 0x0114, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 = IOMUX_PAD(0x0374, 0x0114, 2, 0x061C, 1, 0), + MX8MP_PAD_NAND_DATA07__FLEXSPI_A_DATA07 = IOMUX_PAD(0x0374, 0x0114, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0374, 0x0114, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__CORESIGHT_TRACE11 = IOMUX_PAD(0x0374, 0x0114, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__SIM_M_HADDR09 = IOMUX_PAD(0x0374, 0x0114, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__FLEXSPI_A_DQS = IOMUX_PAD(0x0378, 0x0118, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0378, 0x0118, 2, 0x04E0, 0, 0), + MX8MP_PAD_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0378, 0x0118, 4 | IOMUX_CONFIG_SION, 0x05B4, 1, 0), + MX8MP_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0378, 0x0118, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__CORESIGHT_TRACE12 = IOMUX_PAD(0x0378, 0x0118, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__SIM_M_HADDR10 = IOMUX_PAD(0x0378, 0x0118, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__FLEXSPI_B_DQS = IOMUX_PAD(0x037C, 0x011C, 1, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 = IOMUX_PAD(0x037C, 0x011C, 2, 0x0620, 1, 0), + MX8MP_PAD_NAND_RE_B__UART4_DCE_TX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__UART4_DTE_RX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0600, 5, 0), + MX8MP_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x037C, 0x011C, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__CORESIGHT_TRACE13 = IOMUX_PAD(0x037C, 0x011C, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__SIM_M_HADDR11 = IOMUX_PAD(0x037C, 0x011C, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B = IOMUX_PAD(0x0380, 0x0120, 2, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x0380, 0x0120, 4 | IOMUX_CONFIG_SION, 0x05B4, 2, 0), + MX8MP_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x0380, 0x0120, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__CORESIGHT_TRACE14 = IOMUX_PAD(0x0380, 0x0120, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__SIM_M_HADDR12 = IOMUX_PAD(0x0380, 0x0120, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x0384, 0x0124, 2, 0x0604, 1, 0), + MX8MP_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x0384, 0x0124, 4 | IOMUX_CONFIG_SION, 0x05B8, 2, 0), + MX8MP_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x0384, 0x0124, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__CORESIGHT_TRACE15 = IOMUX_PAD(0x0384, 0x0124, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__SIM_M_HADDR13 = IOMUX_PAD(0x0384, 0x0124, 7, 0x0000, 0, 0), + + MX8MP_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__USDHC3_CMD = IOMUX_PAD(0x0388, 0x0128, 2, 0x060C, 1, 0), + MX8MP_PAD_NAND_WP_B__I2C4_SCL = IOMUX_PAD(0x0388, 0x0128, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0), + MX8MP_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x0388, 0x0128, 5, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__CORESIGHT_EVENTO = IOMUX_PAD(0x0388, 0x0128, 6, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__SIM_M_HADDR14 = IOMUX_PAD(0x0388, 0x0128, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x038C, 0x012C, 0, 0x0508, 0, 0), + MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x038C, 0x012C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXFS__PWM4_OUT = IOMUX_PAD(0x038C, 0x012C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXFS__I2C6_SCL = IOMUX_PAD(0x038C, 0x012C, 3 | IOMUX_CONFIG_SION, 0x05CC, 1, 0), + MX8MP_PAD_SAI5_RXFS__GPIO3_IO19 = IOMUX_PAD(0x038C, 0x012C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x0390, 0x0130, 0, 0x04F4, 0, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x0390, 0x0130, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__PWM3_OUT = IOMUX_PAD(0x0390, 0x0130, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__I2C6_SDA = IOMUX_PAD(0x0390, 0x0130, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x0390, 0x0130, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0394, 0x0134, 0, 0x04F8, 0, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x0394, 0x0134, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD0__PWM2_OUT = IOMUX_PAD(0x0394, 0x0134, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD0__I2C5_SCL = IOMUX_PAD(0x0394, 0x0134, 3 | IOMUX_CONFIG_SION, 0x05C4, 1, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 2, 0), + MX8MP_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x0394, 0x0134, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0398, 0x0138, 0, 0x04FC, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x0398, 0x0138, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 2, 0x04D8, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 3, 0x0510, 0, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 2, 0), + MX8MP_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x0398, 0x0138, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD1__CAN1_TX = IOMUX_PAD(0x0398, 0x0138, 6, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x039C, 0x013C, 0, 0x0500, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x039C, 0x013C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x039C, 0x013C, 2, 0x04D8, 1, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x039C, 0x013C, 3, 0x050C, 0, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 2, 0), + MX8MP_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x039C, 0x013C, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD2__CAN1_RX = IOMUX_PAD(0x039C, 0x013C, 6, 0x054C, 0, 0), + + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03A0, 0x0140, 0, 0x0504, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03A0, 0x0140, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03A0, 0x0140, 2, 0x04D8, 2, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03A0, 0x0140, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 2, 0), + MX8MP_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03A0, 0x0140, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXD3__CAN2_TX = IOMUX_PAD(0x03A0, 0x0140, 6, 0x0000, 0, 0), + + MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03A4, 0x0144, 0, 0x04F0, 0, 0), + MX8MP_PAD_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03A4, 0x0144, 1, 0x04D4, 0, 0), + MX8MP_PAD_SAI5_MCLK__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0144, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI5_MCLK__I2C5_SDA = IOMUX_PAD(0x03A4, 0x0144, 3 | IOMUX_CONFIG_SION, 0x05C8, 1, 0), + MX8MP_PAD_SAI5_MCLK__GPIO3_IO25 = IOMUX_PAD(0x03A4, 0x0144, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI5_MCLK__CAN2_RX = IOMUX_PAD(0x03A4, 0x0144, 6, 0x0550, 0, 0), + + MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 0, 0x04D0, 0, 0), + MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 1, 0x0508, 1, 0), + MX8MP_PAD_SAI1_RXFS__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0148, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXFS__GPIO4_IO00 = IOMUX_PAD(0x03A8, 0x0148, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 1, 0x04F4, 1, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x014C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__GPIO4_IO01 = IOMUX_PAD(0x03AC, 0x014C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 1, 0x04F8, 1, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03B0, 0x0150, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 3, 0), + MX8MP_PAD_SAI1_RXD0__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0150, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 = IOMUX_PAD(0x03B0, 0x0150, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 1, 0x04FC, 1, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 3, 0), + MX8MP_PAD_SAI1_RXD1__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0154, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD1__GPIO4_IO03 = IOMUX_PAD(0x03B4, 0x0154, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 1, 0x0500, 1, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 3, 0), + MX8MP_PAD_SAI1_RXD2__ENET1_MDC = IOMUX_PAD(0x03B8, 0x0158, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD2__GPIO4_IO04 = IOMUX_PAD(0x03B8, 0x0158, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 1, 0x0504, 1, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 3, 0), + MX8MP_PAD_SAI1_RXD3__ENET1_MDIO = IOMUX_PAD(0x03BC, 0x015C, 4, 0x057C, 1, 0), + MX8MP_PAD_SAI1_RXD3__GPIO4_IO05 = IOMUX_PAD(0x03BC, 0x015C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 = IOMUX_PAD(0x03C0, 0x0160, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x03C0, 0x0160, 1, 0x0524, 1, 0), + MX8MP_PAD_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x03C0, 0x0160, 2, 0x0518, 1, 0), + MX8MP_PAD_SAI1_RXD4__ENET1_RGMII_RD0 = IOMUX_PAD(0x03C0, 0x0160, 4, 0x0580, 1, 0), + MX8MP_PAD_SAI1_RXD4__GPIO4_IO06 = IOMUX_PAD(0x03C0, 0x0160, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 = IOMUX_PAD(0x03C4, 0x0164, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x03C4, 0x0164, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x03C4, 0x0164, 2, 0x051C, 1, 0), + MX8MP_PAD_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x0164, 3, 0x04D0, 1, 0), + MX8MP_PAD_SAI1_RXD5__ENET1_RGMII_RD1 = IOMUX_PAD(0x03C4, 0x0164, 4, 0x0584, 1, 0), + MX8MP_PAD_SAI1_RXD5__GPIO4_IO07 = IOMUX_PAD(0x03C4, 0x0164, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 = IOMUX_PAD(0x03C8, 0x0168, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x03C8, 0x0168, 1, 0x0528, 1, 0), + MX8MP_PAD_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x03C8, 0x0168, 2, 0x0520, 1, 0), + MX8MP_PAD_SAI1_RXD6__ENET1_RGMII_RD2 = IOMUX_PAD(0x03C8, 0x0168, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD6__GPIO4_IO08 = IOMUX_PAD(0x03C8, 0x0168, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 = IOMUX_PAD(0x03CC, 0x016C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03CC, 0x016C, 1, 0x0514, 1, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03CC, 0x016C, 2, 0x04D8, 3, 0), + MX8MP_PAD_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x03CC, 0x016C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__ENET1_RGMII_RD3 = IOMUX_PAD(0x03CC, 0x016C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXD7__GPIO4_IO09 = IOMUX_PAD(0x03CC, 0x016C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 0, 0x04D8, 4, 0), + MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 1, 0x0510, 1, 0), + MX8MP_PAD_SAI1_TXFS__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x03D0, 0x0170, 4, 0x0588, 1, 0), + MX8MP_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03D0, 0x0170, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 0, 0x04D4, 1, 0), + MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 1, 0x050C, 1, 0), + MX8MP_PAD_SAI1_TXC__ENET1_RGMII_RXC = IOMUX_PAD(0x03D4, 0x0174, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03D4, 0x0174, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x03D8, 0x0178, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03D8, 0x0178, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x03DC, 0x017C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03DC, 0x017C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x03E0, 0x0180, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03E0, 0x0180, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x03E4, 0x0184, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x03E4, 0x0184, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x03E8, 0x0188, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x03E8, 0x0188, 1, 0x0518, 2, 0), + MX8MP_PAD_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x03E8, 0x0188, 2, 0x0524, 2, 0), + MX8MP_PAD_SAI1_TXD4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x03E8, 0x0188, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD4__GPIO4_IO16 = IOMUX_PAD(0x03E8, 0x0188, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03EC, 0x018C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x03EC, 0x018C, 1, 0x051C, 2, 0), + MX8MP_PAD_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x03EC, 0x018C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__ENET1_RGMII_TXC = IOMUX_PAD(0x03EC, 0x018C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD5__GPIO4_IO17 = IOMUX_PAD(0x03EC, 0x018C, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 = IOMUX_PAD(0x03F0, 0x0190, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x03F0, 0x0190, 1, 0x0520, 2, 0), + MX8MP_PAD_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x03F0, 0x0190, 2, 0x0528, 2, 0), + MX8MP_PAD_SAI1_TXD6__ENET1_RX_ER = IOMUX_PAD(0x03F0, 0x0190, 4, 0x058C, 1, 0), + MX8MP_PAD_SAI1_TXD6__GPIO4_IO18 = IOMUX_PAD(0x03F0, 0x0190, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 = IOMUX_PAD(0x03F4, 0x0194, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03F4, 0x0194, 1, 0x0514, 2, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_CLK = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__ENET1_TX_ER = IOMUX_PAD(0x03F4, 0x0194, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x03F4, 0x0194, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_MCLK = IOMUX_PAD(0x03F8, 0x0198, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03F8, 0x0198, 1, 0x04F0, 1, 0), + MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03F8, 0x0198, 2, 0x04D4, 2, 0), + MX8MP_PAD_SAI1_MCLK__ENET1_TX_CLK = IOMUX_PAD(0x03F8, 0x0198, 4, 0x0578, 1, 0), + MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x03F8, 0x0198, 5, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC = IOMUX_PAD(0x03FC, 0x019C, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03FC, 0x019C, 1, 0x0510, 2, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03FC, 0x019C, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x03FC, 0x019C, 3, 0x04DC, 0, 0), + MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__UART1_DTE_RX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x05E8, 2, 0), + MX8MP_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x03FC, 0x019C, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 4, 0), + MX8MP_PAD_SAI2_RXFS__SIM_M_HSIZE00 = IOMUX_PAD(0x03FC, 0x019C, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 1, 0x050C, 2, 0), + MX8MP_PAD_SAI2_RXC__CAN1_TX = IOMUX_PAD(0x0400, 0x01A0, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__UART1_DCE_RX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x05E8, 3, 0), + MX8MP_PAD_SAI2_RXC__UART1_DTE_TX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x0400, 0x01A0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 4, 0), + MX8MP_PAD_SAI2_RXC__SIM_M_HSIZE01 = IOMUX_PAD(0x0400, 0x01A0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT = IOMUX_PAD(0x0404, 0x01A4, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0404, 0x01A4, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__UART1_DCE_RTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x05E4, 2, 0), + MX8MP_PAD_SAI2_RXD0__UART1_DTE_CTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0404, 0x01A4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 4, 0), + MX8MP_PAD_SAI2_RXD0__SIM_M_HSIZE02 = IOMUX_PAD(0x0404, 0x01A4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC = IOMUX_PAD(0x0408, 0x01A8, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT = IOMUX_PAD(0x0408, 0x01A8, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__UART1_DCE_CTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__UART1_DTE_RTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x05E4, 3, 0), + MX8MP_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x01A8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 5, 0), + MX8MP_PAD_SAI2_TXFS__SIM_M_HWRITE = IOMUX_PAD(0x0408, 0x01A8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK = IOMUX_PAD(0x040C, 0x01AC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x040C, 0x01AC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__CAN1_RX = IOMUX_PAD(0x040C, 0x01AC, 3, 0x054C, 1, 0), + MX8MP_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x01AC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 5, 0), + MX8MP_PAD_SAI2_TXC__SIM_M_HREADYOUT = IOMUX_PAD(0x040C, 0x01AC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 = IOMUX_PAD(0x0410, 0x01B0, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x0410, 0x01B0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN = IOMUX_PAD(0x0410, 0x01B0, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__CAN2_TX = IOMUX_PAD(0x0410, 0x01B0, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN = IOMUX_PAD(0x0410, 0x01B0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x01B0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 = IOMUX_PAD(0x0410, 0x01B0, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXD0__TPSMP_CLK = IOMUX_PAD(0x0410, 0x01B0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI2_MCLK = IOMUX_PAD(0x0414, 0x01B4, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01B4, 1, 0x04F0, 2, 0), + MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN = IOMUX_PAD(0x0414, 0x01B4, 2, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__CAN2_RX = IOMUX_PAD(0x0414, 0x01B4, 3, 0x0550, 1, 0), + MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN = IOMUX_PAD(0x0414, 0x01B4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x01B4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0414, 0x01B4, 6, 0x04E0, 1, 0), + MX8MP_PAD_SAI2_MCLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x0414, 0x01B4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 1, 0x04DC, 1, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 2, 0x0508, 2, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0), + MX8MP_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x01B8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 4, 0), + MX8MP_PAD_SAI3_RXFS__TPSMP_HTRANS00 = IOMUX_PAD(0x0418, 0x01B8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 = IOMUX_PAD(0x041C, 0x01BC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 2, 0x04F4, 2, 0), + MX8MP_PAD_SAI3_RXC__GPT1_CLK = IOMUX_PAD(0x041C, 0x01BC, 3, 0x059C, 0, 0), + MX8MP_PAD_SAI3_RXC__UART2_DCE_CTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__UART2_DTE_RTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x05EC, 2, 0), + MX8MP_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x01BC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__TPSMP_HTRANS01 = IOMUX_PAD(0x041C, 0x01BC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 0, 0x04E4, 1, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 = IOMUX_PAD(0x0420, 0x01C0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 2, 0x04F8, 2, 0), + MX8MP_PAD_SAI3_RXD__UART2_DCE_RTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x05EC, 3, 0), + MX8MP_PAD_SAI3_RXD__UART2_DTE_CTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x01C0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 6, 0), + MX8MP_PAD_SAI3_RXD__TPSMP_HDATA00 = IOMUX_PAD(0x0420, 0x01C0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x0424, 0x01C4, 0, 0x04EC, 1, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 2, 0x04FC, 2, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__UART2_DCE_RX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x05F0, 4, 0), + MX8MP_PAD_SAI3_TXFS__UART2_DTE_TX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0424, 0x01C4, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 5, 0), + MX8MP_PAD_SAI3_TXFS__TPSMP_HDATA01 = IOMUX_PAD(0x0424, 0x01C4, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0428, 0x01C8, 0, 0x04E8, 1, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 2, 0x0500, 2, 0), + MX8MP_PAD_SAI3_TXC__GPT1_CAPTURE1 = IOMUX_PAD(0x0428, 0x01C8, 3, 0x0594, 0, 0), + MX8MP_PAD_SAI3_TXC__UART2_DCE_TX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__UART2_DTE_RX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x05F0, 5, 0), + MX8MP_PAD_SAI3_TXC__GPIO5_IO00 = IOMUX_PAD(0x0428, 0x01C8, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 6, 0), + MX8MP_PAD_SAI3_TXC__TPSMP_HDATA02 = IOMUX_PAD(0x0428, 0x01C8, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x042C, 0x01CC, 0, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 2, 0x0504, 2, 0), + MX8MP_PAD_SAI3_TXD__GPT1_CAPTURE2 = IOMUX_PAD(0x042C, 0x01CC, 3, 0x0598, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0), + MX8MP_PAD_SAI3_TXD__GPIO5_IO01 = IOMUX_PAD(0x042C, 0x01CC, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 = IOMUX_PAD(0x042C, 0x01CC, 6, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXD__TPSMP_HDATA03 = IOMUX_PAD(0x042C, 0x01CC, 7, 0x0000, 0, 0), + + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0430, 0x01D0, 0, 0x04E0, 2, 0), + MX8MP_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x0430, 0x01D0, 1, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01D0, 2, 0x04F0, 3, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__GPIO5_IO02 = IOMUX_PAD(0x0430, 0x01D0, 5, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0), + MX8MP_PAD_SAI3_MCLK__TPSMP_HDATA04 = IOMUX_PAD(0x0430, 0x01D0, 7, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0434, 0x01D4, 1, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__I2C5_SCL = IOMUX_PAD(0x0434, 0x01D4, 2 | IOMUX_CONFIG_SION, 0x05C4, 2, 0), + MX8MP_PAD_SPDIF_TX__GPT1_COMPARE1 = IOMUX_PAD(0x0434, 0x01D4, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__CAN1_TX = IOMUX_PAD(0x0434, 0x01D4, 4, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__GPIO5_IO03 = IOMUX_PAD(0x0434, 0x01D4, 5, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0), + MX8MP_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0438, 0x01D8, 1, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_RX__I2C5_SDA = IOMUX_PAD(0x0438, 0x01D8, 2 | IOMUX_CONFIG_SION, 0x05C8, 2, 0), + MX8MP_PAD_SPDIF_RX__GPT1_COMPARE2 = IOMUX_PAD(0x0438, 0x01D8, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_RX__CAN1_RX = IOMUX_PAD(0x0438, 0x01D8, 4, 0x054C, 2, 0), + MX8MP_PAD_SPDIF_RX__GPIO5_IO04 = IOMUX_PAD(0x0438, 0x01D8, 5, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_EXT_CLK__GPT1_COMPARE3 = IOMUX_PAD(0x043C, 0x01DC, 3, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05 = IOMUX_PAD(0x043C, 0x01DC, 5, 0x0000, 0, 0), + + MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0), + MX8MP_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x043C, 0x01DC, 1, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0440, 0x01E0, 0, 0x0558, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX = IOMUX_PAD(0x0440, 0x01E0, 1, 0x05F8, 4, 0), + MX8MP_PAD_ECSPI1_SCLK__UART3_DTE_TX = IOMUX_PAD(0x0440, 0x01E0, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x0440, 0x01E0, 2 | IOMUX_CONFIG_SION, 0x05A4, 1, 0), + MX8MP_PAD_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x0440, 0x01E0, 3, 0x0538, 1, 0), + MX8MP_PAD_ECSPI1_SCLK__GPIO5_IO06 = IOMUX_PAD(0x0440, 0x01E0, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SCLK__TPSMP_HDATA08 = IOMUX_PAD(0x0440, 0x01E0, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0444, 0x01E4, 0, 0x0560, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x05F8, 5, 0), + MX8MP_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0444, 0x01E4, 2 | IOMUX_CONFIG_SION, 0x05A8, 1, 0), + MX8MP_PAD_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x0444, 0x01E4, 3, 0x0530, 1, 0), + MX8MP_PAD_ECSPI1_MOSI__GPIO5_IO07 = IOMUX_PAD(0x0444, 0x01E4, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MOSI__TPSMP_HDATA09 = IOMUX_PAD(0x0444, 0x01E4, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0448, 0x01E8, 0, 0x055C, 0, 0), + MX8MP_PAD_ECSPI1_MISO__UART3_DCE_CTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MISO__UART3_DTE_RTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x05F4, 2, 0), + MX8MP_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0448, 0x01E8, 2 | IOMUX_CONFIG_SION, 0x05AC, 1, 0), + MX8MP_PAD_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x0448, 0x01E8, 3, 0x0534, 1, 0), + MX8MP_PAD_ECSPI1_MISO__GPIO5_IO08 = IOMUX_PAD(0x0448, 0x01E8, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_MISO__TPSMP_HDATA10 = IOMUX_PAD(0x0448, 0x01E8, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x044C, 0x01EC, 0, 0x0564, 0, 0), + MX8MP_PAD_ECSPI1_SS0__UART3_DCE_RTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x05F4, 3, 0), + MX8MP_PAD_ECSPI1_SS0__UART3_DTE_CTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x044C, 0x01EC, 2 | IOMUX_CONFIG_SION, 0x05B0, 1, 0), + MX8MP_PAD_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x044C, 0x01EC, 3, 0x0540, 1, 0), + MX8MP_PAD_ECSPI1_SS0__GPIO5_IO09 = IOMUX_PAD(0x044C, 0x01EC, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI1_SS0__TPSMP_HDATA11 = IOMUX_PAD(0x044C, 0x01EC, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0450, 0x01F0, 0, 0x0568, 1, 0), + MX8MP_PAD_ECSPI2_SCLK__UART4_DCE_RX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0600, 6, 0), + MX8MP_PAD_ECSPI2_SCLK__UART4_DTE_TX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x0450, 0x01F0, 2 | IOMUX_CONFIG_SION, 0x05B4, 3, 0), + MX8MP_PAD_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x0450, 0x01F0, 3, 0x053C, 1, 0), + MX8MP_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x0450, 0x01F0, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SCLK__TPSMP_HDATA12 = IOMUX_PAD(0x0450, 0x01F0, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0454, 0x01F4, 0, 0x0570, 1, 0), + MX8MP_PAD_ECSPI2_MOSI__UART4_DCE_TX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__UART4_DTE_RX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0600, 7, 0), + MX8MP_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0454, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x05B8, 3, 0), + MX8MP_PAD_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x0454, 0x01F4, 3, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0454, 0x01F4, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MOSI__TPSMP_HDATA13 = IOMUX_PAD(0x0454, 0x01F4, 7, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0458, 0x01F8, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__TPSMP_HDATA14 = IOMUX_PAD(0x0458, 0x01F8, 7, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0458, 0x01F8, 0, 0x056C, 1, 0), + MX8MP_PAD_ECSPI2_MISO__UART4_DCE_CTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__UART4_DTE_RTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x05FC, 2, 0), + MX8MP_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0458, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0), + MX8MP_PAD_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x0458, 0x01F8, 3, 0x052C, 1, 0), + MX8MP_PAD_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0), + + MX8MP_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x045C, 0x01FC, 0, 0x0574, 1, 0), + MX8MP_PAD_ECSPI2_SS0__UART4_DCE_RTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x05FC, 3, 0), + MX8MP_PAD_ECSPI2_SS0__UART4_DTE_CTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x045C, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05C0, 4, 0), + MX8MP_PAD_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x045C, 0x01FC, 5, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__TPSMP_HDATA15 = IOMUX_PAD(0x045C, 0x01FC, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0460, 0x0200, 0 | IOMUX_CONFIG_SION, 0x05A4, 2, 0), + MX8MP_PAD_I2C1_SCL__ENET_QOS_MDC = IOMUX_PAD(0x0460, 0x0200, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SCL__ECSPI1_SCLK = IOMUX_PAD(0x0460, 0x0200, 3, 0x0558, 1, 0), + MX8MP_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x0460, 0x0200, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SCL__TPSMP_HDATA16 = IOMUX_PAD(0x0460, 0x0200, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0464, 0x0204, 0 | IOMUX_CONFIG_SION, 0x05A8, 2, 0), + MX8MP_PAD_I2C1_SDA__ENET_QOS_MDIO = IOMUX_PAD(0x0464, 0x0204, 1, 0x0590, 2, 0), + MX8MP_PAD_I2C1_SDA__ECSPI1_MOSI = IOMUX_PAD(0x0464, 0x0204, 3, 0x0560, 1, 0), + MX8MP_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0464, 0x0204, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C1_SDA__TPSMP_HDATA17 = IOMUX_PAD(0x0464, 0x0204, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0468, 0x0208, 0 | IOMUX_CONFIG_SION, 0x05AC, 2, 0), + MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_IN = IOMUX_PAD(0x0468, 0x0208, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__USDHC3_CD_B = IOMUX_PAD(0x0468, 0x0208, 2, 0x0608, 3, 0), + MX8MP_PAD_I2C2_SCL__ECSPI1_MISO = IOMUX_PAD(0x0468, 0x0208, 3, 0x055C, 1, 0), + MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN = IOMUX_PAD(0x0468, 0x0208, 4, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0468, 0x0208, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SCL__TPSMP_HDATA18 = IOMUX_PAD(0x0468, 0x0208, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x046C, 0x020C, 0 | IOMUX_CONFIG_SION, 0x05B0, 2, 0), + MX8MP_PAD_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT = IOMUX_PAD(0x046C, 0x020C, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SDA__USDHC3_WP = IOMUX_PAD(0x046C, 0x020C, 2, 0x0634, 3, 0), + MX8MP_PAD_I2C2_SDA__ECSPI1_SS0 = IOMUX_PAD(0x046C, 0x020C, 3, 0x0564, 1, 0), + MX8MP_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x046C, 0x020C, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C2_SDA__TPSMP_HDATA19 = IOMUX_PAD(0x046C, 0x020C, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x0470, 0x0210, 0 | IOMUX_CONFIG_SION, 0x05B4, 4, 0), + MX8MP_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x0470, 0x0210, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x0470, 0x0210, 2, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x0210, 3, 0x0568, 2, 0), + MX8MP_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x0470, 0x0210, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SCL__TPSMP_HDATA20 = IOMUX_PAD(0x0470, 0x0210, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0474, 0x0214, 0 | IOMUX_CONFIG_SION, 0x05B8, 4, 0), + MX8MP_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0474, 0x0214, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0474, 0x0214, 2, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__ECSPI2_MOSI = IOMUX_PAD(0x0474, 0x0214, 3, 0x0570, 2, 0), + MX8MP_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0474, 0x0214, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C3_SDA__TPSMP_HDATA21 = IOMUX_PAD(0x0474, 0x0214, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0478, 0x0218, 0 | IOMUX_CONFIG_SION, 0x05BC, 5, 0), + MX8MP_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0478, 0x0218, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0), + MX8MP_PAD_I2C4_SCL__ECSPI2_MISO = IOMUX_PAD(0x0478, 0x0218, 3, 0x056C, 2, 0), + MX8MP_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0478, 0x0218, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SCL__TPSMP_HDATA22 = IOMUX_PAD(0x0478, 0x0218, 7, 0x0000, 0, 0), + + MX8MP_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x047C, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05C0, 5, 0), + MX8MP_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x047C, 0x021C, 1, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SDA__ECSPI2_SS0 = IOMUX_PAD(0x047C, 0x021C, 3, 0x0574, 2, 0), + MX8MP_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x047C, 0x021C, 5, 0x0000, 0, 0), + MX8MP_PAD_I2C4_SDA__TPSMP_HDATA23 = IOMUX_PAD(0x047C, 0x021C, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x0480, 0x0220, 0, 0x05E8, 4, 0), + + MX8MP_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x0480, 0x0220, 0, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x0480, 0x0220, 1, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x0480, 0x0220, 5, 0x0000, 0, 0), + MX8MP_PAD_UART1_RXD__TPSMP_HDATA24 = IOMUX_PAD(0x0480, 0x0220, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0484, 0x0224, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0484, 0x0224, 0, 0x05E8, 5, 0), + MX8MP_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x0484, 0x0224, 1, 0x0000, 0, 0), + MX8MP_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x0484, 0x0224, 5, 0x0000, 0, 0), + MX8MP_PAD_UART1_TXD__TPSMP_HDATA25 = IOMUX_PAD(0x0484, 0x0224, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART2_RXD__UART2_DCE_RX = IOMUX_PAD(0x0488, 0x0228, 0, 0x05F0, 6, 0), + + MX8MP_PAD_UART2_RXD__UART2_DTE_TX = IOMUX_PAD(0x0488, 0x0228, 0, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x0488, 0x0228, 1, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__GPT1_COMPARE3 = IOMUX_PAD(0x0488, 0x0228, 3, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x0488, 0x0228, 5, 0x0000, 0, 0), + MX8MP_PAD_UART2_RXD__TPSMP_HDATA26 = IOMUX_PAD(0x0488, 0x0228, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART2_TXD__UART2_DCE_TX = IOMUX_PAD(0x048C, 0x022C, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART2_TXD__UART2_DTE_RX = IOMUX_PAD(0x048C, 0x022C, 0, 0x05F0, 7, 0), + MX8MP_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x048C, 0x022C, 1, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__GPT1_COMPARE2 = IOMUX_PAD(0x048C, 0x022C, 3, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x048C, 0x022C, 5, 0x0000, 0, 0), + MX8MP_PAD_UART2_TXD__TPSMP_HDATA27 = IOMUX_PAD(0x048C, 0x022C, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART3_RXD__UART3_DCE_RX = IOMUX_PAD(0x0490, 0x0230, 0, 0x05F8, 6, 0), + + MX8MP_PAD_UART3_RXD__UART3_DTE_TX = IOMUX_PAD(0x0490, 0x0230, 0, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__UART1_DCE_CTS = IOMUX_PAD(0x0490, 0x0230, 1, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__UART1_DTE_RTS = IOMUX_PAD(0x0490, 0x0230, 1, 0x05E4, 4, 0), + MX8MP_PAD_UART3_RXD__USDHC3_RESET_B = IOMUX_PAD(0x0490, 0x0230, 2, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__GPT1_CAPTURE2 = IOMUX_PAD(0x0490, 0x0230, 3, 0x0598, 1, 0), + MX8MP_PAD_UART3_RXD__CAN2_TX = IOMUX_PAD(0x0490, 0x0230, 4, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x0490, 0x0230, 5, 0x0000, 0, 0), + MX8MP_PAD_UART3_RXD__TPSMP_HDATA28 = IOMUX_PAD(0x0490, 0x0230, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART3_TXD__UART3_DCE_TX = IOMUX_PAD(0x0494, 0x0234, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART3_TXD__UART3_DTE_RX = IOMUX_PAD(0x0494, 0x0234, 0, 0x05F8, 7, 0), + MX8MP_PAD_UART3_TXD__UART1_DCE_RTS = IOMUX_PAD(0x0494, 0x0234, 1, 0x05E4, 5, 0), + MX8MP_PAD_UART3_TXD__UART1_DTE_CTS = IOMUX_PAD(0x0494, 0x0234, 1, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__USDHC3_VSELECT = IOMUX_PAD(0x0494, 0x0234, 2, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__GPT1_CLK = IOMUX_PAD(0x0494, 0x0234, 3, 0x059C, 1, 0), + MX8MP_PAD_UART3_TXD__CAN2_RX = IOMUX_PAD(0x0494, 0x0234, 4, 0x0550, 2, 0), + MX8MP_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x0494, 0x0234, 5, 0x0000, 0, 0), + MX8MP_PAD_UART3_TXD__TPSMP_HDATA29 = IOMUX_PAD(0x0494, 0x0234, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART4_RXD__UART4_DCE_RX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0600, 8, 0), + + MX8MP_PAD_UART4_RXD__UART4_DTE_TX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__UART2_DCE_CTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__UART2_DTE_RTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x05EC, 4, 0), + MX8MP_PAD_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0), + MX8MP_PAD_UART4_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x0498, 0x0238, 3, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__I2C6_SCL = IOMUX_PAD(0x0498, 0x0238, 4 | IOMUX_CONFIG_SION, 0x05CC, 2, 0), + MX8MP_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x0498, 0x0238, 5, 0x0000, 0, 0), + MX8MP_PAD_UART4_RXD__TPSMP_HDATA30 = IOMUX_PAD(0x0498, 0x0238, 7, 0x0000, 0, 0), + + MX8MP_PAD_UART4_TXD__UART4_DCE_TX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0000, 0, 0), + + MX8MP_PAD_UART4_TXD__UART4_DTE_RX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0600, 9, 0), + MX8MP_PAD_UART4_TXD__UART2_DCE_RTS = IOMUX_PAD(0x049C, 0x023C, 1, 0x05EC, 5, 0), + MX8MP_PAD_UART4_TXD__UART2_DTE_CTS = IOMUX_PAD(0x049C, 0x023C, 1, 0x0000, 0, 0), + MX8MP_PAD_UART4_TXD__GPT1_CAPTURE1 = IOMUX_PAD(0x049C, 0x023C, 3, 0x0594, 1, 0), + MX8MP_PAD_UART4_TXD__I2C6_SDA = IOMUX_PAD(0x049C, 0x023C, 4 | IOMUX_CONFIG_SION, 0x05D0, 2, 0), + MX8MP_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x049C, 0x023C, 5, 0x0000, 0, 0), + MX8MP_PAD_UART4_TXD__TPSMP_HDATA31 = IOMUX_PAD(0x049C, 0x023C, 7, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_EARC_SCL = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__I2C5_SCL = IOMUX_PAD(0x04A0, 0x0240, 3 | IOMUX_CONFIG_SION, 0x05C4, 3, 0), + MX8MP_PAD_HDMI_DDC_SCL__CAN1_TX = IOMUX_PAD(0x04A0, 0x0240, 4, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__GPIO3_IO26 = IOMUX_PAD(0x04A0, 0x0240, 5, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__AUDIOMIX_test_out00 = IOMUX_PAD(0x04A0, 0x0240, 6, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_EARC_SDA = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__I2C5_SDA = IOMUX_PAD(0x04A4, 0x0244, 3 | IOMUX_CONFIG_SION, 0x05C8, 3, 0), + MX8MP_PAD_HDMI_DDC_SDA__CAN1_RX = IOMUX_PAD(0x04A4, 0x0244, 4, 0x054C, 3, 0), + MX8MP_PAD_HDMI_DDC_SDA__GPIO3_IO27 = IOMUX_PAD(0x04A4, 0x0244, 5, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__AUDIOMIX_test_out01 = IOMUX_PAD(0x04A4, 0x0244, 6, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_CEC__HDMIMIX_EARC_CEC = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__I2C6_SCL = IOMUX_PAD(0x04A8, 0x0248, 3 | IOMUX_CONFIG_SION, 0x05CC, 3, 0), + MX8MP_PAD_HDMI_CEC__CAN2_TX = IOMUX_PAD(0x04A8, 0x0248, 4, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__GPIO3_IO28 = IOMUX_PAD(0x04A8, 0x0248, 5, 0x0000, 0, 0), + + MX8MP_PAD_HDMI_HPD__HDMIMIX_EARC_DC_HPD = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__I2C6_SDA = IOMUX_PAD(0x04AC, 0x024C, 3 | IOMUX_CONFIG_SION, 0x05D0, 3, 0), + MX8MP_PAD_HDMI_HPD__CAN2_RX = IOMUX_PAD(0x04AC, 0x024C, 4, 0x0550, 3, 0), + MX8MP_PAD_HDMI_HPD__GPIO3_IO29 = IOMUX_PAD(0x04AC, 0x024C, 5, 0x0000, 0, 0), +}; + +#define MX8MP_PAD_CTL_DSE1 (0 << 1) +#define MX8MP_PAD_CTL_DSE2 (1 << 1) +#define MX8MP_PAD_CTL_DSE4 (2 << 1) +#define MX8MP_PAD_CTL_DSE6 (3 << 1) +#define MX8MP_PAD_CTL_FSEL BIT(4) +#define MX8MP_PAD_CTL_ODE BIT(5) +#define MX8MP_PAD_CTL_PUE BIT(6) +#define MX8MP_PAD_CTL_HYS BIT(7) +#define MX8MP_PAD_CTL_PE BIT(8) + +static inline void imx8mp_setup_pad(iomux_v3_cfg_t pad) +{ + void __iomem *iomux = IOMEM(MX8MP_IOMUXC_BASE_ADDR); + + imx8m_setup_pad(iomux, pad); +} + +#define MX8MP_IOMUXC_GPR1 0x4 +#define MX8MP_IOMUXC_GPR1_ENET1_RGMII_EN BIT(22) + +#endif /* __ASM_ARCH_IMX8MP_PINS_H__ */ diff --git a/arch/arm/mach-imx/include/mach/xload.h b/arch/arm/mach-imx/include/mach/xload.h index dca05aa5d4..05022e9d09 100644 --- a/arch/arm/mach-imx/include/mach/xload.h +++ b/arch/arm/mach-imx/include/mach/xload.h @@ -6,6 +6,7 @@ int imx6_spi_load_image(int instance, unsigned int flash_offset, void *buf, int int imx6_spi_start_image(int instance); int imx6_esdhc_start_image(int instance); int imx8m_esdhc_load_image(int instance, bool start); +int imx8mp_esdhc_load_image(int instance, bool start); int imx_image_size(void); int piggydata_size(void); diff --git a/common/Kconfig b/common/Kconfig index f150092af6..f260291d15 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1184,6 +1184,13 @@ config DEBUG_IMX7D_UART Say Y here if you want barebox low-level debugging support on i.MX7D. +config DEBUG_IMX8MP_UART + bool "i.MX8MP Debug UART" + depends on ARCH_IMX8MP + help + Say Y here if you want barebox low-level debugging support + on i.MX8MP. + config DEBUG_IMX8MQ_UART bool "i.MX8MQ Debug UART" depends on ARCH_IMX8MQ @@ -1281,6 +1288,7 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ DEBUG_IMX7D_UART || \ + DEBUG_IMX8MP_UART || \ DEBUG_IMX8MQ_UART || \ DEBUG_VF610_UART default 1 diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index b1ce9d3d3e..bb6635d5e4 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -28,6 +28,8 @@ obj-$(CONFIG_ARCH_IMX6SL) += clk-imx6sl.o obj-$(CONFIG_ARCH_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_ARCH_IMX7) += clk-imx7.o pbl-$(CONFIG_ARCH_IMX8MM) += clk-pll14xx.o +pbl-$(CONFIG_ARCH_IMX8MP) += clk-pll14xx.o obj-$(CONFIG_ARCH_IMX8MM) += clk-imx8mm.o +obj-$(CONFIG_ARCH_IMX8MP) += clk-imx8mp.o obj-$(CONFIG_ARCH_IMX8MQ) += clk-imx8mq.o obj-$(CONFIG_ARCH_VF610) += clk-vf610.o diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c new file mode 100644 index 0000000000..8286e47960 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mp.c @@ -0,0 +1,720 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2019 NXP. + */ + +#include <dt-bindings/clock/imx8mp-clock.h> +#include <io.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/types.h> +#include <of_address.h> + +#include "clk.h" + +static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; +static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; +static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; +static const char *video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; +static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; +static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; +static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; +static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; + +static const char *imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", + "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", + "audio_pll1_out", "sys_pll3_out", }; + +static const char *imx8mp_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", }; + +static const char *imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", + "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", + "video_pll1_out", "sys_pll3_out", }; + +static const char *imx8mp_ml_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_gpu3d_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_gpu3d_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_audio_axi_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_400m", "audio_pll2_out", + "clk_ext1", "sys_pll2_500m", }; + +static const char *imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "sys_pll1_100m",}; + +static const char *imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", + "video_pll1_out", "sys_pll3_out", }; + +static const char *imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll1_out", }; + +static const char *imx8mp_vpu_bus_sels[] = {"osc_24m", "sys_pll1_800m", "vpu_pll_out", + "audio_pll2_out", "sys_pll3_out", "sys_pll2_1000m", + "sys_pll2_200m", "sys_pll1_100m", }; + +static const char *imx8mp_media_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", + "clk_ext1", "sys_pll2_500m", }; + +static const char *imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", + "clk_ext1", "sys_pll1_133m", }; + +static const char *imx8mp_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_ml_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_ml_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", + "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", + "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mp_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", + "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", + "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll1_out", "sys_pll1_266m", }; + +static const char *imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char *imx8mp_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char *imx8mp_can1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_pcie_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "sys_pll1_400m", }; + +static const char *imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", + "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_160m", "sys_pll1_200m", }; + +static const char *imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext1", "clk_ext2", }; + +static const char *imx8mp_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext2", "clk_ext3", }; + +static const char *imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char *imx8mp_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext1", "clk_ext2", }; + +static const char *imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext2", "clk_ext3", }; + +static const char *imx8mp_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char *imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; + +static const char *imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; + +static const char *imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; + +static const char *imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; + +static const char *imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", + "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char *imx8mp_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", + "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", + "sys_pll2_250m", "video_pll1_out", }; + +static const char *imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", + "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", + "sys_pll3_out", "sys_pll1_100m", }; + +static const char *imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char *imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char *imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char *imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll1_800m", + "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; + +static const char *imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; + +static const char *imx8mp_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1" }; + +static const char *imx8mp_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext2" }; + +static const char *imx8mp_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext3" }; + +static const char *imx8mp_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1" }; + +static const char *imx8mp_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext2" }; + +static const char *imx8mp_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext3" }; + +static const char *imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", + "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", + "sys_pll1_80m", "sys_pll2_166m" }; + +static const char *imx8mp_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", + "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m", + "sys_pll2_500m", "sys_pll1_100m" }; + +static const char *imx8mp_ipp_do_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_133m", + "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", + "vpu_pll_out", "sys_pll1_80m" }; + +static const char *imx8mp_ipp_do_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", + "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out", + "video_pll1_out", "osc_32k" }; + +static const char *imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll2_out", "video_pll1_out", }; + +static const char *imx8mp_hdmi_24m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char *imx8mp_hdmi_ref_266m_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", + "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m", + "audio_pll1_out", "video_pll1_out", }; + +static const char *imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char *imx8mp_media_cam1_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "audio_pll2_out", + "video_pll1_out", }; + +static const char *imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", + "sys_pll1_800m", "sys_pll2_1000m", + "clk_ext2", "audio_pll2_out", + "video_pll1_out", }; + +static const char *imx8mp_media_disp1_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", + "audio_pll1_out", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; + +static const char *imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "audio_pll2_out", + "video_pll1_out", }; + +static const char *imx8mp_media_mipi_phy2_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", + "sys_pll1_800m", "sys_pll2_1000m", + "clk_ext2", "audio_pll2_out", + "video_pll1_out", }; + +static const char *imx8mp_media_mipi_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext3", + "audio_pll2_out", }; + +static const char *imx8mp_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", + "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", + "sys_pll2_333m", "sys_pll3_out", }; + +static const char *imx8mp_pcie2_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "sys_pll1_400m", }; + +static const char *imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", + "sys_pll3_out", "sys_pll2_100m", + "sys_pll1_80m", "sys_pll1_160m", + "sys_pll1_200m", }; + +static const char *imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mp_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_vpu_vc8000e_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "audio_pll2_out", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char *imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char *imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; + +static struct clk_onecell_data clk_data; +static struct clk *clks[IMX8MP_CLK_END]; + +static int imx8mp_clocks_init(struct device_node *ccm_np) +{ + struct device_node *anatop_np; + void __iomem *ccm, *ana; + int ret; + + anatop_np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop"); + ana = of_iomap(anatop_np, 0); + if (WARN_ON(!ana)) + return -ENOMEM; + + ccm = of_iomap(ccm_np, 0); + if (WARN_ON(!ccm)) + return -ENOMEM; + + clks[IMX8MP_CLK_DUMMY] = clk_fixed("dummy", 0); + clks[IMX8MP_CLK_24M] = of_clk_get_by_name(ccm_np, "osc_24m"); + clks[IMX8MP_CLK_32K] = of_clk_get_by_name(ccm_np, "osc_32k"); + clks[IMX8MP_CLK_EXT1] = of_clk_get_by_name(ccm_np, "clk_ext1"); + clks[IMX8MP_CLK_EXT2] = of_clk_get_by_name(ccm_np, "clk_ext2"); + clks[IMX8MP_CLK_EXT3] = of_clk_get_by_name(ccm_np, "clk_ext3"); + clks[IMX8MP_CLK_EXT4] = of_clk_get_by_name(ccm_np, "clk_ext4"); + + clks[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", ana + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", ana + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", ana + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", ana + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", ana + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", ana + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", ana + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", ana + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", ana + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + clks[IMX8MP_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", ana + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + clks[IMX8MP_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", ana, &imx_1443x_pll); + clks[IMX8MP_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", ana + 0x14, &imx_1443x_pll); + clks[IMX8MP_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", ana + 0x28, &imx_1443x_pll); + clks[IMX8MP_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", ana + 0x64, &imx_1416x_pll); + clks[IMX8MP_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", ana + 0x74, &imx_1416x_pll); + clks[IMX8MP_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", ana + 0x84, &imx_1416x_pll); + clks[IMX8MP_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", ana + 0x94, &imx_1416x_pll); + clks[IMX8MP_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", ana + 0x104, &imx_1416x_pll); + clks[IMX8MP_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", ana + 0x114, &imx_1416x_pll); + + clks[IMX8MP_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", ana, 4, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", ana + 0x14, 4, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", ana + 0x28, 4, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", ana + 0x50, 4, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", ana + 0x64, 4, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", ana + 0x74, 4, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", ana + 0x84, 4, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", ana + 0x94, 4, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", ana + 0x104, 4, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX8MP_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", ana + 0x114, 4, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); + + clks[IMX8MP_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", ana, 13); + clks[IMX8MP_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", ana + 0x14, 13); + clks[IMX8MP_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", ana + 0x28, 13); + clks[IMX8MP_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", ana + 0x50, 13); + clks[IMX8MP_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", ana + 0x64, 11); + clks[IMX8MP_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", ana + 0x74, 11); + clks[IMX8MP_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", ana + 0x84, 11); + clks[IMX8MP_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", ana + 0x94, 11); + clks[IMX8MP_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", ana + 0x104, 11); + clks[IMX8MP_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", ana + 0x114, 11); + + clks[IMX8MP_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + clks[IMX8MP_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + clks[IMX8MP_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + clks[IMX8MP_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + clks[IMX8MP_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + clks[IMX8MP_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + clks[IMX8MP_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + clks[IMX8MP_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + clks[IMX8MP_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + clks[IMX8MP_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + clks[IMX8MP_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + clks[IMX8MP_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + clks[IMX8MP_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + clks[IMX8MP_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + clks[IMX8MP_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + clks[IMX8MP_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + clks[IMX8MP_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + clks[IMX8MP_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + clks[IMX8MP_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", ccm + 0x8000, 24, 3, imx8mp_a53_sels, ARRAY_SIZE(imx8mp_a53_sels)); + clks[IMX8MP_CLK_M7_SRC] = imx_clk_mux2("arm_m7_src", ccm + 0x8080, 24, 3, imx8mp_m7_sels, ARRAY_SIZE(imx8mp_m7_sels)); + clks[IMX8MP_CLK_ML_SRC] = imx_clk_mux2("ml_src", ccm + 0x8100, 24, 3, imx8mp_ml_sels, ARRAY_SIZE(imx8mp_ml_sels)); + clks[IMX8MP_CLK_GPU3D_CORE_SRC] = imx_clk_mux2("gpu3d_core_src", ccm + 0x8180, 24, 3, imx8mp_gpu3d_core_sels, ARRAY_SIZE(imx8mp_gpu3d_core_sels)); + clks[IMX8MP_CLK_GPU3D_SHADER_SRC] = imx_clk_mux2("gpu3d_shader_src", ccm + 0x8200, 24, 3, imx8mp_gpu3d_shader_sels, ARRAY_SIZE(imx8mp_gpu3d_shader_sels)); + clks[IMX8MP_CLK_GPU2D_SRC] = imx_clk_mux2("gpu2d_src", ccm + 0x8280, 24, 3, imx8mp_gpu2d_sels, ARRAY_SIZE(imx8mp_gpu2d_sels)); + clks[IMX8MP_CLK_AUDIO_AXI_SRC] = imx_clk_mux2("audio_axi_src", ccm + 0x8300, 24, 3, imx8mp_audio_axi_sels, ARRAY_SIZE(imx8mp_audio_axi_sels)); + clks[IMX8MP_CLK_HSIO_AXI_SRC] = imx_clk_mux2("hsio_axi_src", ccm + 0x8380, 24, 3, imx8mp_hsio_axi_sels, ARRAY_SIZE(imx8mp_hsio_axi_sels)); + clks[IMX8MP_CLK_MEDIA_ISP_SRC] = imx_clk_mux2("media_isp_src", ccm + 0x8400, 24, 3, imx8mp_media_isp_sels, ARRAY_SIZE(imx8mp_media_isp_sels)); + clks[IMX8MP_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", ccm + 0x8000, 28); + clks[IMX8MP_CLK_M4_CG] = imx_clk_gate3("arm_m7_cg", "arm_m7_src", ccm + 0x8080, 28); + clks[IMX8MP_CLK_ML_CG] = imx_clk_gate3("ml_cg", "ml_src", ccm + 0x8100, 28); + clks[IMX8MP_CLK_GPU3D_CORE_CG] = imx_clk_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm + 0x8180, 28); + clks[IMX8MP_CLK_GPU3D_SHADER_CG] = imx_clk_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm + 0x8200, 28); + clks[IMX8MP_CLK_GPU2D_CG] = imx_clk_gate3("gpu2d_cg", "gpu2d_src", ccm + 0x8280, 28); + clks[IMX8MP_CLK_AUDIO_AXI_CG] = imx_clk_gate3("audio_axi_cg", "audio_axi_src", ccm + 0x8300, 28); + clks[IMX8MP_CLK_HSIO_AXI_CG] = imx_clk_gate3("hsio_axi_cg", "hsio_axi_src", ccm + 0x8380, 28); + clks[IMX8MP_CLK_MEDIA_ISP_CG] = imx_clk_gate3("media_isp_cg", "media_isp_src", ccm + 0x8400, 28); + clks[IMX8MP_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", ccm + 0x8000, 0, 3); + clks[IMX8MP_CLK_M7_DIV] = imx_clk_divider2("arm_m7_div", "arm_m7_cg", ccm + 0x8080, 0, 3); + clks[IMX8MP_CLK_ML_DIV] = imx_clk_divider2("ml_div", "ml_cg", ccm + 0x8100, 0, 3); + clks[IMX8MP_CLK_GPU3D_CORE_DIV] = imx_clk_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm + 0x8180, 0, 3); + clks[IMX8MP_CLK_GPU3D_SHADER_DIV] = imx_clk_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm + 0x8200, 0, 3); + clks[IMX8MP_CLK_GPU2D_DIV] = imx_clk_divider2("gpu2d_div", "gpu2d_cg", ccm + 0x8280, 0, 3); + clks[IMX8MP_CLK_AUDIO_AXI_DIV] = imx_clk_divider2("audio_axi_div", "audio_axi_cg", ccm + 0x8300, 0, 3); + clks[IMX8MP_CLK_HSIO_AXI_DIV] = imx_clk_divider2("hsio_axi_div", "hsio_axi_cg", ccm + 0x8380, 0, 3); + clks[IMX8MP_CLK_MEDIA_ISP_DIV] = imx_clk_divider2("media_isp_div", "media_isp_cg", ccm + 0x8400, 0, 3); + + /* CORE SEL */ + clks[IMX8MP_CLK_A53_CORE] = imx_clk_mux2("arm_a53_core", ccm + 0x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels)); + + clks[IMX8MP_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, ccm + 0x8800); + clks[IMX8MP_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mp_enet_axi_sels, ccm + 0x8880); + clks[IMX8MP_CLK_NAND_USDHC_BUS] = imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm + 0x8900); + clks[IMX8MP_CLK_VPU_BUS] = imx8m_clk_composite("vpu_bus", imx8mp_vpu_bus_sels, ccm + 0x8980); + clks[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_composite("media_axi", imx8mp_media_axi_sels, ccm + 0x8a00); + clks[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_composite("media_apb", imx8mp_media_apb_sels, ccm + 0x8a80); + clks[IMX8MP_CLK_HDMI_APB] = imx8m_clk_composite("hdmi_apb", imx8mp_media_apb_sels, ccm + 0x8b00); + clks[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_composite("hdmi_axi", imx8mp_media_axi_sels, ccm + 0x8b80); + clks[IMX8MP_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mp_gpu_axi_sels, ccm + 0x8c00); + clks[IMX8MP_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mp_gpu_ahb_sels, ccm + 0x8c80); + clks[IMX8MP_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mp_noc_sels, ccm + 0x8d00); + clks[IMX8MP_CLK_NOC_IO] = imx8m_clk_composite_critical("noc_io", imx8mp_noc_io_sels, ccm + 0x8d80); + clks[IMX8MP_CLK_ML_AXI] = imx8m_clk_composite("ml_axi", imx8mp_ml_axi_sels, ccm + 0x8e00); + clks[IMX8MP_CLK_ML_AHB] = imx8m_clk_composite("ml_ahb", imx8mp_ml_ahb_sels, ccm + 0x8e80); + + clks[IMX8MP_CLK_AHB] = imx8m_clk_composite_critical("ahb_root", imx8mp_ahb_sels, ccm + 0x9000); + clks[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mp_audio_ahb_sels, ccm + 0x9100); + clks[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_composite("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm + 0x9200); + + clks[IMX8MP_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb_root", ccm + 0x9080, 0, 1); + clks[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", ccm + 0x9180, 0, 1); + + clks[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, ccm + 0xa000); + clks[IMX8MP_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm + 0xa080); + clks[IMX8MP_CLK_VPU_G1] = imx8m_clk_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm + 0xa100); + clks[IMX8MP_CLK_VPU_G2] = imx8m_clk_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm + 0xa180); + clks[IMX8MP_CLK_CAN1] = imx8m_clk_composite("can1", imx8mp_can1_sels, ccm + 0xa200); + clks[IMX8MP_CLK_CAN2] = imx8m_clk_composite("can2", imx8mp_can2_sels, ccm + 0xa280); + clks[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_composite("memrepair", imx8mp_memrepair_sels, ccm + 0xa300); + clks[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm + 0xa380); + clks[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm + 0xa400); + clks[IMX8MP_CLK_I2C5] = imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, ccm + 0xa480); + clks[IMX8MP_CLK_I2C6] = imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, ccm + 0xa500); + clks[IMX8MP_CLK_SAI1] = imx8m_clk_composite("sai1", imx8mp_sai1_sels, ccm + 0xa580); + clks[IMX8MP_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mp_sai2_sels, ccm + 0xa600); + clks[IMX8MP_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mp_sai3_sels, ccm + 0xa680); + clks[IMX8MP_CLK_SAI4] = imx8m_clk_composite("sai4", imx8mp_sai4_sels, ccm + 0xa700); + clks[IMX8MP_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mp_sai5_sels, ccm + 0xa780); + clks[IMX8MP_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mp_sai6_sels, ccm + 0xa800); + clks[IMX8MP_CLK_ENET_QOS] = imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, ccm + 0xa880); + clks[IMX8MP_CLK_ENET_QOS_TIMER] = imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, ccm + 0xa900); + clks[IMX8MP_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, ccm + 0xa980); + clks[IMX8MP_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, ccm + 0xaa00); + clks[IMX8MP_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, ccm + 0xaa80); + clks[IMX8MP_CLK_NAND] = imx8m_clk_composite("nand", imx8mp_nand_sels, ccm + 0xab00); + clks[IMX8MP_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mp_qspi_sels, ccm + 0xab80); + clks[IMX8MP_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mp_usdhc1_sels, ccm + 0xac00); + clks[IMX8MP_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mp_usdhc2_sels, ccm + 0xac80); + clks[IMX8MP_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mp_i2c1_sels, ccm + 0xad00); + clks[IMX8MP_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mp_i2c2_sels, ccm + 0xad80); + clks[IMX8MP_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mp_i2c3_sels, ccm + 0xae00); + clks[IMX8MP_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mp_i2c4_sels, ccm + 0xae80); + + clks[IMX8MP_CLK_UART1] = imx8m_clk_composite("uart1", imx8mp_uart1_sels, ccm + 0xaf00); + clks[IMX8MP_CLK_UART2] = imx8m_clk_composite("uart2", imx8mp_uart2_sels, ccm + 0xaf80); + clks[IMX8MP_CLK_UART3] = imx8m_clk_composite("uart3", imx8mp_uart3_sels, ccm + 0xb000); + clks[IMX8MP_CLK_UART4] = imx8m_clk_composite("uart4", imx8mp_uart4_sels, ccm + 0xb080); + clks[IMX8MP_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, ccm + 0xb100); + clks[IMX8MP_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, ccm + 0xb180); + clks[IMX8MP_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mp_gic_sels, ccm + 0xb200); + clks[IMX8MP_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, ccm + 0xb280); + clks[IMX8MP_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, ccm + 0xb300); + clks[IMX8MP_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mp_pwm1_sels, ccm + 0xb380); + clks[IMX8MP_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mp_pwm2_sels, ccm + 0xb400); + clks[IMX8MP_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mp_pwm3_sels, ccm + 0xb480); + clks[IMX8MP_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mp_pwm4_sels, ccm + 0xb500); + + clks[IMX8MP_CLK_GPT1] = imx8m_clk_composite("gpt1", imx8mp_gpt1_sels, ccm + 0xb580); + clks[IMX8MP_CLK_GPT2] = imx8m_clk_composite("gpt2", imx8mp_gpt2_sels, ccm + 0xb600); + clks[IMX8MP_CLK_GPT3] = imx8m_clk_composite("gpt3", imx8mp_gpt3_sels, ccm + 0xb680); + clks[IMX8MP_CLK_GPT4] = imx8m_clk_composite("gpt4", imx8mp_gpt4_sels, ccm + 0xb700); + clks[IMX8MP_CLK_GPT5] = imx8m_clk_composite("gpt5", imx8mp_gpt5_sels, ccm + 0xb780); + clks[IMX8MP_CLK_GPT6] = imx8m_clk_composite("gpt6", imx8mp_gpt6_sels, ccm + 0xb800); + clks[IMX8MP_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mp_wdog_sels, ccm + 0xb900); + clks[IMX8MP_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mp_wrclk_sels, ccm + 0xb980); + clks[IMX8MP_CLK_IPP_DO_CLKO1] = imx8m_clk_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, ccm + 0xba00); + clks[IMX8MP_CLK_IPP_DO_CLKO2] = imx8m_clk_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, ccm + 0xba80); + clks[IMX8MP_CLK_HDMI_FDCC_TST] = imx8m_clk_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, ccm + 0xbb00); + clks[IMX8MP_CLK_HDMI_24M] = imx8m_clk_composite("hdmi_24m", imx8mp_hdmi_24m_sels, ccm + 0xbb80); + clks[IMX8MP_CLK_HDMI_REF_266M] = imx8m_clk_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, ccm + 0xbc00); + clks[IMX8MP_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mp_usdhc3_sels, ccm + 0xbc80); + clks[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm + 0xbd00); + clks[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm + 0xbd80); + clks[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm + 0xbe00); + clks[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm + 0xbe80); + clks[IMX8MP_CLK_MEDIA_MIPI_PHY2_REF] = imx8m_clk_composite("media_mipi_phy2_ref", imx8mp_media_mipi_phy2_ref_sels, ccm + 0xbf00); + clks[IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC] = imx8m_clk_composite("media_mipi_csi2_esc", imx8mp_media_mipi_csi2_esc_sels, ccm + 0xbf80); + clks[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm + 0xc000); + clks[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm + 0xc080); + clks[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm + 0xc100); + clks[IMX8MP_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, ccm + 0xc180); + clks[IMX8MP_CLK_PDM] = imx8m_clk_composite("pdm", imx8mp_pdm_sels, ccm + 0xc200); + clks[IMX8MP_CLK_VPU_VC8000E] = imx8m_clk_composite("vpu_vc8000e", imx8mp_vpu_vc8000e_sels, ccm + 0xc280); + clks[IMX8MP_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mp_sai7_sels, ccm + 0xc300); + + clks[IMX8MP_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); + clks[IMX8MP_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", ccm + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels), CLK_IS_CRITICAL); + + clks[IMX8MP_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", ccm + 0x4070, 0); + clks[IMX8MP_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", ccm + 0x4080, 0); + clks[IMX8MP_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", ccm + 0x4090, 0); + clks[IMX8MP_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", ccm + 0x40a0, 0); + clks[IMX8MP_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", ccm + 0x40b0, 0); + clks[IMX8MP_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", ccm + 0x40c0, 0); + clks[IMX8MP_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", ccm + 0x40d0, 0); + clks[IMX8MP_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", ccm + 0x40e0, 0); + clks[IMX8MP_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", ccm + 0x40f0, 0); + clks[IMX8MP_CLK_GPT1_ROOT] = imx_clk_gate4("gpt1_root_clk", "gpt1", ccm + 0x4100, 0); + clks[IMX8MP_CLK_GPT2_ROOT] = imx_clk_gate4("gpt2_root_clk", "gpt2", ccm + 0x4110, 0); + clks[IMX8MP_CLK_GPT3_ROOT] = imx_clk_gate4("gpt3_root_clk", "gpt3", ccm + 0x4120, 0); + clks[IMX8MP_CLK_GPT4_ROOT] = imx_clk_gate4("gpt4_root_clk", "gpt4", ccm + 0x4130, 0); + clks[IMX8MP_CLK_GPT5_ROOT] = imx_clk_gate4("gpt5_root_clk", "gpt5", ccm + 0x4140, 0); + clks[IMX8MP_CLK_GPT6_ROOT] = imx_clk_gate4("gpt6_root_clk", "gpt6", ccm + 0x4150, 0); + clks[IMX8MP_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", ccm + 0x4170, 0); + clks[IMX8MP_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", ccm + 0x4180, 0); + clks[IMX8MP_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", ccm + 0x4190, 0); + clks[IMX8MP_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", ccm + 0x41a0, 0); + clks[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", ccm + 0x4220, 0); + clks[IMX8MP_CLK_PCIE_ROOT] = imx_clk_gate4("pcie_root_clk", "pcie_aux", ccm + 0x4250, 0); + clks[IMX8MP_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", ccm + 0x4280, 0); + clks[IMX8MP_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", ccm + 0x4290, 0); + clks[IMX8MP_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", ccm + 0x42a0, 0); + clks[IMX8MP_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", ccm + 0x42b0, 0); + clks[IMX8MP_CLK_QOS_ROOT] = imx_clk_gate4("qos_root_clk", "ipg_root", ccm + 0x42c0, 0); + clks[IMX8MP_CLK_QOS_ENET_ROOT] = imx_clk_gate4("qos_enet_root_clk", "ipg_root", ccm + 0x42e0, 0); + clks[IMX8MP_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", ccm + 0x42f0, 0); + clks[IMX8MP_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", ccm + 0x4300, 0); + clks[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", ccm + 0x4300, 0); + clks[IMX8MP_CLK_I2C5_ROOT] = imx_clk_gate2("i2c5_root_clk", "i2c5", ccm + 0x4330, 0); + clks[IMX8MP_CLK_I2C6_ROOT] = imx_clk_gate2("i2c6_root_clk", "i2c6", ccm + 0x4340, 0); + clks[IMX8MP_CLK_CAN1_ROOT] = imx_clk_gate2("can1_root_clk", "can1", ccm + 0x4350, 0); + clks[IMX8MP_CLK_CAN2_ROOT] = imx_clk_gate2("can2_root_clk", "can2", ccm + 0x4360, 0); + clks[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_root_clk", "ipg_root", ccm + 0x43a0, 0); + clks[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm + 0x43b0, 0); + clks[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_gate4("sim_enet_root_clk", "enet_axi", ccm + 0x4400, 0); + clks[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_gate4("gpu2d_root_clk", "gpu2d_div", ccm + 0x4450, 0); + clks[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm + 0x4460, 0); + clks[IMX8MP_CLK_SNVS_ROOT] = imx_clk_gate4("snvs_root_clk", "ipg_root", ccm + 0x4470, 0); + clks[IMX8MP_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", ccm + 0x4490, 0); + clks[IMX8MP_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", ccm + 0x44a0, 0); + clks[IMX8MP_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", ccm + 0x44b0, 0); + clks[IMX8MP_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", ccm + 0x44c0, 0); + clks[IMX8MP_CLK_USB_ROOT] = imx_clk_gate4("usb_root_clk", "osc_32k", ccm + 0x44d0, 0); + clks[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", ccm + 0x44f0, 0); + clks[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", ccm + 0x4510, 0); + clks[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", ccm + 0x4520, 0); + clks[IMX8MP_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", ccm + 0x4530, 0); + clks[IMX8MP_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", ccm + 0x4540, 0); + clks[IMX8MP_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", ccm + 0x4550, 0); + clks[IMX8MP_CLK_VPU_G1_ROOT] = imx_clk_gate4("vpu_g1_root_clk", "vpu_g1", ccm + 0x4560, 0); + clks[IMX8MP_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", ccm + 0x4570, 0); + clks[IMX8MP_CLK_VPU_VC8KE_ROOT] = imx_clk_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm + 0x4590, 0); + clks[IMX8MP_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2", ccm + 0x45a0, 0); + clks[IMX8MP_CLK_NPU_ROOT] = imx_clk_gate4("npu_root_clk", "ml_div", ccm + 0x45b0, 0); + clks[IMX8MP_CLK_HSIO_ROOT] = imx_clk_gate4("hsio_root_clk", "ipg_root", ccm + 0x45c0, 0); + clks[IMX8MP_CLK_MEDIA_APB_ROOT] = imx_clk_gate2_shared2("media_apb_root_clk", "media_apb", ccm + 0x45d0, 0); + clks[IMX8MP_CLK_MEDIA_AXI_ROOT] = imx_clk_gate2_shared2("media_axi_root_clk", "media_axi", ccm + 0x45d0, 0); + clks[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] = imx_clk_gate2_shared2("media_cam1_pix_root_clk", "media_cam1_pix", ccm + 0x45d0, 0); + clks[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] = imx_clk_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm + 0x45d0, 0); + clks[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] = imx_clk_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm + 0x45d0, 0); + clks[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] = imx_clk_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm + 0x45d0, 0); + clks[IMX8MP_CLK_MEDIA_ISP_ROOT] = imx_clk_gate2_shared2("media_isp_root_clk", "media_isp_div", ccm + 0x45d0, 0); + + clks[IMX8MP_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", ccm + 0x45e0, 0); + clks[IMX8MP_CLK_HDMI_ROOT] = imx_clk_gate4("hdmi_root_clk", "hdmi_axi", ccm + 0x45f0, 0); + clks[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_gate4("tsensor_root_clk", "ipg_root", ccm + 0x4620, 0); + clks[IMX8MP_CLK_VPU_ROOT] = imx_clk_gate4("vpu_root_clk", "vpu_bus", ccm + 0x4630, 0); + clks[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_gate4("audio_root_clk", "ipg_root", ccm + 0x4650, 0); + + clks[IMX8MP_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div", + clks[IMX8MP_CLK_A53_CORE], + clks[IMX8MP_CLK_A53_CORE], + clks[IMX8MP_ARM_PLL_OUT], + clks[IMX8MP_CLK_A53_DIV]); + + imx_check_clocks(clks, ARRAY_SIZE(clks)); + + clk_enable(clks[IMX8MP_SYS_PLL3_OUT]); + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + + ret = of_clk_add_provider(ccm_np, of_clk_src_onecell_get, &clk_data); + if (ret < 0) + pr_err("failed to register clks for i.MX8MM\n"); + + return ret; +} +CLK_OF_DECLARE(imx8mp, "fsl,imx8mp-ccm", imx8mp_clocks_init); diff --git a/drivers/ddr/imx8m/Kconfig b/drivers/ddr/imx8m/Kconfig index e8bce8c49d..7673ab5b4c 100644 --- a/drivers/ddr/imx8m/Kconfig +++ b/drivers/ddr/imx8m/Kconfig @@ -1,5 +1,5 @@ menu "i.MX8M DDR controllers" - depends on ARCH_IMX8MQ || ARCH_IMX8MM + depends on ARCH_IMX8MQ || ARCH_IMX8MM || ARCH_IMX8MP config IMX8M_DRAM bool "imx8m dram controller support" diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c index caaf1ac9b5..5c382bbcc2 100644 --- a/drivers/mci/imx-esdhc-pbl.c +++ b/drivers/mci/imx-esdhc-pbl.c @@ -77,7 +77,7 @@ static int esdhc_read_blocks(struct fsl_esdhc_host *host, void *dst, size_t len) #ifdef CONFIG_ARCH_IMX static int esdhc_search_header(struct fsl_esdhc_host *host, struct imx_flash_header_v2 **header_pointer, - void *buffer, u32 *offset) + void *buffer, u32 *offset, u32 ivt_offset) { int ret; int i, header_count = 1; @@ -86,11 +86,11 @@ static int esdhc_search_header(struct fsl_esdhc_host *host, for (i = 0; i < header_count; i++) { ret = esdhc_read_blocks(host, buf, - *offset + SZ_1K + SECTOR_SIZE); + *offset + ivt_offset + SECTOR_SIZE); if (ret) return ret; - hdr = buf + *offset + SZ_1K; + hdr = buf + *offset + ivt_offset; if (!is_imx_flash_header_v2(hdr)) { pr_debug("IVT header not found on SD card. " @@ -123,7 +123,7 @@ static int esdhc_search_header(struct fsl_esdhc_host *host, static int esdhc_load_image(struct fsl_esdhc_host *host, ptrdiff_t address, - ptrdiff_t entry, u32 offset, bool start) + ptrdiff_t entry, u32 offset, u32 ivt_offset, bool start) { void *buf = (void *)address; @@ -135,7 +135,7 @@ esdhc_load_image(struct fsl_esdhc_host *host, ptrdiff_t address, len = imx_image_size(); len = ALIGN(len, SECTOR_SIZE); - ret = esdhc_search_header(host, &hdr, buf, &offset); + ret = esdhc_search_header(host, &hdr, buf, &offset, ivt_offset); if (ret) return ret; @@ -262,7 +262,7 @@ int imx6_esdhc_start_image(int instance) imx_esdhc_init(&host, &data); - return esdhc_load_image(&host, 0x10000000, 0x10000000, 0, true); + return esdhc_load_image(&host, 0x10000000, 0x10000000, 0, SZ_1K, true); } /** @@ -289,7 +289,35 @@ int imx8m_esdhc_load_image(int instance, bool start) return ret; return esdhc_load_image(&host, MX8M_DDR_CSD1_BASE_ADDR, - MX8MQ_ATF_BL33_BASE_ADDR, SZ_32K, start); + MX8MQ_ATF_BL33_BASE_ADDR, SZ_32K, SZ_1K, + start); +} + +/** + * imx8mp_esdhc_load_image - Load and optionally start an image from USDHC controller + * @instance: The USDHC controller instance (0..2) + * @start: Whether to directly start the loaded image + * + * This uses esdhc_start_image() to load an image from SD/MMC. It is + * assumed that the image is the currently running barebox image (This + * information is used to calculate the length of the image). The + * image is started afterwards. + * + * Return: If successful, this function does not return (if directly started) + * or 0. A negative error code is returned when this function fails. + */ +int imx8mp_esdhc_load_image(int instance, bool start) +{ + struct esdhc_soc_data data; + struct fsl_esdhc_host host; + int ret; + + ret = imx8m_esdhc_init(&host, &data, instance); + if (ret) + return ret; + + return esdhc_load_image(&host, MX8M_DDR_CSD1_BASE_ADDR, + MX8MQ_ATF_BL33_BASE_ADDR, SZ_32K, 0, start); } #endif diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c index 314a2264f9..4a716e249c 100644 --- a/drivers/mci/imx-esdhc.c +++ b/drivers/mci/imx-esdhc.c @@ -376,6 +376,7 @@ static __maybe_unused struct of_device_id fsl_esdhc_compatible[] = { { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data }, { .compatible = "fsl,imx8mq-usdhc", .data = &usdhc_imx6sx_data }, { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx6sx_data }, + { .compatible = "fsl,imx8mp-usdhc", .data = &usdhc_imx6sx_data }, { .compatible = "fsl,ls1046a-esdhc",.data = &esdhc_ls_data }, { /* sentinel */ } }; diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index 772f930f0d..0c2d600d12 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -739,14 +739,17 @@ static int fec_probe(struct device_d *dev) void *base; int ret; enum fec_type type; + void const *type_v; int phy_reset; u32 msec = 1, phy_post_delay = 0; u32 reg; - ret = dev_get_drvdata(dev, (const void **)&type); + ret = dev_get_drvdata(dev, &type_v); if (ret) return ret; + type = (uintptr_t)(type_v); + fec = xzalloc(sizeof(*fec)); fec->type = type; fec->dev = dev; @@ -923,6 +926,9 @@ static __maybe_unused struct of_device_id imx_fec_dt_ids[] = { .compatible = "fsl,imx6sx-fec", .data = (void *)FEC_TYPE_IMX6, }, { + .compatible = "fsl,imx8mp-fec", + .data = (void *)FEC_TYPE_IMX6, + }, { .compatible = "fsl,mvf600-fec", .data = (void *)FEC_TYPE_IMX6, }, { diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 4ae050128c..695a6c384d 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -34,6 +34,7 @@ #define RTL8211F_INSR 0x1d #define RTL8211F_TX_DELAY BIT(8) +#define RTL8211F_RX_DELAY BIT(3) #define RTL8201F_ISR 0x1e #define RTL8201F_IER 0x13 @@ -84,19 +85,50 @@ static int rtl8211c_config_init(struct phy_device *phydev) static int rtl8211f_config_init(struct phy_device *phydev) { + struct device_d *dev = &phydev->dev; + u16 val_txdly, val_rxdly; int ret; - u16 val = 0; - ret = genphy_config_init(phydev); - if (ret < 0) + switch (phydev->interface) { + case PHY_INTERFACE_MODE_RGMII: + val_txdly = 0; + val_rxdly = 0; + break; + + case PHY_INTERFACE_MODE_RGMII_RXID: + val_txdly = 0; + val_rxdly = RTL8211F_RX_DELAY; + break; + + case PHY_INTERFACE_MODE_RGMII_TXID: + val_txdly = RTL8211F_TX_DELAY; + val_rxdly = 0; + break; + + case PHY_INTERFACE_MODE_RGMII_ID: + val_txdly = RTL8211F_TX_DELAY; + val_rxdly = RTL8211F_RX_DELAY; + break; + + default: /* the rest of the modes imply leaving delay as is. */ + return 0; + } + + ret = phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, + val_txdly); + if (ret < 0) { + dev_err(dev, "Failed to update the TX delay register\n"); return ret; + } - /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */ - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || - phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) - val = RTL8211F_TX_DELAY; + ret = phy_modify_paged(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY, + val_rxdly); + if (ret < 0) { + dev_err(dev, "Failed to update the RX delay register\n"); + return ret; + } - return phy_modify_paged(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY, val); + return 0; } static int rtl8366rb_config_init(struct phy_device *phydev) diff --git a/drivers/nvmem/ocotp.c b/drivers/nvmem/ocotp.c index 34e33dee82..62f510785b 100644 --- a/drivers/nvmem/ocotp.c +++ b/drivers/nvmem/ocotp.c @@ -728,6 +728,14 @@ static struct imx_ocotp_data vf610_ocotp_data = { .format_mac = vf610_ocotp_format_mac, }; +static struct imx_ocotp_data imx8mp_ocotp_data = { + .num_regs = 1024, + .addr_to_offset = imx6sl_addr_to_offset, + .mac_offsets_num = 2, + .mac_offsets = { 0x90, 0x96 }, + .format_mac = imx_ocotp_format_mac, +}; + static struct imx_ocotp_data imx8mq_ocotp_data = { .num_regs = 2048, .addr_to_offset = imx6sl_addr_to_offset, @@ -753,6 +761,9 @@ static __maybe_unused struct of_device_id imx_ocotp_dt_ids[] = { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_ocotp_data, }, { + .compatible = "fsl,imx8mp-ocotp", + .data = &imx8mp_ocotp_data, + }, { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_ocotp_data, }, { diff --git a/drivers/pinctrl/imx-iomux-v3.c b/drivers/pinctrl/imx-iomux-v3.c index a45c242fd1..fd05274512 100644 --- a/drivers/pinctrl/imx-iomux-v3.c +++ b/drivers/pinctrl/imx-iomux-v3.c @@ -251,6 +251,8 @@ static __maybe_unused struct of_device_id imx_iomux_v3_dt_ids[] = { }, { .compatible = "fsl,imx8mm-iomuxc", }, { + .compatible = "fsl,imx8mp-iomuxc", + }, { .compatible = "fsl,imx8mq-iomuxc", }, { /* sentinel */ diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index e5280ac3e9..c0265fc2d7 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -291,6 +291,9 @@ static __maybe_unused struct of_device_id imx_serial_dt_ids[] = { .compatible = "fsl,imx8mm-uart", .data = &imx21_data, }, { + .compatible = "fsl,imx8mp-uart", + .data = &imx21_data, + }, { /* sentinel */ } }; diff --git a/firmware/Kconfig b/firmware/Kconfig index 169c6ee915..97b7b3c2ee 100644 --- a/firmware/Kconfig +++ b/firmware/Kconfig @@ -10,6 +10,9 @@ config FIRMWARE_IMX_LPDDR4_PMU_TRAIN config FIRMWARE_IMX8MM_ATF bool +config FIRMWARE_IMX8MP_ATF + bool + config FIRMWARE_IMX8MQ_ATF bool diff --git a/firmware/Makefile b/firmware/Makefile index 020d48440d..3d4b7fd935 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -10,6 +10,7 @@ firmware-$(CONFIG_FIRMWARE_IMX_LPDDR4_PMU_TRAIN) += \ lpddr4_pmu_train_2d_imem.bin firmware-$(CONFIG_FIRMWARE_IMX8MM_ATF) += imx8mm-bl31.bin +firmware-$(CONFIG_FIRMWARE_IMX8MP_ATF) += imx8mp-bl31.bin firmware-$(CONFIG_FIRMWARE_IMX8MQ_ATF) += imx8mq-bl31.bin firmware-$(CONFIG_DRIVER_NET_FSL_FMAN) += fsl_fman_ucode_ls1046_r1.0_106_4_18.bin diff --git a/images/Makefile.imx b/images/Makefile.imx index 765702f26d..586197906c 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -299,6 +299,34 @@ $(call build_imx_habv4img, CONFIG_MACH_PHYTEC_SOM_IMX6, start_phytec_phycore_imx $(call build_imx_habv4img, CONFIG_MACH_PHYTEC_SOM_IMX6, start_phytec_phycore_imx6dl_som_lc_emmc_1gib, phytec-som-imx6/flash-header-phytec-pcm058dl-1gib, phytec-phycore-imx6dl-som-lc-emmc-1gib) +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6q_prti6q, protonic-imx6/flash-header-prti6q, protonic-prti6q) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6q_prtwd2, protonic-imx6/flash-header-prtwd2, protonic-prtwd2) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6q_vicut1, protonic-imx6/flash-header-vicut1q, protonic-vicut1q) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_alti6p, protonic-imx6/flash-header-alti6p, protonic-alti6p) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_lanmcu, protonic-imx6/flash-header-lanmcu, protonic-lanmcu) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_plybas, protonic-imx6/flash-header-plybas, protonic-plybas) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_plym2m, protonic-imx6/flash-header-plym2m, protonic-plym2m) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_prtmvt, protonic-imx6/flash-header-prtmvt, protonic-prtmvt) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_prtrvt, protonic-imx6/flash-header-prtrvt, protonic-prtrvt) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_prtvt7, protonic-imx6/flash-header-prtvt7, protonic-prtvt7) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_victgo, protonic-imx6/flash-header-victgo, protonic-victgo) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6dl_vicut1, protonic-imx6/flash-header-vicut1, protonic-vicut1) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6qp_prtwd3, protonic-imx6/flash-header-prtwd3, protonic-prtwd3) + +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6qp_vicutp, protonic-imx6/flash-header-vicutp, protonic-vicutp) + $(call build_imx_habv4img, CONFIG_MACH_KONTRON_SAMX6I, start_imx6q_samx6i, kontron-samx6i/flash-header-samx6i-quad, imx6q-samx6i) $(call build_imx_habv4img, CONFIG_MACH_KONTRON_SAMX6I, start_imx6dl_samx6i, kontron-samx6i/flash-header-samx6i-duallite, imx6dl-samx6i) @@ -326,6 +354,8 @@ $(call build_imx_habv4img, CONFIG_MACH_PHYTEC_SOM_IMX6, start_phytec_phycore_imx $(call build_imx_habv4img, CONFIG_MACH_PHYTEC_SOM_IMX6, start_phytec_phycore_imx6ull_som_emmc_512mb, phytec-som-imx6/flash-header-phytec-pcl063-512mb, phytec-phycore-imx6ull-emmc-512mb) +$(call build_imx_habv4img, CONFIG_MACH_PROTONIC_IMX6, start_imx6ul_prti6g, protonic-imx6/flash-header-prti6g, protonic-prti6g) + $(call build_imx_habv4img, CONFIG_MACH_TECHNEXION_PICO_HOBBIT, start_imx6ul_pico_hobbit_256mb, technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-256, imx6ul-pico-hobbit-256mb) $(call build_imx_habv4img, CONFIG_MACH_TECHNEXION_PICO_HOBBIT, start_imx6ul_pico_hobbit_512mb, technexion-pico-hobbit/flash-header-imx6ul-pico-hobbit-512, imx6ul-pico-hobbit-512mb) @@ -370,6 +400,12 @@ CFG_start_nxp_imx8mm_evk.pblb.imximg = $(board)/nxp-imx8mm-evk/flash-header-imx8 FILE_barebox-nxp-imx8mm-evk.img = start_nxp_imx8mm_evk.pblb.pimximg image-$(CONFIG_MACH_NXP_IMX8MM_EVK) += barebox-nxp-imx8mm-evk.img +# ----------------------- i.MX8mp based boards -------------------------- +pblb-$(CONFIG_MACH_NXP_IMX8MP_EVK) += start_nxp_imx8mp_evk +CFG_start_nxp_imx8mp_evk.pblb.imximg = $(board)/nxp-imx8mp-evk/flash-header-imx8mp-evk.imxcfg +FILE_barebox-nxp-imx8mp-evk.img = start_nxp_imx8mp_evk.pblb.pimximg +image-$(CONFIG_MACH_NXP_IMX8MP_EVK) += barebox-nxp-imx8mp-evk.img + # ----------------------- i.MX8mq based boards -------------------------- pblb-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += start_nxp_imx8mq_evk CFG_start_nxp_imx8mq_evk.pblb.imximg = $(board)/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg diff --git a/include/mfd/pca9450.h b/include/mfd/pca9450.h new file mode 100644 index 0000000000..256f661911 --- /dev/null +++ b/include/mfd/pca9450.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef PCA9450_H_ +#define PCA9450_H_ + +enum { + PCA9450_REG_DEV_ID = 0x00, + PCA9450_INT1 = 0x01, + PCA9450_INT1_MSK = 0x02, + PCA9450_STATUS1 = 0x03, + PCA9450_STATUS2 = 0x04, + PCA9450_PWRON_STAT = 0x05, + PCA9450_SW_RST = 0x06, + PCA9450_PWR_CTRL = 0x07, + PCA9450_RESET_CTRL = 0x08, + PCA9450_CONFIG1 = 0x09, + PCA9450_CONFIG2 = 0x0A, + PCA9450_BUCK123_DVS = 0x0C, + PCA9450_BUCK1OUT_LIMIT = 0x0D, + PCA9450_BUCK2OUT_LIMIT = 0x0E, + PCA9450_BUCK3OUT_LIMIT = 0x0F, + PCA9450_BUCK1CTRL = 0x10, + PCA9450_BUCK1OUT_DVS0 = 0x11, + PCA9450_BUCK1OUT_DVS1 = 0x12, + PCA9450_BUCK2CTRL = 0x13, + PCA9450_BUCK2OUT_DVS0 = 0x14, + PCA9450_BUCK2OUT_DVS1 = 0x15, + PCA9450_BUCK3CTRL = 0x16, + PCA9450_BUCK3OUT_DVS0 = 0x17, + PCA9450_BUCK3OUT_DVS1 = 0x18, + PCA9450_BUCK4CTRL = 0x19, + PCA9450_BUCK4OUT = 0x1A, + PCA9450_BUCK5CTRL = 0x1B, + PCA9450_BUCK5OUT = 0x1C, + PCA9450_BUCK6CTRL = 0x1D, + PCA9450_BUCK6OUT = 0x1E, + PCA9450_LDO_AD_CTRL = 0x20, + PCA9450_LDO1CTRL = 0x21, + PCA9450_LDO2CTRL = 0x22, + PCA9450_LDO3CTRL = 0x23, + PCA9450_LDO4CTRL = 0x24, + PCA9450_LDO5CTRL_L = 0x25, + PCA9450_LDO5CTRL_H = 0x26, + PCA9450_LOADSW_CTRL = 0x2A, + PCA9450_VRFLT1_STS = 0x2B, + PCA9450_VRFLT2_STS = 0x2C, + PCA9450_VRFLT1_MASK = 0x2D, + PCA9450_VRFLT2_MASK = 0x2E, + PCA9450_REG_NUM, +}; + +#endif diff --git a/scripts/imx/README b/scripts/imx/README index d573d3a6be..99155af013 100644 --- a/scripts/imx/README +++ b/scripts/imx/README @@ -22,7 +22,7 @@ end up at 0x80001000 from where it is then executed. Example config file, suitable for an Eukra cpuimx35: soc imx35 -dcdofs 0x400 +ivtofs 0x400 loadaddr 0x80000000 wm 32 0x53F80004 0x00821000 wm 32 0x53F80004 0x00821000 diff --git a/scripts/imx/imx-image.c b/scripts/imx/imx-image.c index ec7444a772..de04962b09 100644 --- a/scripts/imx/imx-image.c +++ b/scripts/imx/imx-image.c @@ -238,7 +238,7 @@ static size_t add_header_v1(struct config_data *data, void *buf) { struct imx_flash_header *hdr; int dcdsize = curdcd * sizeof(uint32_t); - int offset = data->image_dcd_offset; + int offset = data->image_ivt_offset; uint32_t loadaddr = data->image_load_addr; uint32_t imagesize = data->load_size; @@ -307,7 +307,7 @@ static size_t add_header_v2(const struct config_data *data, void *buf) { struct imx_flash_header_v2 *hdr; int dcdsize = curdcd * sizeof(uint32_t); - int offset = data->image_dcd_offset; + int offset = data->image_ivt_offset; uint32_t loadaddr = data->image_load_addr; uint32_t imagesize = data->load_size; @@ -329,7 +329,8 @@ static size_t add_header_v2(const struct config_data *data, void *buf) hdr->header.version = IVT_VERSION; hdr->entry = loadaddr + HEADER_LEN; - hdr->dcd_ptr = loadaddr + offset + offsetof(struct imx_flash_header_v2, dcd_header); + if (dcdsize) + hdr->dcd_ptr = loadaddr + offset + offsetof(struct imx_flash_header_v2, dcd_header); if (create_usb_image) { dcd_ptr_content = hdr->dcd_ptr; dcd_ptr_offset = offsetof(struct imx_flash_header_v2, dcd_ptr) + offset; @@ -357,13 +358,14 @@ static size_t add_header_v2(const struct config_data *data, void *buf) hdr->boot_data.size += CSF_LEN; } - hdr->dcd_header.tag = TAG_DCD_HEADER; - hdr->dcd_header.length = htobe16(sizeof(uint32_t) + dcdsize); - hdr->dcd_header.version = DCD_VERSION; - buf += sizeof(*hdr); - memcpy(buf, dcdtable, dcdsize); + if (dcdsize) { + hdr->dcd_header.tag = TAG_DCD_HEADER; + hdr->dcd_header.length = htobe16(sizeof(uint32_t) + dcdsize); + hdr->dcd_header.version = DCD_VERSION; + memcpy(buf, dcdtable, dcdsize); + } return imagesize; } @@ -443,41 +445,42 @@ static int write_mem_v2(uint32_t addr, uint32_t val, int width, int set_bits, in return 0; } -static int xread(int fd, void *buf, int len) +static void xread(int fd, void *buf, int len) { int ret; while (len) { ret = read(fd, buf, len); - if (ret < 0) - return ret; + if (ret < 0) { + fprintf(stderr, "read failed: %s\n", strerror(errno)); + exit(1); + } + if (!ret) - return EOF; + return; buf += ret; len -= ret; } - - return 0; } -static int xwrite(int fd, void *buf, int len) +static void xwrite(int fd, void *buf, int len) { int ret; while (len) { ret = write(fd, buf, len); - if (ret < 0) - return ret; + if (ret < 0) { + fprintf(stderr, "write failed: %s\n", strerror(errno)); + exit(1); + } buf += ret; len -= ret; } - - return 0; } static void write_dcd(const char *outfile) { - int outfd, ret; + int outfd; int dcdsize = curdcd * sizeof(uint32_t); outfd = open(outfile, O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR | S_IWUSR); @@ -487,11 +490,7 @@ static void write_dcd(const char *outfile) exit(1); } - ret = xwrite(outfd, dcdtable, dcdsize); - if (ret < 0) { - perror("write"); - exit(1); - } + xwrite(outfd, dcdtable, dcdsize); } static int check(const struct config_data *data, uint32_t cmd, uint32_t addr, @@ -690,11 +689,7 @@ static int hab_sign(struct config_data *data) csf_space); } - ret = xread(fd, buf, s.st_size); - if (ret < 0) { - fprintf(stderr, "read failed: %s\n", strerror(errno)); - return -errno; - } + xread(fd, buf, s.st_size); /* * For i.MX8M, write into the reserved CSF section @@ -726,11 +721,7 @@ static int hab_sign(struct config_data *data) } } - ret = xwrite(outfd, buf, csf_space); - if (ret < 0) { - fprintf(stderr, "write failed: %s\n", strerror(errno)); - return -errno; - } + xwrite(outfd, buf, csf_space); ret = close(outfd); if (ret) { @@ -790,11 +781,10 @@ int main(int argc, char *argv[]) int outfd; int dcd_only = 0; int now = 0; - int i, header_copies; int add_barebox_header; uint32_t barebox_image_size = 0; struct config_data data = { - .image_dcd_offset = 0xffffffff, + .image_ivt_offset = 0xffffffff, .write_mem = write_mem, .check = check, .nop = nop, @@ -892,11 +882,11 @@ int main(int argc, char *argv[]) create_usb_image = 0; } - if (data.image_dcd_offset == 0xffffffff) { + if (data.image_ivt_offset == 0xffffffff) { if (create_usb_image) - data.image_dcd_offset = 0x0; + data.image_ivt_offset = 0x0; else - data.image_dcd_offset = FLASH_HEADER_OFFSET; + data.image_ivt_offset = FLASH_HEADER_OFFSET; } if (!data.header_version) { @@ -920,14 +910,14 @@ int main(int argc, char *argv[]) case 1: barebox_image_size = add_header_v1(&data, buf); if (data.srkfile) { - ret = add_srk(buf, data.image_dcd_offset, data.image_load_addr, + ret = add_srk(buf, data.image_ivt_offset, data.image_load_addr, data.srkfile); if (ret) exit(1); } break; case 2: - if (data.image_dcd_offset + sizeof(struct imx_flash_header_v2) + + if (data.image_ivt_offset + sizeof(struct imx_flash_header_v2) + MAX_DCD * sizeof(u32) > HEADER_LEN) { fprintf(stderr, "i.MX v2 header exceeds SW limit set by imx-image\n"); exit(1); @@ -987,45 +977,35 @@ int main(int argc, char *argv[]) exit(1); } - header_copies = (data.cpu_type == IMX_CPU_IMX35) ? 2 : 1; - - for (i = 0; i < header_copies; i++) { - ret = xwrite(outfd, add_barebox_header ? bb_header : buf, - sizeof_bb_header); - if (ret < 0) { - perror("write"); + if (data.cpu_type == IMX_CPU_IMX35) { + xwrite(outfd, buf, header_len); + xwrite(outfd, buf, header_len); + } else { + if (add_barebox_header && + data.image_ivt_offset + data.header_gap < sizeof_bb_header) { + fprintf(stderr, "barebox header conflicts with IVT\n"); exit(1); } - if (lseek(outfd, data.header_gap, SEEK_CUR) < 0) { + if (lseek(outfd, data.header_gap, SEEK_SET) < 0) { perror("lseek"); exit(1); } - ret = xwrite(outfd, buf + sizeof_bb_header, - header_len - sizeof_bb_header); - if (ret < 0) { - perror("write"); - exit(1); - } + xwrite(outfd, buf, header_len); } - ret = xwrite(outfd, infile, insize); - if (ret) { - perror("write"); - exit(1); - } + if (add_barebox_header) + pwrite(outfd, bb_header, sizeof_bb_header, 0); + + xwrite(outfd, infile, insize); /* pad until next 4k boundary */ now = 4096 - (insize % 4096); if (data.csf && now) { memset(buf, 0x5a, now); - ret = xwrite(outfd, buf, now); - if (ret) { - perror("write"); - exit(1); - } + xwrite(outfd, buf, now); } ret = close(outfd); @@ -1054,11 +1034,7 @@ int main(int argc, char *argv[]) exit(1); } - ret = xwrite(outfd, infile, insize); - if (ret < 0) { - perror("write"); - exit (1); - } + xwrite(outfd, infile, insize); close(outfd); } diff --git a/scripts/imx/imx.c b/scripts/imx/imx.c index ea576c22d3..1fb3922fcf 100644 --- a/scripts/imx/imx.c +++ b/scripts/imx/imx.c @@ -211,16 +211,22 @@ static int do_loadaddr(struct config_data *data, int argc, char *argv[]) return 0; } -static int do_dcd_offset(struct config_data *data, int argc, char *argv[]) +static int do_ivt_offset(struct config_data *data, int argc, char *argv[]) { if (argc < 2) return -EINVAL; - data->image_dcd_offset = strtoul(argv[1], NULL, 0); + data->image_ivt_offset = strtoul(argv[1], NULL, 0); return 0; } +static int do_dcdofs_error(struct config_data *data, int argc, char *argv[]) +{ + fprintf(stderr, "ERROR: misnomer dcdofs has been renamed to ivtofs. imxcfg must be adapted.\n"); + return -EINVAL; +} + struct soc_type { char *name; int header_version; @@ -240,6 +246,7 @@ static struct soc_type socs[] = { { .name = "imx6", .header_version = 2, .cpu_type = IMX_CPU_IMX6, .header_gap = 0, .first_opcode = 0xea0003fe /* b 0x1000 */}, { .name = "imx7", .header_version = 2, .cpu_type = IMX_CPU_IMX7, .header_gap = 0, .first_opcode = 0xea0003fe /* b 0x1000 */}, { .name = "imx8mm", .header_version = 2, .cpu_type = IMX_CPU_IMX8MM, .header_gap = SZ_32K, .first_opcode = 0x14000000 /* b 0x0000 (offset computed) */}, + { .name = "imx8mp", .header_version = 2, .cpu_type = IMX_CPU_IMX8MP, .header_gap = SZ_32K, .first_opcode = 0x14000000 /* b 0x0000 (offset computed) */}, { .name = "imx8mq", .header_version = 2, .cpu_type = IMX_CPU_IMX8MQ, .header_gap = SZ_32K, .first_opcode = 0x14000000 /* b 0x0000 (offset computed) */}, { .name = "vf610", .header_version = 2, .cpu_type = IMX_CPU_VF610, .header_gap = 0, .first_opcode = 0xea0003fe /* b 0x1000 */}, }; @@ -334,7 +341,7 @@ static int do_hab_blocks(struct config_data *data, int argc, char *argv[]) char *str; int ret; uint32_t signed_size = data->load_size; - uint32_t offset = data->image_dcd_offset; + uint32_t offset = data->image_ivt_offset; if (!data->csf) return -EINVAL; @@ -358,8 +365,8 @@ static int do_hab_blocks(struct config_data *data, int argc, char *argv[]) if (signed_size > 0) { ret = asprintf(&str, "Blocks = 0x%08x 0x%08x 0x%08x \"%s\"\n", - data->image_load_addr + data->image_dcd_offset, offset, - signed_size - data->image_dcd_offset, data->outfile); + data->image_load_addr + data->image_ivt_offset, offset, + signed_size - data->image_ivt_offset, data->outfile); } else { fprintf(stderr, "Invalid signed size area 0x%08x\n", signed_size); @@ -585,8 +592,11 @@ struct command cmds[] = { .name = "loadaddr", .parse = do_loadaddr, }, { + .name = "ivtofs", + .parse = do_ivt_offset, + }, { .name = "dcdofs", - .parse = do_dcd_offset, + .parse = do_dcdofs_error, }, { .name = "soc", .parse = do_soc, diff --git a/scripts/imx/imx.h b/scripts/imx/imx.h index d466e5dad0..7a3ac31cd2 100644 --- a/scripts/imx/imx.h +++ b/scripts/imx/imx.h @@ -4,7 +4,14 @@ static inline int cpu_is_mx8m(const struct config_data *data) { - return data->cpu_type == IMX_CPU_IMX8MQ || data->cpu_type == IMX_CPU_IMX8MM; + switch (data->cpu_type) { + case IMX_CPU_IMX8MQ: + case IMX_CPU_IMX8MM: + case IMX_CPU_IMX8MP: + return true; + default: + return false; + } } int parse_config(struct config_data *data, const char *filename); diff --git a/scripts/regsubst.pl b/scripts/regsubst.pl index 3b6b8aa2e9..026c4eed2f 100755 --- a/scripts/regsubst.pl +++ b/scripts/regsubst.pl @@ -45,7 +45,7 @@ First you have to add the right #include directives to your file: $ cat flash-header-myboard.imxcfg soc imx6 loadaddr 0x20000000 - dcdofs 0x400 + ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> @@ -59,7 +59,7 @@ Then you can process the file with B<regsubst.pl>: $ scripts/regsubst.pl -I arch/arm/mach-imx/include flash-header-myboard.imxcfg soc imx6 loadaddr 0x20000000 - dcdofs 0x400 + ivtofs 0x400 #include <mach/imx6-ddr-regs.h> #include <mach/imx6dl-ddr-regs.h> |