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-rw-r--r--arch/arm/boards/ls1046ardb/lowlevel.c3
-rw-r--r--arch/arm/boards/tqmls1046a/board.c33
-rw-r--r--arch/arm/boards/tqmls1046a/lowlevel.c93
-rw-r--r--arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg (renamed from arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg)2
-rw-r--r--arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg33
-rw-r--r--arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg84
-rw-r--r--arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg8
-rw-r--r--arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg14
-rw-r--r--arch/arm/configs/layerscape_defconfig8
-rw-r--r--arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts123
-rw-r--r--arch/arm/dts/fsl-tqmls1046a.dtsi4
-rw-r--r--arch/arm/mach-layerscape/Makefile2
-rw-r--r--arch/arm/mach-layerscape/boot.c39
-rw-r--r--arch/arm/mach-layerscape/include/mach/bbu.h22
-rw-r--r--arch/arm/mach-layerscape/include/mach/layerscape.h2
-rw-r--r--arch/arm/mach-layerscape/include/mach/xload.h4
-rw-r--r--arch/arm/mach-layerscape/xload-qspi.c37
-rw-r--r--arch/arm/mach-layerscape/xload.c24
-rw-r--r--common/bbu.c4
-rw-r--r--common/filetype.c7
-rw-r--r--drivers/ddr/fsl/fsl_ddr.h2
-rw-r--r--drivers/mci/imx-esdhc-pbl.c5
-rw-r--r--drivers/net/fsl-fman.c2
-rw-r--r--images/Makefile.layerscape21
-rw-r--r--include/bbu.h4
-rw-r--r--include/filetype.h2
-rw-r--r--include/soc/fsl/fsl_ddr_sdram.h1
-rw-r--r--scripts/pblimage.c36
28 files changed, 413 insertions, 206 deletions
diff --git a/arch/arm/boards/ls1046ardb/lowlevel.c b/arch/arm/boards/ls1046ardb/lowlevel.c
index 6de1606..0c95fbb 100644
--- a/arch/arm/boards/ls1046ardb/lowlevel.c
+++ b/arch/arm/boards/ls1046ardb/lowlevel.c
@@ -3,6 +3,7 @@
#include <common.h>
#include <debug_ll.h>
#include <ddr_spd.h>
+#include <image-metadata.h>
#include <platform_data/mmc-esdhc-imx.h>
#include <i2c/i2c-early.h>
#include <soc/fsl/fsl_ddr_sdram.h>
@@ -201,6 +202,8 @@ static noinline __noreturn void ls1046ardb_r_entry(unsigned long memsize)
debug_ll_init();
ls1046a_init_lowlevel();
+ IMD_USED_OF(fsl_ls1046a_rdb);
+
i2c = ls1046_i2c_init(IOMEM(LSCH2_I2C1_BASE_ADDR));
ret = spd_read_eeprom(i2c, i2c_fsl_xfer, 0x51, &spd_eeprom);
if (ret) {
diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c
index 5d6d5ad..8cc4d73 100644
--- a/arch/arm/boards/tqmls1046a/board.c
+++ b/arch/arm/boards/tqmls1046a/board.c
@@ -3,10 +3,15 @@
#include <common.h>
#include <init.h>
#include <envfs.h>
+#include <bbu.h>
+#include <bootsource.h>
#include <asm/memory.h>
#include <linux/sizes.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <mach/bbu.h>
+#include <mach/layerscape.h>
static int tqmls1046a_mem_init(void)
{
@@ -21,11 +26,39 @@ mem_initcall(tqmls1046a_mem_init);
static int tqmls1046a_postcore_init(void)
{
+ struct ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR);
+ enum bootsource bootsource;
+ unsigned long sd_bbu_flags = 0, qspi_bbu_flags = 0;
+
if (!of_machine_is_compatible("tqc,tqmls1046a"))
return 0;
defaultenv_append_directory(defaultenv_tqmls1046a);
+ /* Configure iomux for i2c4 */
+ out_be32(&scfg->rcwpmuxcr0, 0x3300);
+
+ /* divide CGA1/CGA2 PLL by 24 to get QSPI interface clock */
+ out_be32(&scfg->qspi_cfg, 0x30100000);
+
+ bootsource = ls1046_bootsource_get();
+
+ switch (bootsource) {
+ case BOOTSOURCE_MMC:
+ of_device_enable_path("/chosen/environment-sd");
+ sd_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+ break;
+ case BOOTSOURCE_SPI_NOR:
+ of_device_enable_path("/chosen/environment-qspi");
+ qspi_bbu_flags = BBU_HANDLER_FLAG_DEFAULT;
+ break;
+ default:
+ break;
+ }
+
+ ls1046a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox", sd_bbu_flags);
+ ls1046a_bbu_qspi_register_handler("qspi", "/dev/qspiflash0.barebox", qspi_bbu_flags);
+
return 0;
}
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 044d6a4..dc0e179 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <debug_ll.h>
+#include <image-metadata.h>
#include <platform_data/mmc-esdhc-imx.h>
#include <soc/fsl/fsl_ddr_sdram.h>
#include <soc/fsl/immap_lsch2.h>
@@ -116,7 +117,7 @@ found:
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
/* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x61;
+ popts->cpo_sample = 0x48;
}
static struct dimm_params dimm_params[] = {
@@ -169,37 +170,97 @@ static struct fsl_ddr_controller ddrc[] = {
.erratum_A009942 = 1,
.chip_selects_per_ctrl = 4,
.board_options = ddr_board_options,
+ .fsl_ddr_config_reg = {
+ .cs[0].bnds = 0x0000007F,
+ .cs[0].config = 0x80010312,
+ .cs[0].config_2 = 0x00000000,
+ .cs[1].bnds = 0x00000000,
+ .cs[1].config = 0x00000000,
+ .cs[1].config_2 = 0x00000000,
+ .cs[2].bnds = 0x00000000,
+ .cs[2].config = 0x00000000,
+ .cs[2].config_2 = 0x00000000,
+ .cs[3].bnds = 0x00000000,
+ .cs[3].config = 0x00000000,
+ .cs[3].config_2 = 0x00000000,
+ .timing_cfg_3 = 0x020F1100,
+ .timing_cfg_0 = 0x77660008,
+ .timing_cfg_1 = 0xF1FCC265,
+ .timing_cfg_2 = 0x0059415E,
+ .ddr_sdram_cfg = 0x65000000,
+ .ddr_sdram_cfg_2 = 0x00401150,
+ .ddr_sdram_cfg_3 = 0x00000000,
+ .ddr_sdram_mode = 0x03010625,
+ .ddr_sdram_mode_2 = 0x00100200,
+ .ddr_sdram_mode_3 = 0x00010625,
+ .ddr_sdram_mode_4 = 0x00100200,
+ .ddr_sdram_mode_5 = 0x00010625,
+ .ddr_sdram_mode_6 = 0x00100200,
+ .ddr_sdram_mode_7 = 0x00010625,
+ .ddr_sdram_mode_8 = 0x00100200,
+ .ddr_sdram_mode_9 = 0x00000500,
+ .ddr_sdram_mode_10 = 0x04400000,
+ .ddr_sdram_mode_11 = 0x00000400,
+ .ddr_sdram_mode_12 = 0x04400000,
+ .ddr_sdram_mode_13 = 0x00000400,
+ .ddr_sdram_mode_14 = 0x04400000,
+ .ddr_sdram_mode_15 = 0x00000400,
+ .ddr_sdram_mode_16 = 0x04400000,
+ .ddr_sdram_interval = 0x0F3C0000,
+ .ddr_data_init = 0xDEADBEEF,
+ .ddr_sdram_clk_cntl = 0x02000000,
+ .ddr_init_addr = 0x00000000,
+ .ddr_init_ext_addr = 0x00000000,
+ .timing_cfg_4 = 0x00224002,
+ .timing_cfg_5 = 0x04401400,
+ .timing_cfg_6 = 0x00000000,
+ .timing_cfg_7 = 0x25500000,
+ .timing_cfg_8 = 0x03335A00,
+ .timing_cfg_9 = 0x00000000,
+ .ddr_zq_cntl = 0x8A090705,
+ .ddr_wrlvl_cntl = 0x86550609,
+ .ddr_wrlvl_cntl_2 = 0x09080806,
+ .ddr_wrlvl_cntl_3 = 0x06040409,
+ .ddr_sr_cntr = 0x00000000,
+ .ddr_sdram_rcw_1 = 0x00000000,
+ .ddr_sdram_rcw_2 = 0x00000000,
+ .ddr_sdram_rcw_3 = 0x00000000,
+ .ddr_cdr1 = 0x80080000,
+ .ddr_cdr2 = 0x000000C0,
+ .dq_map_0 = 0x00000000,
+ .dq_map_1 = 0x00000000,
+ .dq_map_2 = 0x00000000,
+ .dq_map_3 = 0x00000000,
+ .debug[28] = 0x00700046,
+ },
},
};
-static struct fsl_ddr_info ls1046a_info = {
- .num_ctrls = ARRAY_SIZE(ddrc),
- .c = ddrc,
-};
-
extern char __dtb_fsl_tqmls1046a_mbls10xxa_start[];
-static noinline __noreturn void tqmls1046a_r_entry(unsigned long memsize)
+static noinline __noreturn void tqmls1046a_r_entry(void)
{
unsigned long membase = LS1046A_DDR_SDRAM_BASE;
- if (get_pc() >= membase) {
- if (memsize + membase >= 0x100000000)
- memsize = 0x100000000 - membase;
-
+ if (get_pc() >= membase)
barebox_arm_entry(membase, 0x80000000,
__dtb_fsl_tqmls1046a_mbls10xxa_start);
- }
arm_cpu_lowlevel_init();
- debug_ll_init();
ls1046a_init_lowlevel();
- memsize = fsl_ddr_sdram(&ls1046a_info);
+ debug_ll_init();
+
+ udelay(500);
+ putc_ll('>');
+
+ IMD_USED_OF(fsl_tqmls1046a_mbls10xxa);
+
+ fsl_ddr_set_memctl_regs(&ddrc[0], 0);
ls1046a_errata_post_ddr();
- ls1046a_esdhc_start_image(memsize, 0, 0);
+ ls1046a_xload_start_image(0, 0, 0);
pr_err("Booting failed\n");
@@ -213,5 +274,5 @@ __noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned lo
relocate_to_current_adr();
setup_c();
- tqmls1046a_r_entry(r0);
+ tqmls1046a_r_entry();
}
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg
index 7ac1398..0a04afa 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_sd.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi.cfg
@@ -1,3 +1,5 @@
+#Configure QSPI clock
+0957015c 40100000
#Configure Scratch register
09570600 00000000
09570604 10000000
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg
deleted file mode 100644
index 32865ca..0000000
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_pbi_qspi.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-#Configure QSPI clock
-0957015c 40100000
-#Configure Scratch register
-09570600 00000000
-09570604 40010000
-#Disable CCI barrier tranaction
-09570178 0000e010
-09180000 00000008
-#USB PHY frequency sel
-09570418 0000009c
-0957041c 0000009c
-09570420 0000009c
-#Serdes SATA
-09eb1300 80104e20
-09eb08dc 00502880
-#PEX gen3 link (errata A-010477)
-09570158 00000300
-89400890 01048000
-89500890 01048000
-89600890 01048000
-#PEX gen3 equalization preset values (errata A-008851)
-894008bc 01000000
-89400154 47474747
-89400158 47474747
-894008bc 00000000
-895008bc 01000000
-89500154 47474747
-89500158 47474747
-895008bc 00000000
-896008bc 01000000
-89600154 47474747
-89600158 47474747
-896008bc 00000000
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg
deleted file mode 100644
index 6c72d00..0000000
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg
+++ /dev/null
@@ -1,84 +0,0 @@
-# RCW values
-# 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00]
-# 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110]
-# 8: 9 - MEM_PLL_CFG : 0 [0x0 / 0b00]
-# 10: 15 - MEM_PLL_RAT : 20 [0x14 / 0b010100]
-# 24: 25 - CGA_PLL1_CFG : 0 [0x0 / 0b00]
-# 26: 31 - CGA_PLL1_RAT : 16 [0x10 / 0b010000]
-# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00]
-# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110]
-# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000]
-# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011]
-# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001]
-# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11]
-# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11]
-# 168:169 - SRDS_PLL_PD_S1 : 0 [0x0 / 0b00]
-# 170:171 - SRDS_PLL_PD_S2 : 0 [0x0 / 0b00]
-# 176:177 - SRDS_DIV_PEX_S1 : 1 [0x1 / 0b01]
-# 178:179 - SRDS_DIV_PEX_S2 : 1 [0x1 / 0b01]
-# 186:187 - DDR_REFCLK_SEL : 0 [0x0 / 0b00]
-# 188:188 - SRDS_REFCLK_SEL_S1 : 0 [0x0 / 0b0]
-# 189:189 - SRDS_REFCLK_SEL_S2 : 0 [0x0 / 0b0]
-# 190:191 - DDR_FDBK_MULT : 2 [0x2 / 0b10]
-# 192:195 - PBI_SRC : 6 [0x6 / 0b0110]
-# 201:201 - BOOT_HO : 0 [0x0 / 0b0]
-# 202:202 - SB_EN : 0 [0x0 / 0b0]
-# 203:211 - IFC_MODE : 64 [0x40 / 0b001000000]
-# 224:226 - HWA_CGA_M1_CLK_SEL : 6 [0x6 / 0b110]
-# 230:231 - DRAM_LAT : 1 [0x1 / 0b01]
-# 232:232 - DDR_RATE : 0 [0x0 / 0b0]
-# 234:234 - DDR_RSV0 : 0 [0x0 / 0b0]
-# 242:242 - SYS_PLL_SPD : 0 [0x0 / 0b0]
-# 243:243 - MEM_PLL_SPD : 0 [0x0 / 0b0]
-# 244:244 - CGA_PLL1_SPD : 0 [0x0 / 0b0]
-# 245:245 - CGA_PLL2_SPD : 0 [0x0 / 0b0]
-# 264:266 - HOST_AGT_PEX : 0 [0x0 / 0b000]
-# 288:295 - GP_INFO1 : 0 [0x00 / 0b00000000]
-# 299:319 - GP_INFO2 : 0 [0x00000 / 0b000000000000000000000]
-# 354:356 - UART_EXT : 0 [0x0 / 0b000]
-# 357:359 - IRQ_EXT : 0 [0x0 / 0b000]
-# 360:362 - SPI_EXT : 0 [0x0 / 0b000]
-# 363:365 - SDHC_EXT : 0 [0x0 / 0b000]
-# 366:368 - UART_BASE : 5 [0x5 / 0b101]
-# 369:369 - ASLEEP : 0 [0x0 / 0b0]
-# 370:370 - RTC : 0 [0x0 / 0b0]
-# 371:371 - SDHC_BASE : 0 [0x0 / 0b0]
-# 372:372 - IRQ_OUT : 1 [0x1 / 0b1]
-# 373:381 - IRQ_BASE : 0 [0x00 / 0b000000000]
-# 382:383 - SPI_BASE : 0 [0x0 / 0b00]
-# 384:386 - IFC_GRP_A_EXT : 1 [0x1 / 0b001]
-# 393:395 - IFC_GRP_D_EXT : 0 [0x0 / 0b000]
-# 396:398 - IFC_GRP_E1_EXT : 0 [0x0 / 0b000]
-# 399:401 - IFC_GRP_F_EXT : 1 [0x1 / 0b001]
-# 405:405 - IFC_GRP_E1_BASE : 0 [0x0 / 0b0]
-# 407:407 - IFC_GRP_D_BASE : 0 [0x0 / 0b0]
-# 412:413 - IFC_GRP_A_BASE : 0 [0x0 / 0b00]
-# 415:415 - IFC_A_22_24 : 0 [0x0 / 0b0]
-# 416:418 - EC1 : 0 [0x0 / 0b000]
-# 419:421 - EC2 : 0 [0x0 / 0b000]
-# 422:423 - LVDD_VSEL : 1 [0x1 / 0b01]
-# 424:424 - I2C_IPGCLK_SEL : 0 [0x0 / 0b0]
-# 425:425 - EM1 : 0 [0x0 / 0b0]
-# 426:426 - EM2 : 0 [0x0 / 0b0]
-# 427:427 - EMI2_DMODE : 1 [0x1 / 0b1]
-# 428:428 - EMI2_CMODE : 0 [0x0 / 0b0]
-# 429:429 - USB_DRVVBUS : 0 [0x0 / 0b0]
-# 430:430 - USB_PWRFAULT : 0 [0x0 / 0b0]
-# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01]
-# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10]
-# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1]
-# 439:440 - EVDD_VSEL : 0 [0x0 / 0b00]
-# 441:443 - IIC2_BASE : 0 [0x0 / 0b000]
-# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0]
-# 445:447 - IIC2_EXT : 2 [0x2 / 0b010]
-# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000]
-# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001]
-
-
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-0c140010 0e000000 00000000 00000000
-33335559 f0005002 60040000 c1000000
-00000000 00000000 00000000 00028800
-20004000 01103202 00000096 00000001
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
index 395c75c..2df229c 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg
@@ -8,7 +8,7 @@
# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00]
# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110]
# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000]
-# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011]
+# 128:143 - SRDS_PRTCL_S1 : 4403 [0x1133 / 0b0001000100110011]
# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001]
# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11]
# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11]
@@ -39,7 +39,7 @@
# 357:359 - IRQ_EXT : 0 [0x0 / 0b000]
# 360:362 - SPI_EXT : 0 [0x0 / 0b000]
# 363:365 - SDHC_EXT : 0 [0x0 / 0b000]
-# 366:368 - UART_BASE : 5 [0x5 / 0b101]
+# 366:368 - UART_BASE : 6 [0x6 / 0b110]
# 369:369 - ASLEEP : 0 [0x0 / 0b0]
# 370:370 - RTC : 0 [0x0 / 0b0]
# 371:371 - SDHC_BASE : 0 [0x0 / 0b0]
@@ -79,6 +79,6 @@
aa55aa55 01ee0100
# RCW
0c140010 0e000000 00000000 00000000
-33335559 f0005002 40025000 c1000000
-00000000 00000000 00000000 00028800
+11335559 f0005002 40025000 c1000000
+00000000 00000000 00000000 00030800
20004000 01103202 00000096 00000001
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
index 4ef6d57..72ab1cd 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
@@ -8,7 +8,7 @@
# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00]
# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110]
# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000]
-# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011]
+# 128:143 - SRDS_PRTCL_S1 : 4403 [0x1133 / 0b0001000100110011]
# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001]
# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11]
# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11]
@@ -39,7 +39,7 @@
# 357:359 - IRQ_EXT : 0 [0x0 / 0b000]
# 360:362 - SPI_EXT : 0 [0x0 / 0b000]
# 363:365 - SDHC_EXT : 0 [0x0 / 0b000]
-# 366:368 - UART_BASE : 5 [0x5 / 0b101]
+# 366:368 - UART_BASE : 6 [0x6 / 0b110]
# 369:369 - ASLEEP : 0 [0x0 / 0b0]
# 370:370 - RTC : 0 [0x0 / 0b0]
# 371:371 - SDHC_BASE : 0 [0x0 / 0b0]
@@ -67,10 +67,10 @@
# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01]
# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10]
# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1]
-# 439:440 - EVDD_VSEL : 2 [0x2 / 0b10]
+# 439:440 - EVDD_VSEL : 0 [0x0 / 0b00]
# 441:443 - IIC2_BASE : 0 [0x0 / 0b000]
# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0]
-# 445:447 - IIC2_EXT : 1 [0x1 / 0b001]
+# 445:447 - IIC2_EXT : 2 [0x2 / 0b010]
# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000]
# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001]
@@ -79,6 +79,6 @@
aa55aa55 01ee0100
# RCW
0c140010 0e000000 00000000 00000000
-33335559 f0005002 60040000 c1000000
-00000000 00000000 00000000 00028800
-20004000 01103301 00000096 00000001
+11335559 f0005002 60040000 c1000000
+00000000 00000000 00000000 00030800
+20004000 01103202 00000096 00000001
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index dadbcc2..b81f375 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -22,7 +22,6 @@ CONFIG_PBL_CONSOLE=y
CONFIG_PARTITION_DISK_EFI=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_RESET_SOURCE=y
-CONFIG_DEBUG_LL=y
CONFIG_CMD_DMESG=y
CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
@@ -85,8 +84,13 @@ CONFIG_DRIVER_NET_FSL_FMAN=y
CONFIG_DP83867_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_NET_DSA_MV88E6XXX=y
+CONFIG_DRIVER_SPI_FSL_QUADSPI=y
CONFIG_I2C=y
CONFIG_I2C_IMX=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
CONFIG_MCI=y
CONFIG_MCI_MMC_BOOT_PARTITIONS=y
CONFIG_MCI_IMX_ESDHC=y
@@ -94,10 +98,12 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_OF=y
CONFIG_LED_TRIGGERS=y
+CONFIG_LED_PCA955X=y
CONFIG_EEPROM_AT25=y
CONFIG_EEPROM_AT24=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
+CONFIG_GPIO_PCA953X=y
CONFIG_NVMEM=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED=y
diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
index f21479e..f0332e3 100644
--- a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
+++ b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
@@ -20,10 +20,30 @@
serial0 = &duart0;
serial1 = &duart1;
mmc0 = &esdhc;
+ qspiflash0 = &qflash0;
+ qspiflash1 = &qflash1;
+ qsgmii_s1_p1 = &qsgmii1_phy1;
+ qsgmii_s1_p2 = &qsgmii1_phy2;
+ qsgmii_s2_p1 = &qsgmii2_phy1;
+ qsgmii_s2_p2 = &qsgmii2_phy2;
+ qsgmii_s2_p3 = &qsgmii2_phy3;
+ qsgmii_s2_p4 = &qsgmii2_phy4;
};
chosen {
stdout-path = "serial1:115200n8";
+
+ environment-sd {
+ compatible = "barebox,environment";
+ device-path = &environment_sd;
+ status = "disabled";
+ };
+
+ environment-qspi {
+ compatible = "barebox,environment";
+ device-path = &environment_qspi;
+ status = "disabled";
+ };
};
gpio-keys-polled {
@@ -57,6 +77,24 @@
};
+&esdhc {
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "fixed-partitions";
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x1000 0xdf000>;
+ };
+
+ environment_sd: partition@e0000 {
+ label = "barebox-environment";
+ reg = <0xe0000 0x20000>;
+ };
+ };
+};
&duart0 {
status = "okay";
@@ -66,6 +104,14 @@
status = "okay";
};
+&esdhc {
+ mmc-hs200-1_8v;
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+};
+
&i2c3 {
status = "okay";
@@ -132,43 +178,40 @@
&fman0 {
status = "okay";
- ethernet@e0000 {
- status = "disabled";
+ ethernet@e0000 { /* EMAC.1 */
+ phy-connection-type = "sgmii";
+
};
- ethernet@e2000 {
- phy-handle = <&qsgmii1_phy2>;
+ ethernet@e2000 { /* EMAC.2 */
phy-connection-type = "sgmii";
};
- ethernet@e4000 {
+ ethernet@e4000 { /* EMAC.3 */
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
phy-mode = "rgmii-id";
};
- ethernet@e6000 {
+ ethernet@e6000 { /* EMAC.4 */
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
phy-mode = "rgmii-id";
};
- ethernet@e8000 {
- status = "disabled";
+ ethernet@e8000 { /* EMAC.5 */
+ phy-connection-type = "sgmii";
};
- ethernet@ea000 {
- phy-handle = <&qsgmii2_phy2>;
+ ethernet@ea000 { /* EMAC.6 */
phy-connection-type = "sgmii";
};
- ethernet@f0000 {
- phy-handle = <&qsgmii1_phy1>;
+ ethernet@f0000 { /* EMAC.9 */
phy-connection-type = "sgmii";
};
- ethernet@f2000 {
- phy-handle = <&qsgmii2_phy1>;
+ ethernet@f2000 { /* EMAC.10 */
phy-connection-type = "sgmii";
};
@@ -212,6 +255,13 @@
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
};
+ rgmii_phy2: ethernet-phy@0c {
+ reg = <0x0c>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ };
+
qsgmii1_phy1: ethernet-phy@1c {
reg = <0x1c>;
};
@@ -219,15 +269,6 @@
qsgmii1_phy2: ethernet-phy@1d {
reg = <0x1d>;
};
- };
-
- mdio@fd000 {
- rgmii_phy2: ethernet-phy@0c {
- reg = <0x0c>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
- };
qsgmii2_phy1: ethernet-phy@00 {
reg = <0x00>;
@@ -236,5 +277,41 @@
qsgmii2_phy2: ethernet-phy@01 {
reg = <0x01>;
};
+
+ qsgmii2_phy3: ethernet-phy@02 {
+ reg = <0x02>;
+ };
+
+ qsgmii2_phy4: ethernet-phy@03 {
+ reg = <0x03>;
+ };
+ };
+
+ mdio@fd000 {
+ status = "disabled";
+ };
+};
+
+&qflash0 {
+ partitions {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "fixed-partitions";
+
+ partition@0 {
+ label = "barebox";
+ reg = <0x0 0x200000>;
+ };
+
+ environment_qspi: partition@200000 {
+ label = "barebox-environment";
+ reg = <0x200000 0x80000>;
+ };
+
+ partition@280000 {
+ label = "data";
+ reg = <0x280000 0x0>;
+ };
};
};
diff --git a/arch/arm/dts/fsl-tqmls1046a.dtsi b/arch/arm/dts/fsl-tqmls1046a.dtsi
index 4717e66..0ea2612 100644
--- a/arch/arm/dts/fsl-tqmls1046a.dtsi
+++ b/arch/arm/dts/fsl-tqmls1046a.dtsi
@@ -40,15 +40,15 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <108000000>;
+ spi-max-frequency = <62500000>;
reg = <0>;
};
qflash1: mx66u51235f@1 {
#address-cells = <1>;
#size-cells = <1>;
- spi-max-frequency = <108000000>;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <62500000>;
reg = <1>;
};
};
diff --git a/arch/arm/mach-layerscape/Makefile b/arch/arm/mach-layerscape/Makefile
index 2698392..73cd61a 100644
--- a/arch/arm/mach-layerscape/Makefile
+++ b/arch/arm/mach-layerscape/Makefile
@@ -2,3 +2,5 @@ obj- := __dummy__.o
lwl-y += lowlevel.o errata.o
lwl-$(CONFIG_ARCH_LS1046) += lowlevel-ls1046a.o
obj-y += icid.o
+obj-pbl-y += boot.o
+pbl-y += xload-qspi.o xload.o
diff --git a/arch/arm/mach-layerscape/boot.c b/arch/arm/mach-layerscape/boot.c
new file mode 100644
index 0000000..c804977
--- /dev/null
+++ b/arch/arm/mach-layerscape/boot.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <init.h>
+#include <bootsource.h>
+#include <mach/layerscape.h>
+#include <soc/fsl/immap_lsch2.h>
+
+enum bootsource ls1046_bootsource_get(void)
+{
+ void __iomem *dcfg = IOMEM(LSCH2_DCFG_ADDR);
+ uint32_t rcw_src;
+
+ rcw_src = in_be32(dcfg) >> 23;
+
+ if (rcw_src == 0x40)
+ return BOOTSOURCE_MMC;
+ if ((rcw_src & 0x1fe) == 0x44)
+ return BOOTSOURCE_SPI_NOR;
+ if ((rcw_src & 0x1f0) == 0x10)
+ /* 8bit NOR Flash */
+ return BOOTSOURCE_NOR;
+ if ((rcw_src & 0x1f0) == 0x20)
+ /* 16bit NOR Flash */
+ return BOOTSOURCE_NOR;
+
+ return BOOTSOURCE_UNKNOWN;
+}
+
+static int ls1046a_bootsource_init(void)
+{
+ if (!of_machine_is_compatible("fsl,ls1046a"))
+ return 0;
+
+ bootsource_set(ls1046_bootsource_get());
+
+ return 0;
+}
+coredevice_initcall(ls1046a_bootsource_init); \ No newline at end of file
diff --git a/arch/arm/mach-layerscape/include/mach/bbu.h b/arch/arm/mach-layerscape/include/mach/bbu.h
new file mode 100644
index 0000000..1ea0cbb
--- /dev/null
+++ b/arch/arm/mach-layerscape/include/mach/bbu.h
@@ -0,0 +1,22 @@
+#ifndef __MACH_LAYERSCAPE_BBU_H
+#define __MACH_LAYERSCAPE_BBU_H
+
+#include <bbu.h>
+
+static inline int ls1046a_bbu_mmc_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+{
+ return bbu_register_std_file_update(name, flags, devicefile,
+ filetype_layerscape_image);
+}
+
+static inline int ls1046a_bbu_qspi_register_handler(const char *name,
+ const char *devicefile,
+ unsigned long flags)
+{
+ return bbu_register_std_file_update(name, flags, devicefile,
+ filetype_layerscape_qspi_image);
+}
+
+#endif /* __MACH_LAYERSCAPE_BBU_H */ \ No newline at end of file
diff --git a/arch/arm/mach-layerscape/include/mach/layerscape.h b/arch/arm/mach-layerscape/include/mach/layerscape.h
index 55e0b7b..3366e7f 100644
--- a/arch/arm/mach-layerscape/include/mach/layerscape.h
+++ b/arch/arm/mach-layerscape/include/mach/layerscape.h
@@ -4,4 +4,6 @@
#define LS1046A_DDR_SDRAM_BASE 0x80000000
#define LS1046A_DDR_FREQ 2100000000
+enum bootsource ls1046_bootsource_get(void);
+
#endif /* __MACH_LAYERSCAPE_H */
diff --git a/arch/arm/mach-layerscape/include/mach/xload.h b/arch/arm/mach-layerscape/include/mach/xload.h
index fedd36e..eb2d998 100644
--- a/arch/arm/mach-layerscape/include/mach/xload.h
+++ b/arch/arm/mach-layerscape/include/mach/xload.h
@@ -2,5 +2,9 @@
#define __MACH_XLOAD_H
int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long r2);
+int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
+ unsigned long r2);
+int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
+ unsigned long r2);
#endif /* __MACH_XLOAD_H */
diff --git a/arch/arm/mach-layerscape/xload-qspi.c b/arch/arm/mach-layerscape/xload-qspi.c
new file mode 100644
index 0000000..c76780a
--- /dev/null
+++ b/arch/arm/mach-layerscape/xload-qspi.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <soc/fsl/immap_lsch2.h>
+#include <asm-generic/sections.h>
+#include <asm/cache.h>
+#include <mach/xload.h>
+#include <mach/layerscape.h>
+
+/*
+ * The offset of the 2nd stage image in the output file. This must match with the
+ * offset the pblimage tool puts barebox to.
+ */
+#define BAREBOX_START (128 * 1024)
+
+int ls1046a_qspi_start_image(unsigned long r0, unsigned long r1,
+ unsigned long r2)
+{
+ void *qspi_reg_base = IOMEM(LSCH2_QSPI0_BASE_ADDR);
+ void *membase = (void *)LS1046A_DDR_SDRAM_BASE;
+ void *qspi_mem_base = IOMEM(0x40000000);
+ void (*barebox)(unsigned long, unsigned long, unsigned long) = membase;
+
+ /* Switch controller into little endian mode */
+ out_be32(qspi_reg_base, 0x000f400c);
+
+ memcpy(membase, qspi_mem_base + BAREBOX_START, barebox_image_size);
+ icache_invalidate();
+
+ printf("Starting barebox\n");
+
+ barebox(r0, r1, r2);
+
+ printf("failed\n");
+
+ return -EIO;
+}
diff --git a/arch/arm/mach-layerscape/xload.c b/arch/arm/mach-layerscape/xload.c
new file mode 100644
index 0000000..54495d7
--- /dev/null
+++ b/arch/arm/mach-layerscape/xload.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <bootsource.h>
+#include <mach/layerscape.h>
+#include <mach/xload.h>
+
+int ls1046a_xload_start_image(unsigned long r0, unsigned long r1,
+ unsigned long r2)
+{
+ enum bootsource src;
+
+ src = ls1046_bootsource_get();
+
+ switch (src) {
+ case BOOTSOURCE_SPI_NOR:
+ return ls1046a_qspi_start_image(r0, r1, r2);
+ case BOOTSOURCE_MMC:
+ return ls1046a_esdhc_start_image(r0, r1, r2);
+ default:
+ pr_err("Unknown bootsource\n");
+ return -EINVAL;
+ }
+}
diff --git a/common/bbu.c b/common/bbu.c
index 5cb09e4..00bec32 100644
--- a/common/bbu.c
+++ b/common/bbu.c
@@ -299,6 +299,8 @@ static int bbu_std_file_handler(struct bbu_handler *handler,
return -EINVAL;
}
+ device_detect_by_name(devpath_to_name(data->devicefile));
+
ret = stat(data->devicefile, &s);
if (ret) {
oflags |= O_CREAT;
@@ -361,7 +363,7 @@ err_close:
* Return: 0 if successful, negative error code otherwise
*/
int bbu_register_std_file_update(const char *name, unsigned long flags,
- char *devicefile, enum filetype imagetype)
+ const char *devicefile, enum filetype imagetype)
{
struct bbu_std *std;
struct bbu_handler *handler;
diff --git a/common/filetype.c b/common/filetype.c
index fb029a7..e2d707b 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -75,6 +75,8 @@ static const struct filetype_str filetype_str[] = {
[filetype_elf] = { "ELF", "elf" },
[filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
[filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
+ [filetype_layerscape_image] = { "Layerscape image", "layerscape-PBL" },
+ [filetype_layerscape_qspi_image] = { "Layerscape QSPI image", "layerscape-qspi-PBL" },
};
const char *file_type_to_string(enum filetype f)
@@ -329,6 +331,11 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
if (is_sparse_image(_buf))
return filetype_android_sparse;
+ if (buf[0] == 0x55aa55aa && buf[1] == 0x0001ee01)
+ return filetype_layerscape_image;
+ if (buf[0] == 0x01ee0100 && buf[1] == 0xaa55aa55)
+ return filetype_layerscape_qspi_image;
+
if (bufsize < 64)
return filetype_unknown;
diff --git a/drivers/ddr/fsl/fsl_ddr.h b/drivers/ddr/fsl/fsl_ddr.h
index ee6069d..ab991a5 100644
--- a/drivers/ddr/fsl/fsl_ddr.h
+++ b/drivers/ddr/fsl/fsl_ddr.h
@@ -227,8 +227,6 @@ unsigned int mclk_to_picos(struct fsl_ddr_controller *c, unsigned int mclk);
unsigned int get_memory_clk_period_ps(struct fsl_ddr_controller *c);
unsigned int picos_to_mclk(struct fsl_ddr_controller *c, unsigned int picos);
-void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step);
-
void erratum_a009942_check_cpo(void);
#endif
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index f7f8c33..0251757 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -16,6 +16,7 @@
#include <mci.h>
#include <linux/sizes.h>
#include <asm-generic/sections.h>
+#include <asm/cache.h>
#include <mach/xload.h>
#ifdef CONFIG_ARCH_IMX
#include <mach/atf.h>
@@ -445,7 +446,7 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
*/
val = esdhc_read32(&esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
val &= ~0x0000fff0;
- val |= (2 << 8) | (6 << 4);
+ val |= (8 << 8) | (3 << 4);
esdhc_write32(&esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
esdhc_write32(&esdhc, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP);
@@ -457,6 +458,8 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
return ret;
}
+ icache_invalidate();
+
printf("Starting barebox\n");
barebox(r0, r1, r2);
diff --git a/drivers/net/fsl-fman.c b/drivers/net/fsl-fman.c
index 1a11ca4..4e6bb2e 100644
--- a/drivers/net/fsl-fman.c
+++ b/drivers/net/fsl-fman.c
@@ -640,6 +640,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
i * MAX_RXBUF_LEN));
buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
i * MAX_RXBUF_LEN));
+ dma_sync_single_for_device((unsigned long)rx_buf_pool + i * MAX_RXBUF_LEN,
+ MAX_RXBUF_LEN, DMA_FROM_DEVICE);
muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
out_be32(&rxbd->buf_ptr_lo, buf_lo);
rxbd++;
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index 47df377..d20cc6a 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -14,6 +14,12 @@ quiet_cmd_lspbl_image = LSPBL-IMG $@
$(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) \
-m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
+quiet_cmd_lspbl_spi_image = LSPBL-SPI-IMG $@
+ cmd_lspbl_spi_image = $(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-rcw-tmp) $(word 2,$^) ; \
+ $(CPP) $(lspbl_cfg_cpp_flags) -o $(lspbl-pbi-tmp) $(word 3,$^) ; \
+ $(objtree)/scripts/pblimage -o $@ -r $(lspbl-rcw-tmp) -s \
+ -m $($(patsubst $(obj)/%.pblb,PBL_CODE_SIZE_%,$<)) -p $(lspbl-pbi-tmp) -i $<
+
pbl-$(CONFIG_MACH_LS1046ARDB) += start_ls1046ardb.pbl
$(obj)/barebox-ls1046ardb-2nd.image: $(obj)/start_ls1046ardb.pblb
$(call if_changed,shipped)
@@ -31,7 +37,7 @@ $(obj)/barebox-ls1046ardb-emmc.image: $(obj)/start_ls1046ardb.pblb \
$(obj)/barebox-ls1046ardb-qspi.image: $(obj)/start_ls1046ardb.pblb \
$(board)/ls1046ardb/ls1046ardb_rcw_qspi.cfg \
$(board)/ls1046ardb/ls1046ardb_pbi.cfg
- $(call if_changed,lspbl_image)
+ $(call if_changed,lspbl_spi_image)
image-$(CONFIG_MACH_LS1046ARDB) += barebox-ls1046ardb-sd.image barebox-ls1046ardb-qspi.image \
barebox-ls1046ardb-emmc.image barebox-ls1046ardb-2nd.image
@@ -42,18 +48,13 @@ $(obj)/barebox-tqmls1046a-2nd.image: $(obj)/start_tqmls1046a.pblb
$(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg \
- $(board)/tqmls1046a/tqmls1046a_pbi_sd.cfg
- $(call if_changed,lspbl_image)
-
-$(obj)/barebox-tqmls1046a-emmc.image: $(obj)/start_tqmls1046a.pblb \
- $(board)/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg \
- $(board)/tqmls1046a/tqmls1046a_pbi_sd.cfg
+ $(board)/tqmls1046a/tqmls1046a_pbi.cfg
$(call if_changed,lspbl_image)
$(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \
- $(board)/tqmls1046a/tqmls1046a_pbi_qspi.cfg
- $(call if_changed,lspbl_image)
+ $(board)/tqmls1046a/tqmls1046a_pbi.cfg
+ $(call if_changed,lspbl_spi_image)
-image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image barebox-tqmls1046a-emmc.image \
+image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \
barebox-tqmls1046a-qspi.image barebox-tqmls1046a-2nd.image
diff --git a/include/bbu.h b/include/bbu.h
index 0ed355b..9da6785 100644
--- a/include/bbu.h
+++ b/include/bbu.h
@@ -54,7 +54,7 @@ int bbu_handlers_iterate(int (*fn)(struct bbu_handler *, void *), void *);
int bbu_register_handler(struct bbu_handler *);
int bbu_register_std_file_update(const char *name, unsigned long flags,
- char *devicefile, enum filetype imagetype);
+ const char *devicefile, enum filetype imagetype);
#else
@@ -64,7 +64,7 @@ static inline int bbu_register_handler(struct bbu_handler *unused)
}
static inline int bbu_register_std_file_update(const char *name, unsigned long flags,
- char *devicefile, enum filetype imagetype)
+ const char *devicefile, enum filetype imagetype)
{
return -ENOSYS;
}
diff --git a/include/filetype.h b/include/filetype.h
index 395053d..dcb331a 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -45,6 +45,8 @@ enum filetype {
filetype_elf,
filetype_imx_image_v1,
filetype_imx_image_v2,
+ filetype_layerscape_image,
+ filetype_layerscape_qspi_image,
filetype_max,
};
diff --git a/include/soc/fsl/fsl_ddr_sdram.h b/include/soc/fsl/fsl_ddr_sdram.h
index 07d0af9..80508ef 100644
--- a/include/soc/fsl/fsl_ddr_sdram.h
+++ b/include/soc/fsl/fsl_ddr_sdram.h
@@ -540,6 +540,7 @@ struct fsl_ddr_info {
};
phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo);
+void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step);
#ifdef CONFIG_SYS_FSL_DDR_LE
#define ddr_in32(a) in_le32(a)
diff --git a/scripts/pblimage.c b/scripts/pblimage.c
index 6e83c52..73c0169 100644
--- a/scripts/pblimage.c
+++ b/scripts/pblimage.c
@@ -13,6 +13,7 @@
#include <stdint.h>
#include <getopt.h>
#include <endian.h>
+#include <byteswap.h>
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
#define PBL_ACS_CONT_CMD 0x81000000
@@ -49,11 +50,11 @@ static int pbl_end;
static int image_size;
static int out_fd;
static int in_fd;
+static int spiimage;
static uint32_t pbl_cmd_initaddr;
static uint32_t pbi_crc_cmd1;
static uint32_t pbi_crc_cmd2;
-static uint32_t pbl_end_cmd[4];
enum arch {
ARCH_ARM,
@@ -210,16 +211,6 @@ static void pbl_parser(char *name)
static void add_end_cmd(void)
{
uint32_t crc32_pbl;
- int i;
- unsigned char *p = (unsigned char *)&pbl_end_cmd;
-
- for (i = 0; i < 4; i++)
- pbl_end_cmd[i] = htobe32(pbl_end_cmd[i]);
-
- for (i = 0; i < 16; i++) {
- *pmem_buf++ = *p++;
- pbl_size++;
- }
/* Add PBI CRC command. */
*pmem_buf++ = 0x08;
@@ -240,6 +231,7 @@ static void add_end_cmd(void)
static void pbl_load_image(void)
{
int size;
+ uint64_t *buf64 = (void *)mem_buf;
/* parse the rcw.cfg file. */
pbl_parser(rcwfile);
@@ -256,6 +248,15 @@ static void pbl_load_image(void)
add_end_cmd();
+ if (spiimage) {
+ int i;
+
+ pbl_size = roundup(pbl_size, 8);
+
+ for (i = 0; i < pbl_size / 8; i++)
+ buf64[i] = bswap_64(buf64[i]);
+ }
+
size = pbl_size;
if (write(out_fd, (const void *)&mem_buf, size) != size) {
@@ -297,18 +298,10 @@ static int pblimage_check_params(void)
pbl_cmd_initaddr = loadaddr & PBL_ADDR_24BIT_MASK;
pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
pbl_cmd_initaddr += image_size;
- pbl_end_cmd[0] = 0x09610000;
- pbl_end_cmd[1] = 0x00000000;
- pbl_end_cmd[2] = 0x096100c0;
- pbl_end_cmd[3] = 0x00000000;
} else {
pbi_crc_cmd1 = 0x13;
pbi_crc_cmd2 = 0x80;
pbl_cmd_initaddr = 0x82000000;
- pbl_end_cmd[0] = 0x091380c0;
- pbl_end_cmd[1] = 0x00000000;
- pbl_end_cmd[2] = 0x091380c0;
- pbl_end_cmd[3] = 0x00000000;
}
next_pbl_cmd = pbl_cmd_initaddr;
@@ -357,7 +350,7 @@ int main(int argc, char *argv[])
int opt, ret;
off_t pos;
- while ((opt = getopt(argc, argv, "i:r:p:o:m:")) != -1) {
+ while ((opt = getopt(argc, argv, "i:r:p:o:m:s")) != -1) {
switch (opt) {
case 'i':
infile = optarg;
@@ -374,6 +367,9 @@ int main(int argc, char *argv[])
case 'm':
pbl_end = atoi(optarg);
break;
+ case 's':
+ spiimage = 1;
+ break;
default:
exit(EXIT_FAILURE);
}