diff options
| -rw-r--r-- | drivers/ddr/imx8m/ddr_init.c | 18 | ||||
| -rw-r--r-- | drivers/ddr/imx8m/helper.c | 6 | ||||
| -rw-r--r-- | include/soc/imx8m/ddr.h | 1 |
3 files changed, 25 insertions, 0 deletions
diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index ae05b13622..9a4b4e2ca8 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -13,14 +13,32 @@ #include <mach/imx8m-regs.h> #include <mach/imx8m-ccm-regs.h> +bool imx8m_ddr_old_spreadsheet = true; + static void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) { int i = 0; for (i = 0; i < num; i++) { + if (ddrc_cfg->reg == DDRC_ADDRMAP7(0)) + imx8m_ddr_old_spreadsheet = false; reg32_write((unsigned long)ddrc_cfg->reg, ddrc_cfg->val); ddrc_cfg++; } + + /* + * Older NXP DDR configuration spreadsheets don't initialize ADDRMAP7, + * which falsifies the memory size read back from the controller + * in barebox proper. + */ + if (imx8m_ddr_old_spreadsheet) { + pr_warn("Working around old spreadsheet. Please regenerate\n"); + /* + * Alternatively, stick { DDRC_ADDRMAP7(0), 0xf0f } into + * struct dram_timing_info::ddrc_cfg of your old timing file + */ + reg32_write(DDRC_ADDRMAP7(0), 0xf0f); + } } /* diff --git a/drivers/ddr/imx8m/helper.c b/drivers/ddr/imx8m/helper.c index 94bbb81157..98e4084958 100644 --- a/drivers/ddr/imx8m/helper.c +++ b/drivers/ddr/imx8m/helper.c @@ -62,6 +62,12 @@ void dram_config_save(struct dram_timing_info *timing_info, cfg++; } + if (imx8m_ddr_old_spreadsheet) { + cfg->reg = DDRC_ADDRMAP7(0); + cfg->val = 0xf0f; + cfg++; + } + /* save ddrphy config */ saved_timing->ddrphy_cfg = cfg; for (i = 0; i < timing_info->ddrphy_cfg_num; i++) { diff --git a/include/soc/imx8m/ddr.h b/include/soc/imx8m/ddr.h index 9ae7cb8776..147a7d499a 100644 --- a/include/soc/imx8m/ddr.h +++ b/include/soc/imx8m/ddr.h @@ -407,6 +407,7 @@ static inline void reg32setbit(unsigned long addr, u32 bit) #define dwc_ddrphy_apb_rd(addr) \ reg32_read(IOMEM(IP2APB_DDRPHY_IPS_BASE_ADDR(0)) + 4 * (addr)) +extern bool imx8m_ddr_old_spreadsheet; extern struct dram_cfg_param ddrphy_trained_csr[]; extern uint32_t ddrphy_trained_csr_num; |