diff options
Diffstat (limited to 'arch/arm/boards/a9m2440')
| -rw-r--r-- | arch/arm/boards/a9m2440/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/a9m2410dev.c | 82 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/a9m2440.c | 144 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/baseboards.h | 6 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/config.h | 60 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/env/bin/_update | 34 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/env/bin/boot | 40 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/env/bin/init | 30 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/env/bin/update_kernel | 13 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/env/bin/update_root | 13 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/env/config | 26 | ||||
| -rw-r--r-- | arch/arm/boards/a9m2440/lowlevel_init.S | 243 |
12 files changed, 0 insertions, 696 deletions
diff --git a/arch/arm/boards/a9m2440/Makefile b/arch/arm/boards/a9m2440/Makefile deleted file mode 100644 index e32c0aca64..0000000000 --- a/arch/arm/boards/a9m2440/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -lwl-y += lowlevel_init.o -obj-y += a9m2440.o -obj-$(CONFIG_MACH_A9M2410DEV) += a9m2410dev.o diff --git a/arch/arm/boards/a9m2440/a9m2410dev.c b/arch/arm/boards/a9m2440/a9m2410dev.c deleted file mode 100644 index 627a8c6158..0000000000 --- a/arch/arm/boards/a9m2440/a9m2410dev.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Juergen Beisert - -/** - * @file - * @brief a9m2410dev Baseboad specific initialization routines - * - */ - -#include <common.h> -#include <driver.h> -#include <init.h> -#include <io.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c-busctl.h> -#include <mach/s3c24xx-gpio.h> - -#include "baseboards.h" - -/** - * Initialize the CPU to be able to work with the a9m2410dev evaluation board - */ -int a9m2410dev_devices_init(void) -{ - unsigned int reg; - - /* ---------- configure the GPIOs ------------- */ - writel(0x007FFFFF, S3C_GPACON); - writel(0x00000000, S3C_GPCCON); - writel(0x00000000, S3C_GPCUP); - writel(0x00000000, S3C_GPDCON); - writel(0x00000000, S3C_GPDUP); - writel(0xAAAAAAAA, S3C_GPECON); - writel(0x0000E03F, S3C_GPEUP); - writel(0x00000000, S3C_GPBCON); /* all inputs */ - writel(0x00000007, S3C_GPBUP); /* pullup disabled for GPB0..3 */ - writel(0x00009000, S3C_GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */ - writel(0x000000FF, S3C_GPFUP); - writel(readl(S3C_GPGDAT) | 0x1010, S3C_GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */ - writel(0x0100A93A, S3C_GPGCON); /* switch on USB device */ - writel(0x0000F000, S3C_GPGUP); - writel(0x0029FAAA, S3C_GPHCON); - - writel((1 << 12) | (0 << 11), S3C_GPJDAT); - writel(0x0016aaaa, S3C_GPJCON); - writel(~((0<<12)| (1<<11)), S3C_GPJUP); - - writel((0 << 12) | (0 << 11), S3C_GPJDAT); - writel(0x0016aaaa, S3C_GPJCON); - writel(0x00001fff, S3C_GPJUP); - - writel(0x00000000, S3C_DSC0); - writel(0x00000000, S3C_DSC1); - - /* - * USB port1 normal, USB port0 normal, USB1 pads for device - * PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1, - */ - writel((readl(S3C_MISCCR) & ~0xFFFF) | 0x0140, S3C_MISCCR); - - /* ----------- configure the access to the outer space ---------- */ - reg = readl(S3C_BWSCON); - - /* CS#1 to access the network controller */ - reg &= ~0xf0; - reg |= 0xe0; - writel(0x1350, S3C_BANKCON1); - - /* CS#2 to the dual 16550 UART */ - reg &= ~0xf00; - reg |= 0x400; - writel(0x0d50, S3C_BANKCON2); - - writel(reg, S3C_BWSCON); - - /* release the reset signal to the network and UART device */ - reg = readl(S3C_MISCCR); - reg |= 0x10000; - writel(reg, S3C_MISCCR); - - return 0; -} diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c deleted file mode 100644 index de18ea0120..0000000000 --- a/arch/arm/boards/a9m2440/a9m2440.c +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Juergen Beisert, Pengutronix - -#include <common.h> -#include <driver.h> -#include <init.h> -#include <asm/armlinux.h> -#include <asm/sections.h> -#include <generated/mach-types.h> -#include <partition.h> -#include <nand.h> -#include <io.h> -#include <mach/devices-s3c24xx.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c24xx-nand.h> -#include <mach/s3c-generic.h> -#include <mach/s3c-busctl.h> -#include <mach/s3c24xx-gpio.h> - -#include "baseboards.h" - -static struct s3c24x0_nand_platform_data nand_info = { - .nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1) -}; - -static int a9m2440_check_for_ram(uint32_t addr) -{ - uint32_t tmp1, tmp2; - int rc = 0; - - tmp1 = readl(addr); - tmp2 = readl(addr + sizeof(uint32_t)); - - writel(0xaaaaaaaa, addr); - writel(0x55555555, addr + sizeof(uint32_t)); - if ((readl(addr) != 0xaaaaaaaa) || (readl(addr + sizeof(uint32_t)) != 0x55555555)) - rc = 1; /* seems no RAM */ - - writel(0x55555555, addr); - writel(0xaaaaaaaa, addr + sizeof(uint32_t)); - if ((readl(addr) != 0x55555555) || (readl(addr + sizeof(uint32_t)) != 0xaaaaaaaa)) - rc = 1; /* seems no RAM */ - - writel(tmp1, addr); - writel(tmp2, addr + sizeof(uint32_t)); - - return rc; -} - -static int a9m2440_mem_init(void) -{ - /* - * The special SDRAM setup code for this machine will always enable - * both SDRAM banks. But the second SDRAM device may not exists! - * So we must check here, if the second bank is populated to get the - * correct RAM size. - */ - switch (readl(S3C_BANKSIZE) & 0x7) { - case 0: - if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 32 * 1024 * 1024)) - s3c24xx_disable_second_sdram_bank(); - break; - case 1: - if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 64 * 1024 * 1024)) - s3c24xx_disable_second_sdram_bank(); - break; - case 2: - if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 128 * 1024 * 1024)) - s3c24xx_disable_second_sdram_bank(); - break; - case 4: - case 5: - case 6: /* not supported on this machine */ - break; - default: - if (a9m2440_check_for_ram(S3C_SDRAM_BASE + 16 * 1024 * 1024)) - s3c24xx_disable_second_sdram_bank(); - break; - } - - arm_add_mem_device("ram0", S3C_SDRAM_BASE, s3c24xx_get_memory_size()); - - return 0; -} -mem_initcall(a9m2440_mem_init); - -static int a9m2440_devices_init(void) -{ - uint32_t reg; - - /* ----------- configure the access to the outer space ---------- */ - reg = readl(S3C_BWSCON); - - /* CS#5 to access the network controller */ - reg &= ~0x00f00000; - reg |= 0x00d00000; /* 16 bit */ - writel(0x1f4c, S3C_BANKCON5); - - writel(reg, S3C_BWSCON); - -#ifdef CONFIG_MACH_A9M2410DEV - a9m2410dev_devices_init(); -#endif - - /* release the reset signal to external devices */ - reg = readl(S3C_MISCCR); - reg |= 0x10000; - writel(reg, S3C_MISCCR); - - /* ----------- the devices the boot loader should work with -------- */ - s3c24xx_add_nand(&nand_info); - /* - * cs8900 network controller onboard - * Connected to CS line 5 + A24 and interrupt line EINT9, - * data width is 16 bit - */ - add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, - S3C_CS5_BASE + (1 << 24) + 0x300, 16, IORESOURCE_MEM, NULL); - -#ifdef CONFIG_NAND - /* ----------- add some vital partitions -------- */ - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); -#endif - armlinux_set_architecture(MACH_TYPE_A9M2440); - - return 0; -} - -device_initcall(a9m2440_devices_init); - -static int a9m2440_console_init(void) -{ - barebox_set_model("Digi A9M2440"); - barebox_set_hostname("a9m2440"); - - s3c24xx_add_uart1(); - return 0; -} - -console_initcall(a9m2440_console_init); diff --git a/arch/arm/boards/a9m2440/baseboards.h b/arch/arm/boards/a9m2440/baseboards.h deleted file mode 100644 index be4ae65e82..0000000000 --- a/arch/arm/boards/a9m2440/baseboards.h +++ /dev/null @@ -1,6 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Juergen Beisert - -#ifdef CONFIG_MACH_A9M2410DEV -extern int a9m2410dev_devices_init(void); -#endif diff --git a/arch/arm/boards/a9m2440/config.h b/arch/arm/boards/a9m2440/config.h deleted file mode 100644 index c22ff53036..0000000000 --- a/arch/arm/boards/a9m2440/config.h +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -/** - * @file - * @brief Global defintions for the ARM S3C2440 based a9m2440 CPU card - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/** - * The external clock reference is a 16.9344 MHz crystal - */ -#define S3C24XX_CLOCK_REFERENCE 16934400 - -/** - * Define the main clock configuration to be used in register CLKDIVN - * - * We must limit the frequency of the connected SDRAMs with the clock ratio - * setup to 1:4:8. This will result into FCLK:HCLK:PCLK = 400Mhz:100MHz:50MHz - */ -#define BOARD_SPECIFIC_CLKDIVN 0x05 - -/** - * Define the MPLL configuration to be used in register MPLLCON - * - * We want the MPLL to run at 399.65 MHz - */ -#define BOARD_SPECIFIC_MPLL ((0x6e << 12) + (3 << 4) + 1) - -/** - * Define the UPLL configuration to be used in register UPLLCON - * - * We want the UPLL to run at 47.98 MHz - */ -#define BOARD_SPECIFIC_UPLL ((0x3c << 12) + (4 << 4) + 2) - -/* - * Flash access timings - * Tacls = 0ns (but 20ns data setup time) - * Twrph0 = 25ns (write) 35ns (read) - * Twrph1 = 10ns (10ns data hold time) - * Read cycle time = 50ns - * - * Assumed HCLK is 100MHz - * Tacls = 1 (-> 20ns) - * Twrph0 = 3 (-> 40ns) - * Twrph1 = 1 (-> 20ns) - * Cycle time = 80ns - */ -#define A9M2440_TACLS 1 -#define A9M2440_TWRPH0 3 -#define A9M2440_TWRPH1 1 - -/* needed in the generic NAND boot code only */ -#ifdef CONFIG_S3C_NAND_BOOT -# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1) -#endif - -#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/a9m2440/env/bin/_update b/arch/arm/boards/a9m2440/env/bin/_update deleted file mode 100644 index b10682ece4..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/_update +++ /dev/null @@ -1,34 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/arm/boards/a9m2440/env/bin/boot b/arch/arm/boards/a9m2440/env/bin/boot deleted file mode 100644 index 86e22cf9ff..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/boot +++ /dev/null @@ -1,40 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xnand ]; then - root=nand - kernel=nand -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$root = xnand ]; then - bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" -fi -if [ x$root = xnet ]; then - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" - if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" - else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" - fi -fi - -bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\"" - -bootargs="$bootargs cs89x0_media=rj45 cs89x0_mac=$eth0.ethaddr" - -if [ x$kernel = xnet ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -else - bootm /dev/nand0.kernel.bb -fi - diff --git a/arch/arm/boards/a9m2440/env/bin/init b/arch/arm/boards/a9m2440/env/bin/init deleted file mode 100644 index dd94ef6be0..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/init +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config - -if [ -e /dev/nand0 ]; then - addpart /dev/nand0 $nand_parts -fi - -if [ -z $eth0.ethaddr ]; then - while [ -z $eth0.ethaddr ]; do - readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr - done - echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" -fi - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel [<imagename>] to update kernel into flash" - echo "type update_root [<imagename>] to update rootfs into flash" - echo - exit -fi - -boot diff --git a/arch/arm/boards/a9m2440/env/bin/update_kernel b/arch/arm/boards/a9m2440/env/bin/update_kernel deleted file mode 100644 index c43a55785b..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/update_kernel +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -. /env/config - -part=/dev/nand0.kernel.bb - -if [ x$1 = x ]; then - image=$uimage -else - image=$1 -fi - -. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2440/env/bin/update_root b/arch/arm/boards/a9m2440/env/bin/update_root deleted file mode 100644 index 46cbca5beb..0000000000 --- a/arch/arm/boards/a9m2440/env/bin/update_root +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh - -. /env/config - -part=/dev/nand0.root.bb - -if [ x$1 = x ]; then - image=$jffs2 -else - image=$1 -fi - -. /env/bin/_update $image diff --git a/arch/arm/boards/a9m2440/env/config b/arch/arm/boards/a9m2440/env/config deleted file mode 100644 index d1fb01b731..0000000000 --- a/arch/arm/boards/a9m2440/env/config +++ /dev/null @@ -1,26 +0,0 @@ -#!/bin/sh - -# can be either 'net' or 'nand'' -kernel=net -root=net - -uimage=uImage-a9m2440 -jffs2=root-a9m2440.jffs2 - -autoboot_timeout=3 - -nfsroot="/nfsexport/OSELAS.BSP-Hesch-TMU-1/platform-FS_A9M2440/root" -bootargs="console=ttySAC0,38400" - -nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" -rootpart_nand="/dev/mtdblock3" - -# use 'dhcp' to do dhcp in barebox and in kernel -#ip=dhcp - -# or set your networking parameters here -eth0.ipaddr=192.168.42.32 -eth0.netmask=255.255.0.0 -eth0.gateway=192.168.23.1 -eth0.serverip=192.168.23.2 -#eth0.ethaddr= diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S deleted file mode 100644 index 585863f9d4..0000000000 --- a/arch/arm/boards/a9m2440/lowlevel_init.S +++ /dev/null @@ -1,243 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <config.h> -#include <linux/sizes.h> -#include <mach/s3c-iomap.h> -#include <mach/s3c24xx-gpio.h> -#include <asm/barebox-arm-head.h> - - .section ".text_bare_init.barebox_arm_reset_vector","ax" - -/* - * To be able to setup the SDRAM interface correctly, we need some - * external information about the connected SDRAM devices. - * - * When we set GPH8, we can read at GPB: - * Bit 0..1: Memory device size -> 00=16M, 01=64M, 10=32M, 11=128M - * Bit 2: CL setting - * - * Some remarks: The CL setting seems useless. It always signals a CL3 - * requirement, but the SDRAM types I found on the cards are supporting - * CL2 @ 100 MHz. But also these SDRAM types are only support 105 MHz max. - * So, we never need CL3 because we can't run the CPU at 533 MHz (which - * implies an 133 MHz SDRAM clock). - * All devices are connected via 32 bit databus - * - * Note: I was able to check the 32 MiB and 64 MiB configuration only. I didn't - * had access to a 16 MiB nor 128 MiB config. - * - */ - -sdram_init: - /* - * Read the configuration. After reset until any GPIO port is - * configured yet, these pins show external settings, to detect - * the SDRAM size. - */ - ldr r1, =S3C_GPBDAT - ldr r4, [r1] - and r4, r4, #0x3 - - ldr r1, =S3C_MEMCTL_BASE - /* configure both SDRAM areas with 32 bit data bus width */ - ldr r0, =((0x2 << 24) + (0x2 << 28)) - str r0, [r1], #0x1c /* post add register offset for bank6 */ - - /* - * With the configuration we simply need to calculate an offset into - * our table with the predefined SDRAM settings - */ - adr r0, SDRAMDATA - mov r2, #6*4 /* # of bytes per table entry */ - mul r3, r4, r2 - add r0, r0, r3 /* start address of the entry */ - - /* - * store the table entry data into the registers - */ -1: - ldr r3, [r0], #4 - str r3, [r1], #4 - subs r2, r2, #4 - bne 1b - -/* TODO: Check if the second bank is populated, and switch it off if not */ - - mov pc, lr - -/* - * we need 4 sets of memory settings per main CPU clock speed - * - * 400MHz main speed: - * - 16 MiB in the first bank, maybe 16 MiB in the second bank (untested!) - * - 32 MiB in the first bank, maybe 32 MiB in the second bank (CL=2) - * - 64 MiB in the first bank, maybe 64 MiB in the second bank (CL=2) - * - 128 MiB in the first bank, maybe 128 MiB in the second bank (untested!) - * - * Note: SDRAM clock runs at 100MHz - */ - -SDRAMDATA: -/* --------------------------- 16 MiB @ 100MHz --------------------------- */ - /* - * - MT = 11 (= sync dram type) - * - Trcd = 01 (= CL3) - * - SCAN = 00 (= 8 bit columns) - */ - .word ((0x3 << 15) + (0x1 << 2) + (0x0)) - .word ((0x3 << 15) + (0x1 << 2) + (0x0)) - /* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 11 (= 7 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = FIXME - */ - .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x3 << 18) + 468) - /* - * SDRAM banksize - * - BURST_EN = 0 (= burst mode disabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 010 (= 128MiB) FIXME????? - */ - .word ((0 << 7) + (1 << 5) + (1 << 4) + 2) - /* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ - .word (0x2 << 4) - .word (0x2 << 4) - -/* ------------- one or two banks with 64 MiB @ 100MHz -------------------- */ - - /* - * - MT = 11 (= sync dram type) - * - Trcd = 00 (= CL2) - * - SCAN = 01 (= 9 bit columns) - */ - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - /* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 - */ - .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) - /* - * SDRAM banksize - * - BURST_EN = 1 (= burst mode enabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 001 (= 64 MiB) - */ - .word ((1 << 7) + (1 << 5) + (1 << 4) + 1) - /* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ - .word (0x2 << 4) - .word (0x2 << 4) - -/* ------------- one or two banks with 32 MiB @ 100MHz -------------------- */ - - /* - * - MT = 11 (= sync dram type) - * - Trcd = 00 (= CL2) - * - SCAN = 01 (= 9 bit columns) - */ - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - /* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 15.6 = 2049 - 1560 = 489 - */ - .word ((0x1 << 23) + (0x0 << 22) + (0x0 << 20) + (0x1 << 18) + 489) - /* - * SDRAM banksize - * - BURST_EN = 1 (= burst mode enabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 000 (= 32 MiB) - */ - .word ((1 << 7) + (1 << 5) + (1 << 4) + 0) - /* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ - .word (0x2 << 4) - .word (0x2 << 4) - -/* ------------ one or two banks with 128 MiB @ 100MHz -------------------- */ - - /* - * - MT = 11 (= sync dram type) - * - Trcd = 00 (= CL2) - * - SCAN = 01 (= 9 bit columns) - */ - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - .word ((0x3 << 15) + (0x0 << 2) + (0x1)) - /* - * SDRAM refresh settings - * - REFEN = 1 (= refresh enabled) - * - TREFMD = 0 (= auto refresh) - * - Trp = 00 (= 2 RAS precharge clocks) - * - Tsrc = 01 (= 5 clocks -> row cycle time @100MHz 2+5=7 -> 70ns) - * - Refrsh = 2^11 + 1 - 100 * 7.5 = 2049 - FIXME = 1259 - */ - .word ((0x1 << 23) + (0x0 << 22) + (0x1 << 20) + (0x3 << 18) + 1259) - /* - * SDRAM banksize - * - BURST_EN = 0 (= burst mode disabled) - * - SCKE_EN = 1 (= SDRAM SCKE enabled) - * - SCLK_EN = 1 (= clock active only during accesses) - * - BK67MAP = 010 (= 128MiB) - */ - .word (0x32) - /* - * SDRAM mode register - * CL = 010 (= 2 clocks) - */ - .word (0x2 << 4) - .word (0x2 << 4) - -/* ------------------------------------------------------------------------ */ - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - - bl arm_cpu_lowlevel_init - - bl s3c24x0_disable_wd - - /* skip everything here if we are already running from SDRAM */ - cmp pc, #S3C_SDRAM_BASE - blo 1f - cmp pc, #S3C_SDRAM_END - bhs 1f - - b out - -/* we are running from NOR or NAND/SRAM memory. Do further initialisation */ -1: - bl s3c24x0_pll_init - - bl sdram_init - -#ifdef CONFIG_S3C_NAND_BOOT -/* up to here we are running from the internal SRAM area */ - bl s3c24x0_nand_boot -#endif -out: - mov r0, #S3C_SDRAM_BASE - mov r1, #SZ_32M - mov r2, #0 - b barebox_arm_entry |